[PATCH] D43055: [RISCV] Implement MC relaxations for compressed instructions.

Alex Bradbury via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Feb 27 15:09:33 PST 2018

asb added a comment.
Herald added a subscriber: shiva0217.

Is it possible to add tests for this?

Comment at: lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp:118
+  case RISCV::C_BEQZ:
+    // beq    $rs1, $rs2, $imm12.
+    Res.setOpcode(RISCV::BEQ);
It would be clearer to just have the comment summarise the transform. e.g.:
// c.beqz $rs1, $imm -> beq $rs1, x0, $imm

And similar for other cases

Comment at: lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp:153-158
+    return (unsigned)RISCV::BEQ;
+  case RISCV::C_BNEZ:
+    return (unsigned)RISCV::BNE;
+  case RISCV::C_J:
+  case RISCV::C_JAL: // fall through.
+    return (unsigned)RISCV::JAL;
Surely these (unsigned) casts are unnecessary?


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