[llvm] r326153 - [SelectionDAG] Remove code from PromoteIntRes_CONCAT_VECTORS that was added in r320674 to help X86.

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Mon Feb 26 16:07:24 PST 2018


Author: ctopper
Date: Mon Feb 26 16:07:24 2018
New Revision: 326153

URL: http://llvm.org/viewvc/llvm-project?rev=326153&view=rev
Log:
[SelectionDAG] Remove code from PromoteIntRes_CONCAT_VECTORS that was added in r320674 to help X86.

AVX512 used to promote v32i1 to v32i8 during legalization when BWI was disabled. So this code was added to improve legalization of v32i1 concat_vectors of v16i1 by extending the v16i1 to v16i8 to avoid scalarization.

X86 has since switched to legalizing v32i1 by splitting to v16i1 instead. This has rendered this code unnecessary and its no longer exercised.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=326153&r1=326152&r2=326153&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Mon Feb 26 16:07:24 2018
@@ -3488,21 +3488,6 @@ SDValue DAGTypeLegalizer::PromoteIntRes_
   assert(NumElem * NumOperands == NumOutElem &&
          "Unexpected number of elements");
 
-  // If the input type is legal and we can promote it to a legal type with the
-  // same element size, go ahead do that to create a new concat.
-  if (getTypeAction(N->getOperand(0).getValueType()) ==
-      TargetLowering::TypeLegal) {
-    EVT InPromotedTy = EVT::getVectorVT(*DAG.getContext(), OutElemTy, NumElem);
-    if (TLI.isTypeLegal(InPromotedTy)) {
-      SmallVector<SDValue, 8> Ops(NumOperands);
-      for (unsigned i = 0; i < NumOperands; ++i) {
-        Ops[i] = DAG.getNode(ISD::ANY_EXTEND, dl, InPromotedTy,
-                             N->getOperand(i));
-      }
-      return DAG.getNode(ISD::CONCAT_VECTORS, dl, NOutVT, Ops);
-    }
-  }
-
   // Take the elements from the first vector.
   SmallVector<SDValue, 8> Ops(NumOutElem);
   for (unsigned i = 0; i < NumOperands; ++i) {




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