[PATCH] D43682: [mips] Support 'z' inline asm constraint

[Simon Dardis via Phabricator via llvm-commits]

sdardis requested changes to this revision.
sdardis added a comment.
This revision now requires changes to proceed.

Reading and writing to the fcc register set directly is somewhat cumbersome, in that we have to perform mask and shift operations or bit insertions. If that constraint can allocate any fcc register it will probably require some sort of pseudo instruction to generate the correct sequence.



================
Comment at: lib/Target/Mips/MipsISelLowering.cpp:3655
       case 'x':
+      case 'z':
         return C_RegisterClass;
----------------
Document the constraint in the above comment.


================
Comment at: lib/Target/Mips/MipsSEInstrInfo.cpp:106-107
       Opc = Mips::MFLO_DSP;
+    else if (Mips::FCCRegClass.contains(SrcReg))
+      Opc = Mips::CFC1;
     else if (Mips::DSPCCRegClass.contains(SrcReg)) {
----------------
This is insufficient to read a particular fcc register. cfc1 and ctc1 operate on the float point control registers, not the fcc register set. The $fcsr register or the $fccr register can used to read/write the entire set of $fcc registers (i'd suggest the $fccr / $25). You then have to mask off the non-relevant bits.

Additionally, it may require a pseudo instruction which uses a scratch GPR and is expanded post register allocation to make the correct sequence if any other register that $fcc0 is used.


================
Comment at: test/CodeGen/Mips/inlineasm_constraint_z.ll:1
+; RUN: llc -march=mips < %s | FileCheck %s
+
----------------
This need -verify-machineinstrs, also use -mtriple=mips-unknown-linux-gnu and use the update_llc_checks script.


Repository:
  rL LLVM

https://reviews.llvm.org/D43682