[llvm] r326065 - [X86] Use SelectionDAG::SplitVectorOperand to simplify some code. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 25 18:16:34 PST 2018
Author: ctopper
Date: Sun Feb 25 18:16:34 2018
New Revision: 326065
URL: http://llvm.org/viewvc/llvm-project?rev=326065&view=rev
Log:
[X86] Use SelectionDAG::SplitVectorOperand to simplify some code. NFC
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=326065&r1=326064&r2=326065&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Feb 25 18:16:34 2018
@@ -25134,13 +25134,9 @@ void X86TargetLowering::ReplaceNodeResul
// we can split using the k-register rather than memory.
if (SrcVT == MVT::v64i1 && DstVT == MVT::i64 && Subtarget.hasBWI()) {
assert(!Subtarget.is64Bit() && "Expected 32-bit mode");
- SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v32i1,
- N->getOperand(0),
- DAG.getIntPtrConstant(0, dl));
+ SDValue Lo, Hi;
+ std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
Lo = DAG.getBitcast(MVT::i32, Lo);
- SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v32i1,
- N->getOperand(0),
- DAG.getIntPtrConstant(32, dl));
Hi = DAG.getBitcast(MVT::i32, Hi);
SDValue Res = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
Results.push_back(Res);
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