[PATCH] D41949: [RISCV] implement li pseudo instruction

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Missing testcase for "li a0, foo".



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Comment at: lib/Target/RISCV/RISCVInstrInfo.td:401
+// PseudoLI is probably not the best idea anyway given that up to
+// 8 32-bit instructions are needed to generate an arbitrary 64-bit immediate.
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 8,
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I'm not sure it's a good idea to make code generation use this pseudo-instruction; you'll miss optimization opportunities, like MachineCSE of lui instructions.


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Comment at: test/MC/RISCV/rv64i-aliases-valid.s:94
+# CHECK-EXPAND: addi t4, t4, -272
+li t4, 0x123456789abcdef0
+# CHECK-EXPAND: addiw t5, zero, -1
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This seems a little unfortunate... given you can load an arbitrary 32-bit immediate in two instructions, you should be able to load a 64-bit immediate in six instructions ("hi << 32 | lo").  But I guess that requires a second register?


https://reviews.llvm.org/D41949