[llvm] r325782 - [mips] Generate memory dependencies for byVal arguments

Stefan Maksimovic via llvm-commits llvm-commits at lists.llvm.org
Thu Feb 22 05:40:42 PST 2018


Author: smaksimovic
Date: Thu Feb 22 05:40:42 2018
New Revision: 325782

URL: http://llvm.org/viewvc/llvm-project?rev=325782&view=rev
Log:
[mips] Generate memory dependencies for byVal arguments

There were no memory dependencies made between stores generated
when lowering formal arguments and loads generated when
call lowering byVal arguments which made the Post-RA scheduler
place a load before a matching store.

Make the fixed object stored to mutable so that the load
instructions can have their memory dependencies added

Set the frame object as isAliased which clears the underlying
objects vector in ScheduleDAGInstrs::buildSchedGraph().
This results in addition of all stores as dependenies for loads.

This problem appeared when passing a byVal parameter
coupled with a fastcc function call.

Differential Revision: https://reviews.llvm.org/D37515

Added:
    llvm/trunk/test/CodeGen/Mips/fastcc_byval.ll
Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
    llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=325782&r1=325781&r2=325782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Thu Feb 22 05:40:42 2018
@@ -4063,7 +4063,12 @@ void MipsTargetLowering::copyByValRegs(
 
   // Create frame object.
   EVT PtrTy = getPointerTy(DAG.getDataLayout());
-  int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, true);
+  // Make the fixed object stored to mutable so that the load instructions
+  // referencing it have their memory dependencies added.
+  // Set the frame object as isAliased which clears the underlying objects
+  // vector in ScheduleDAGInstrs::buildSchedGraph() resulting in addition of all
+  // stores as dependencies for loads referencing this fixed object.
+  int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, false, true);
   SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
   InVals.push_back(FIN);
 

Added: llvm/trunk/test/CodeGen/Mips/fastcc_byval.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fastcc_byval.ll?rev=325782&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/fastcc_byval.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/fastcc_byval.ll Thu Feb 22 05:40:42 2018
@@ -0,0 +1,27 @@
+; RUN: llc -mtriple=mipsel-linux-gnu -O3 -relocation-model=pic < %s | FileCheck %s
+
+; Test that a load comes after a store to the same memory location when passing
+; a byVal parameter to a function which has a fastcc function call
+
+%struct.str = type { i32, i32, [3 x i32*] }
+
+declare fastcc void @_Z1F3str(%struct.str* noalias nocapture sret %agg.result, %struct.str* byval nocapture readonly align 4 %s)
+
+define i32 @_Z1g3str(%struct.str* byval nocapture readonly align 4 %s) {
+; CHECK-LABEL: _Z1g3str:
+; CHECK: sw  $7, [[OFFSET:[0-9]+]]($sp)
+; CHECK: lw  ${{[0-9]+}}, [[OFFSET]]($sp)
+entry:
+  %ref.tmp = alloca %struct.str, align 4
+  %0 = bitcast %struct.str* %ref.tmp to i8*
+  call void @llvm.lifetime.start.p0i8(i64 20, i8* nonnull %0)
+  call fastcc void @_Z1F3str(%struct.str* nonnull sret %ref.tmp, %struct.str* byval nonnull align 4 %s)
+  %cl.sroa.3.0..sroa_idx2 = getelementptr inbounds %struct.str, %struct.str* %ref.tmp, i32 0, i32 1
+  %cl.sroa.3.0.copyload = load i32, i32* %cl.sroa.3.0..sroa_idx2, align 4
+  call void @llvm.lifetime.end.p0i8(i64 20, i8* nonnull %0)
+  ret i32 %cl.sroa.3.0.copyload
+}
+
+declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture)
+
+declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture)

Modified: llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll?rev=325782&r1=325781&r2=325782&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll Thu Feb 22 05:40:42 2018
@@ -243,10 +243,9 @@ define void @f5(i64 %a0, %struct.S4* noc
 ; CHECK-NEXT:    lw $7, 52($sp)
 ; CHECK-NEXT:    lw $6, 48($sp)
 ; CHECK-NEXT:    lw $5, 44($sp)
-; CHECK-NEXT:    lw $4, 40($sp)
 ; CHECK-NEXT:    lw $25, %call16(f6)($gp)
 ; CHECK-NEXT:    jalr $25
-; CHECK-NEXT:    nop
+; CHECK-NEXT:    lw $4, 40($sp)
 ; CHECK-NEXT:    lw $ra, 28($sp) # 4-byte Folded Reload
 ; CHECK-NEXT:    jr $ra
 ; CHECK-NEXT:    addiu $sp, $sp, 32




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