[PATCH] D42647: AMDGPU: Track physreg uses in SILoadStoreOptimizer

[Marek Olšák via Phabricator via llvm-commits]

mareko added inline comments.


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Comment at: test/CodeGen/AMDGPU/smrd.ll:258
 ;
-; GCN: s_buffer_load_dword
-; GCN: s_buffer_load_dword
-define amdgpu_ps float @smrd_imm_nomerge_m0(<4 x i32> inreg %desc, i32 inreg %prim, float %u, float %v) #0 {
+; Merging is still thwarted on GFX9 due to s_set_gpr_idx
+;
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mareko wrote:
> Merging of these copcodes is disabled on GFX9 because of the cache line straddling bug.
Note that merging buffer loads is fully enabled on GFX9 now. See git commit ea06ecf3436ea455a7f304095ebf7f4f4ec989f3 .


Repository:
  rL LLVM

https://reviews.llvm.org/D42647