[llvm] r324110 - [AArch64][GlobalISel] Use getRegClassForTypeOnBank() in selectCopy.

[Hans Wennborg via llvm-commits]

Merged to 6.0 in r325584 (to be able to merge r325463 etc.).

On Fri, Feb 2, 2018 at 7:03 PM, Amara Emerson via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Author: aemerson
> Date: Fri Feb  2 10:03:30 2018
> New Revision: 324110
>
> URL: http://llvm.org/viewvc/llvm-project?rev=324110&view=rev
> Log:
> [AArch64][GlobalISel] Use getRegClassForTypeOnBank() in selectCopy.
>
> Differential Revision: https://reviews.llvm.org/D42832
>
> Modified:
>     llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=324110&r1=324109&r2=324110&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Fri Feb  2 10:03:30 2018
> @@ -135,16 +135,21 @@ AArch64InstructionSelector::AArch64Instr
>  // for each class in the bank.
>  static const TargetRegisterClass *
>  getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB,
> -                         const RegisterBankInfo &RBI) {
> +                         const RegisterBankInfo &RBI,
> +                         bool GetAllRegSet = false) {
>    if (RB.getID() == AArch64::GPRRegBankID) {
>      if (Ty.getSizeInBits() <= 32)
> -      return &AArch64::GPR32RegClass;
> +      return GetAllRegSet ? &AArch64::GPR32allRegClass
> +                          : &AArch64::GPR32RegClass;
>      if (Ty.getSizeInBits() == 64)
> -      return &AArch64::GPR64RegClass;
> +      return GetAllRegSet ? &AArch64::GPR64allRegClass
> +                          : &AArch64::GPR64RegClass;
>      return nullptr;
>    }
>
>    if (RB.getID() == AArch64::FPRRegBankID) {
> +    if (Ty.getSizeInBits() <= 16)
> +      return &AArch64::FPR16RegClass;
>      if (Ty.getSizeInBits() == 32)
>        return &AArch64::FPR32RegClass;
>      if (Ty.getSizeInBits() == 64)
> @@ -324,6 +329,7 @@ static bool selectCopy(MachineInstr &I,
>
>    const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
>    const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
> +  (void)DstSize;
>    unsigned SrcReg = I.getOperand(1).getReg();
>    const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
>    (void)SrcSize;
> @@ -342,26 +348,12 @@ static bool selectCopy(MachineInstr &I,
>        "Copy with different width?!");
>    assert((DstSize <= 64 || RegBank.getID() == AArch64::FPRRegBankID) &&
>           "GPRs cannot get more than 64-bit width values");
> -  const TargetRegisterClass *RC = nullptr;
>
> -  if (RegBank.getID() == AArch64::FPRRegBankID) {
> -    if (DstSize <= 16)
> -      RC = &AArch64::FPR16RegClass;
> -    else if (DstSize <= 32)
> -      RC = &AArch64::FPR32RegClass;
> -    else if (DstSize <= 64)
> -      RC = &AArch64::FPR64RegClass;
> -    else if (DstSize <= 128)
> -      RC = &AArch64::FPR128RegClass;
> -    else {
> -      DEBUG(dbgs() << "Unexpected bitcast size " << DstSize << '\n');
> -      return false;
> -    }
> -  } else {
> -    assert(RegBank.getID() == AArch64::GPRRegBankID &&
> -           "Bitcast for the flags?");
> -    RC =
> -        DstSize <= 32 ? &AArch64::GPR32allRegClass : &AArch64::GPR64allRegClass;
> +  const TargetRegisterClass *RC = getRegClassForTypeOnBank(
> +      MRI.getType(DstReg), RegBank, RBI, /* GetAllRegSet */ true);
> +  if (!RC) {
> +    DEBUG(dbgs() << "Unexpected bitcast size " << DstSize << '\n');
> +    return false;
>    }
>
>    // No need to constrain SrcReg. It will get constrained when
>
>
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