[PATCH] D36104: [AArch64] Coalesce Copy Zero during instruction selection

[Haicheng Wu via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL325459: [AArch64] Coalesce Copy Zero during instruction selection (authored by haicheng, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D36104?vs=120601&id=134832#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D36104

Files:
  llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/trunk/test/CodeGen/AArch64/arm64-addr-type-promotion.ll
  llvm/trunk/test/CodeGen/AArch64/arm64-cse.ll
  llvm/trunk/test/CodeGen/AArch64/copy-zero-reg.ll
  llvm/trunk/test/CodeGen/AArch64/i128-fast-isel-fallback.ll

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