[llvm] r325457 - [BPF] Return true in enableMultipleCopyHints().
Jonas Paulsson via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 18 02:09:55 PST 2018
Author: jonpa
Date: Sun Feb 18 02:09:54 2018
New Revision: 325457
URL: http://llvm.org/viewvc/llvm-project?rev=325457&view=rev
Log:
[BPF] Return true in enableMultipleCopyHints().
Enable multiple COPY hints to eliminate more COPYs during register allocation.
Note that this is something all targets should do, see
https://reviews.llvm.org/D38128.
Review: Yonghong Song
Modified:
llvm/trunk/lib/Target/BPF/BPFRegisterInfo.h
llvm/trunk/test/CodeGen/BPF/alu8.ll
llvm/trunk/test/CodeGen/BPF/basictest.ll
llvm/trunk/test/CodeGen/BPF/cmp.ll
llvm/trunk/test/CodeGen/BPF/dwarfdump.ll
llvm/trunk/test/CodeGen/BPF/intrinsics.ll
llvm/trunk/test/CodeGen/BPF/objdump_intrinsics.ll
llvm/trunk/test/CodeGen/BPF/remove_truncate_3.ll
llvm/trunk/test/CodeGen/BPF/sanity.ll
llvm/trunk/test/CodeGen/BPF/shifts.ll
Modified: llvm/trunk/lib/Target/BPF/BPFRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/BPF/BPFRegisterInfo.h?rev=325457&r1=325456&r2=325457&view=diff
==============================================================================
--- llvm/trunk/lib/Target/BPF/BPFRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/BPF/BPFRegisterInfo.h Sun Feb 18 02:09:54 2018
@@ -29,6 +29,8 @@ struct BPFRegisterInfo : public BPFGenRe
BitVector getReservedRegs(const MachineFunction &MF) const override;
+ bool enableMultipleCopyHints() const override { return true; }
+
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
unsigned FIOperandNum,
RegScavenger *RS = nullptr) const override;
Modified: llvm/trunk/test/CodeGen/BPF/alu8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/BPF/alu8.ll?rev=325457&r1=325456&r2=325457&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/BPF/alu8.ll (original)
+++ llvm/trunk/test/CodeGen/BPF/alu8.ll Sun Feb 18 02:09:54 2018
@@ -9,22 +9,22 @@ define i8 @mov(i8 %a, i8 %b) nounwind {
define i8 @add(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: add:
-; CHECK: r1 += r2 # encoding: [0x0f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
; CHECK: r0 = r1 # encoding: [0xbf,0x10,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r0 += r2 # encoding: [0x0f,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
%1 = add i8 %a, %b
ret i8 %1
}
define i8 @and(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: and:
-; CHECK: r1 &= r2 # encoding: [0x5f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r0 &= r2 # encoding: [0x5f,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
%1 = and i8 %a, %b
ret i8 %1
}
define i8 @bis(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: bis:
-; CHECK: r1 |= r2 # encoding: [0x4f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r0 |= r2 # encoding: [0x4f,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
%1 = or i8 %a, %b
ret i8 %1
}
@@ -39,7 +39,7 @@ define i8 @xorand(i8 %a, i8 %b) nounwind
define i8 @xor(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: xor:
-; CHECK: r1 ^= r2 # encoding: [0xaf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r0 ^= r2 # encoding: [0xaf,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
%1 = xor i8 %a, %b
ret i8 %1
}
Modified: llvm/trunk/test/CodeGen/BPF/basictest.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/BPF/basictest.ll?rev=325457&r1=325456&r2=325457&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/BPF/basictest.ll (original)
+++ llvm/trunk/test/CodeGen/BPF/basictest.ll Sun Feb 18 02:09:54 2018
@@ -4,7 +4,7 @@ define i32 @test0(i32 %X) {
%tmp.1 = add i32 %X, 1
ret i32 %tmp.1
; CHECK-LABEL: test0:
-; CHECK: r1 += 1
+; CHECK: r0 += 1
}
; CHECK-LABEL: store_imm:
Modified: llvm/trunk/test/CodeGen/BPF/cmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/BPF/cmp.ll?rev=325457&r1=325456&r2=325457&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/BPF/cmp.ll (original)
+++ llvm/trunk/test/CodeGen/BPF/cmp.ll Sun Feb 18 02:09:54 2018
@@ -17,7 +17,7 @@ define signext i8 @foo_cmp1(i8 signext %
%.0 = phi i8 [ %3, %2 ], [ %5, %4 ]
ret i8 %.0
; CHECK-LABEL:foo_cmp1:
-; CHECK: if r2 s>= r1
+; CHECK: if r0 s>= r1
}
; Function Attrs: nounwind readnone uwtable
@@ -37,7 +37,7 @@ define signext i8 @foo_cmp2(i8 signext %
%.0 = phi i8 [ %3, %2 ], [ %5, %4 ]
ret i8 %.0
; CHECK-LABEL:foo_cmp2:
-; CHECK: if r2 s> r1
+; CHECK: if r0 s> r1
}
; Function Attrs: nounwind readnone uwtable
@@ -57,7 +57,7 @@ define signext i8 @foo_cmp3(i8 signext %
%.0 = phi i8 [ %3, %2 ], [ %5, %4 ]
ret i8 %.0
; CHECK-LABEL:foo_cmp3:
-; CHECK: if r1 s>= r2
+; CHECK: if r1 s>= r0
}
; Function Attrs: nounwind readnone uwtable
@@ -77,7 +77,7 @@ define signext i8 @foo_cmp4(i8 signext %
%.0 = phi i8 [ %3, %2 ], [ %5, %4 ]
ret i8 %.0
; CHECK-LABEL:foo_cmp4:
-; CHECK: if r1 s> r2
+; CHECK: if r1 s> r0
}
; Function Attrs: nounwind readnone uwtable
@@ -86,9 +86,9 @@ define signext i8 @min(i8 signext %a, i8
%a.b = select i1 %1, i8 %a, i8 %b
ret i8 %a.b
; CHECK-LABEL:min:
-; CHECK: if r2 s> r1
-; CHECK: r1 = r2
; CHECK: r0 = r1
+; CHECK: if r2 s> r0
+; CHECK: r0 = r2
}
; Function Attrs: nounwind readnone uwtable
@@ -106,7 +106,7 @@ define signext i8 @max(i8 signext %a, i8
%a.b = select i1 %1, i8 %a, i8 %b
ret i8 %a.b
; CHECK-LABEL:max:
-; CHECK: if r1 s> r2
+; CHECK: if r0 s> r2
}
; Function Attrs: nounwind readnone uwtable
Modified: llvm/trunk/test/CodeGen/BPF/dwarfdump.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/BPF/dwarfdump.ll?rev=325457&r1=325456&r2=325457&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/BPF/dwarfdump.ll (original)
+++ llvm/trunk/test/CodeGen/BPF/dwarfdump.ll Sun Feb 18 02:09:54 2018
@@ -61,4 +61,4 @@ attributes #1 = { nounwind readnone }
; CHECK: file_names[ 1] 0 0x00000000 0x00000000 "testprog.c"
; CHECK: 0x0000000000000000 2
-; CHECK: 0x0000000000000020 7
+; CHECK: 0x0000000000000028 7
Modified: llvm/trunk/test/CodeGen/BPF/intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/BPF/intrinsics.ll?rev=325457&r1=325456&r2=325457&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/BPF/intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/BPF/intrinsics.ll Sun Feb 18 02:09:54 2018
@@ -83,15 +83,15 @@ entry:
ret i32 %conv5
; CHECK-LABEL: bswap:
; CHECK-EL: r1 = be64 r1 # encoding: [0xdc,0x01,0x00,0x00,0x40,0x00,0x00,0x00]
-; CHECK-EL: r2 = be32 r2 # encoding: [0xdc,0x02,0x00,0x00,0x20,0x00,0x00,0x00]
-; CHECK-EL: r2 += r1 # encoding: [0x0f,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK-EL: r0 = be32 r0 # encoding: [0xdc,0x00,0x00,0x00,0x20,0x00,0x00,0x00]
+; CHECK-EL: r0 += r1 # encoding: [0x0f,0x10,0x00,0x00,0x00,0x00,0x00,0x00]
; CHECK-EL: r3 = be16 r3 # encoding: [0xdc,0x03,0x00,0x00,0x10,0x00,0x00,0x00]
-; CHECK-EL: r2 += r3 # encoding: [0x0f,0x32,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK-EL: r0 += r3 # encoding: [0x0f,0x30,0x00,0x00,0x00,0x00,0x00,0x00]
; CHECK-EB: r1 = le64 r1 # encoding: [0xd4,0x10,0x00,0x00,0x00,0x00,0x00,0x40]
-; CHECK-EB: r2 = le32 r2 # encoding: [0xd4,0x20,0x00,0x00,0x00,0x00,0x00,0x20]
-; CHECK-EB: r2 += r1 # encoding: [0x0f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK-EB: r0 = le32 r0 # encoding: [0xd4,0x00,0x00,0x00,0x00,0x00,0x00,0x20]
+; CHECK-EB: r0 += r1 # encoding: [0x0f,0x01,0x00,0x00,0x00,0x00,0x00,0x00]
; CHECK-EB: r3 = le16 r3 # encoding: [0xd4,0x30,0x00,0x00,0x00,0x00,0x00,0x10]
-; CHECK-EB: r2 += r3 # encoding: [0x0f,0x23,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK-EB: r0 += r3 # encoding: [0x0f,0x03,0x00,0x00,0x00,0x00,0x00,0x00]
}
declare i64 @llvm.bswap.i64(i64) #1
Modified: llvm/trunk/test/CodeGen/BPF/objdump_intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/BPF/objdump_intrinsics.ll?rev=325457&r1=325456&r2=325457&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/BPF/objdump_intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/BPF/objdump_intrinsics.ll Sun Feb 18 02:09:54 2018
@@ -83,15 +83,15 @@ entry:
ret i32 %conv5
; CHECK-LABEL: bswap:
; CHECK-EL: r1 = be64 r1
-; CHECK-EL: r2 = be32 r2
-; CHECK-EL: r2 += r1
+; CHECK-EL: r0 = be32 r0
+; CHECK-EL: r0 += r1
; CHECK-EL: r3 = be16 r3
-; CHECK-EL: r2 += r3
+; CHECK-EL: r0 += r3
; CHECK-EB: r1 = le64 r1
-; CHECK-EB: r2 = le32 r2
-; CHECK-EB: r2 += r1
+; CHECK-EB: r0 = le32 r0
+; CHECK-EB: r0 += r1
; CHECK-EB: r3 = le16 r3
-; CHECK-EB: r2 += r3
+; CHECK-EB: r0 += r3
}
declare i64 @llvm.bswap.i64(i64) #1
Modified: llvm/trunk/test/CodeGen/BPF/remove_truncate_3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/BPF/remove_truncate_3.ll?rev=325457&r1=325456&r2=325457&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/BPF/remove_truncate_3.ll (original)
+++ llvm/trunk/test/CodeGen/BPF/remove_truncate_3.ll Sun Feb 18 02:09:54 2018
@@ -91,13 +91,13 @@ define i32 @xdp_dummy(%struct.xdp_md* no
; Function Attrs: norecurse nounwind readnone
define i32 @rol32(i32, i32) local_unnamed_addr #1 {
%3 = shl i32 %0, %1
-; CHECK: r3 <<= 32
-; CHECK: r3 >>= 32
+; CHECK: r1 <<= 32
+; CHECK: r1 >>= 32
%4 = sub i32 0, %1
%5 = and i32 %4, 31
%6 = lshr i32 %0, %5
-; CHECK: r1 <<= 32
-; CHECK: r1 >>= 32
+; CHECK: r0 <<= 32
+; CHECK: r0 >>= 32
%7 = or i32 %6, %3
ret i32 %7
}
Modified: llvm/trunk/test/CodeGen/BPF/sanity.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/BPF/sanity.ll?rev=325457&r1=325456&r2=325457&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/BPF/sanity.ll (original)
+++ llvm/trunk/test/CodeGen/BPF/sanity.ll Sun Feb 18 02:09:54 2018
@@ -7,7 +7,7 @@ define i32 @foo_int(i32 %a, i32 %b) #0 {
%1 = add nsw i32 %b, %a
ret i32 %1
; CHECK-LABEL: foo_int:
-; CHECK: r2 += r1
+; CHECK: r0 += r1
}
; Function Attrs: nounwind readnone uwtable
@@ -15,9 +15,9 @@ define signext i8 @foo_char(i8 signext %
%1 = add i8 %b, %a
ret i8 %1
; CHECK-LABEL: foo_char:
-; CHECK: r2 += r1
-; CHECK: r2 <<= 56
-; CHECK: r2 s>>= 56
+; CHECK: r0 += r1
+; CHECK: r0 <<= 56
+; CHECK: r0 s>>= 56
}
; Function Attrs: nounwind readnone uwtable
@@ -26,9 +26,9 @@ define i64 @foo_ll(i64 %a, i64 %b, i64 %
%2 = sub i64 %1, %c
ret i64 %2
; CHECK-LABEL: foo_ll:
-; CHECK: r2 += r1
-; CHECK: r2 -= r3
; CHECK: r0 = r2
+; CHECK: r0 += r1
+; CHECK: r0 -= r3
}
; Function Attrs: nounwind uwtable
@@ -60,7 +60,7 @@ define signext i8 @foo_cmp(i8 signext %a
%a.b = select i1 %1, i8 %a, i8 %b
ret i8 %a.b
; CHECK-LABEL: foo_cmp:
-; CHECK: if r2 s> r1
+; CHECK: if r2 s> r0
}
; Function Attrs: nounwind readnone uwtable
@@ -82,7 +82,7 @@ define i32 @foo_muldiv(i8 signext %a, i1
%.0 = phi i32 [ %4, %2 ], [ %7, %5 ]
ret i32 %.0
; CHECK-LABEL: foo_muldiv:
-; CHECK: r2 *= r3
+; CHECK: r0 *= r3
}
; Function Attrs: nounwind uwtable
Modified: llvm/trunk/test/CodeGen/BPF/shifts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/BPF/shifts.ll?rev=325457&r1=325456&r2=325457&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/BPF/shifts.ll (original)
+++ llvm/trunk/test/CodeGen/BPF/shifts.ll Sun Feb 18 02:09:54 2018
@@ -3,7 +3,7 @@
define zeroext i8 @lshr8(i8 zeroext %a, i8 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: lshr8:
-; CHECK: r1 >>= r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r0 >>= r2 # encoding: [0x7f,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
%shr = lshr i8 %a, %cnt
ret i8 %shr
}
@@ -11,7 +11,7 @@ entry:
define signext i8 @ashr8(i8 signext %a, i8 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: ashr8:
-; CHECK: r1 s>>= r2 # encoding: [0xcf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r0 s>>= r2 # encoding: [0xcf,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
%shr = ashr i8 %a, %cnt
ret i8 %shr
}
@@ -19,7 +19,7 @@ entry:
define zeroext i8 @shl8(i8 zeroext %a, i8 zeroext %cnt) nounwind readnone {
entry:
; CHECK: shl8
-; CHECK: r1 <<= r2 # encoding: [0x6f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r0 <<= r2 # encoding: [0x6f,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
%shl = shl i8 %a, %cnt
ret i8 %shl
}
@@ -27,7 +27,7 @@ entry:
define zeroext i16 @lshr16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: lshr16:
-; CHECK: r1 >>= r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r0 >>= r2 # encoding: [0x7f,0x20,0x00,0x00,0x00,0x00,0x00,0x00
%shr = lshr i16 %a, %cnt
ret i16 %shr
}
@@ -35,7 +35,7 @@ entry:
define signext i16 @ashr16(i16 signext %a, i16 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: ashr16:
-; CHECK: r1 s>>= r2 # encoding: [0xcf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r0 s>>= r2 # encoding: [0xcf,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
%shr = ashr i16 %a, %cnt
ret i16 %shr
}
@@ -43,7 +43,7 @@ entry:
define zeroext i16 @shl16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: shl16:
-; CHECK: r1 <<= r2 # encoding: [0x6f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r0 <<= r2 # encoding: [0x6f,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
%shl = shl i16 %a, %cnt
ret i16 %shl
}
@@ -51,8 +51,8 @@ entry:
define zeroext i32 @lshr32(i32 zeroext %a, i32 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: lshr32:
-; CHECK: r1 >>= r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
-; CHECK: r1 <<= 32 # encoding: [0x67,0x01,0x00,0x00,0x20,0x00,0x00,0x00]
+; CHECK: r0 >>= r2 # encoding: [0x7f,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r0 <<= 32 # encoding: [0x67,0x00,0x00,0x00,0x20,0x00,0x00,0x00]
%shr = lshr i32 %a, %cnt
ret i32 %shr
}
@@ -60,7 +60,7 @@ entry:
define signext i32 @ashr32(i32 signext %a, i32 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: ashr32:
-; CHECK: r1 s>>= r2 # encoding: [0xcf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r0 s>>= r2 # encoding: [0xcf,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
%shr = ashr i32 %a, %cnt
ret i32 %shr
}
@@ -68,7 +68,7 @@ entry:
define zeroext i32 @shl32(i32 zeroext %a, i32 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: shl32:
-; CHECK: r1 <<= r2 # encoding: [0x6f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r0 <<= r2 # encoding: [0x6f,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
%shl = shl i32 %a, %cnt
ret i32 %shl
}
@@ -76,7 +76,7 @@ entry:
define zeroext i64 @lshr64(i64 zeroext %a, i64 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: lshr64:
-; CHECK: r1 >>= r2 # encoding: [0x7f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r0 >>= r2 # encoding: [0x7f,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
%shr = lshr i64 %a, %cnt
ret i64 %shr
}
@@ -84,7 +84,7 @@ entry:
define signext i64 @ashr64(i64 signext %a, i64 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: ashr64:
-; CHECK: r1 s>>= r2 # encoding: [0xcf,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r0 s>>= r2 # encoding: [0xcf,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
%shr = ashr i64 %a, %cnt
ret i64 %shr
}
@@ -92,8 +92,8 @@ entry:
define zeroext i64 @shl64(i64 zeroext %a, i64 zeroext %cnt) nounwind readnone {
entry:
; CHECK-LABEL: shl64:
-; CHECK: r1 <<= r2 # encoding: [0x6f,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
; CHECK: r0 = r1 # encoding: [0xbf,0x10,0x00,0x00,0x00,0x00,0x00,0x00]
+; CHECK: r0 <<= r2 # encoding: [0x6f,0x20,0x00,0x00,0x00,0x00,0x00,0x00]
; CHECK: exit # encoding: [0x95,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
%shl = shl i64 %a, %cnt
ret i64 %shl
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