[PATCH] D43201: [X86] Only reorder srl/and on last DAG combiner run

Sanjay Patel via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Feb 16 07:31:07 PST 2018

spatel accepted this revision.
spatel added a comment.
This revision is now accepted and ready to land.


Comment at: test/CodeGen/X86/test-vs-bittest.ll:8
 ; CHECK-NEXT:    pushq %rax
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    testl $2048, %edi # imm = 0x800
Nit: all of the tests in this file have .cfi noise; use 'nounwind' attribute to remove that.

Comment at: test/CodeGen/X86/test-vs-bittest.ll:55
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    testl $2048, %edi # imm = 0x800
 ; CHECK-NEXT:    je .LBB2_2
craig.topper wrote:
> Note this test is identical to test64 above with the operands of the 'br' instruction reversed. We were always using 'test'. Seems the initial selectionDAG in one of the cases(i forgot which one) has an ISD::XOR inverting the setcc result before the branch. This somehow causes a difference in DAG combine ordering or something that leads to different results.
Mysteries of SDAG... :)
Please add this as a test comment here or the other test, so we have a record of it.


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