[PATCH] D43374: [ARM]Decoding MSR with unpredictable destination register causes an assert

[Simi Pallipurath via Phabricator via llvm-commits]

simpal01 updated this revision to Diff 134580.
simpal01 added a comment.

Reuploaded the diff with more context


https://reviews.llvm.org/D43374

Files:
  lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  lib/Target/ARM/Disassembler/ARMDisassembler.cpp
  lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
  test/MC/ARM/thumbv8m.s
  test/MC/Disassembler/ARM/invalid-thumb-MSR-MClass.txt

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