[llvm] r325255 - [Hexagon] Fix lowering of formal arguments after r324737

Galina Kistanova via llvm-commits llvm-commits at lists.llvm.org
Thu Feb 15 09:51:38 PST 2018


Hello Krzysztof,

It looks like one or your resent commits added broken tests to one of our
builders:
http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/7938

. . .
    LLVM :: CodeGen/Hexagon/adjust-latency-stackST.ll
    LLVM :: CodeGen/Hexagon/always-ext.ll
    LLVM :: CodeGen/Hexagon/branchfolder-keep-impdef.ll
    LLVM :: CodeGen/Hexagon/convertdptoint.ll
    LLVM :: CodeGen/Hexagon/dadd.ll
    LLVM :: CodeGen/Hexagon/dmul.ll
    LLVM :: CodeGen/Hexagon/double.ll
    LLVM :: CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll
    LLVM :: CodeGen/Hexagon/dsub.ll
    LLVM :: CodeGen/Hexagon/expand-condsets-rm-segment.ll
    LLVM :: CodeGen/Hexagon/expand-condsets-undef.ll
    LLVM :: CodeGen/Hexagon/float.ll
    LLVM :: CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll
    LLVM :: CodeGen/Hexagon/i16_VarArg.ll
    LLVM :: CodeGen/Hexagon/i1_VarArg.ll
    LLVM :: CodeGen/Hexagon/i8_VarArg.ll
    LLVM :: CodeGen/Hexagon/memcpy-likely-aligned.ll
    LLVM :: CodeGen/Hexagon/rdf-extra-livein.ll
    LLVM :: CodeGen/Hexagon/rdf-filter-defs.ll
    LLVM :: CodeGen/Hexagon/store-imm-stack-object.ll
    LLVM :: CodeGen/Hexagon/swp-epilog-reuse.ll
    LLVM :: CodeGen/Hexagon/tail-call-mem-intrinsics.ll
    LLVM :: CodeGen/Hexagon/trap-unreachable.ll
    LLVM :: CodeGen/Hexagon/vect/vect-fma.ll


The builder was already red and did not send notifications on the changes.
Please have a look?

Thanks

Galina

On Thu, Feb 15, 2018 at 7:47 AM, Krzysztof Parzyszek via llvm-commits <
llvm-commits at lists.llvm.org> wrote:

> Author: kparzysz
> Date: Thu Feb 15 07:47:53 2018
> New Revision: 325255
>
> URL: http://llvm.org/viewvc/llvm-project?rev=325255&view=rev
> Log:
> [Hexagon] Fix lowering of formal arguments after r324737
>
> Lowering of formal arguments needs to be aware of vararg functions.
>
> Added:
>     llvm/trunk/test/CodeGen/Hexagon/vararg-formal.ll
> Modified:
>     llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/
> Hexagon/HexagonISelLowering.cpp?rev=325255&r1=325254&r2=325255&view=diff
> ============================================================
> ==================
> --- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Thu Feb 15
> 07:47:53 2018
> @@ -107,14 +107,20 @@ static cl::opt<int> MaxStoresPerMemsetOp
>  namespace {
>
>    class HexagonCCState : public CCState {
> -    unsigned NumNamedVarArgParams;
> +    unsigned NumNamedVarArgParams = 0;
>
>    public:
>      HexagonCCState(CallingConv::ID CC, bool IsVarArg, MachineFunction &MF,
>                     SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
> -                   int NumNamedVarArgParams)
> -        : CCState(CC, IsVarArg, MF, locs, C),
> -          NumNamedVarArgParams(NumNamedVarArgParams) {}
> +                   const Function *Callee)
> +        : CCState(CC, IsVarArg, MF, locs, C) {
> +      // If a function has zero args and is a vararg function, that's
> +      // disallowed so it must be an undeclared function.  Do not assume
> +      // varargs if the callee is undefined.
> +      if (Callee && Callee->isVarArg() &&
> +          Callee->getFunctionType()->getNumParams() != 0)
> +        NumNamedVarArgParams = Callee->getFunctionType()->getNumParams();
> +    }
>
>      unsigned getNumNamedVarArgParams() const { return
> NumNamedVarArgParams; }
>    };
> @@ -323,25 +329,17 @@ HexagonTargetLowering::LowerCall(TargetL
>    MachineFrameInfo &MFI = MF.getFrameInfo();
>    auto PtrVT = getPointerTy(MF.getDataLayout());
>
> -  // Check for varargs.
> -  unsigned NumNamedVarArgParams = 0;
> -
> +  const Function *CalleeF = nullptr;
>    if (GlobalAddressSDNode *GAN = dyn_cast<GlobalAddressSDNode>(Callee)) {
>      const GlobalValue *GV = GAN->getGlobal();
>      Callee = DAG.getTargetGlobalAddress(GV, dl, MVT::i32);
> -    if (const Function* F = dyn_cast<Function>(GV)) {
> -      // If a function has zero args and is a vararg function, that's
> -      // disallowed so it must be an undeclared function.  Do not assume
> -      // varargs if the callee is undefined.
> -      if (F->isVarArg() && F->getFunctionType()->getNumParams() != 0)
> -        NumNamedVarArgParams = F->getFunctionType()->getNumParams();
> -    }
> +    CalleeF = dyn_cast<Function>(GV);
>    }
>
>    // Analyze operands of the call, assigning locations to each operand.
>    SmallVector<CCValAssign, 16> ArgLocs;
> -  HexagonCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
> -                        ArgLocs, *DAG.getContext(), NumNamedVarArgParams);
> +  HexagonCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs,
> *DAG.getContext(),
> +                        CalleeF);
>
>    if (Subtarget.useHVXOps())
>      CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_HVX);
> @@ -698,8 +696,8 @@ SDValue HexagonTargetLowering::LowerForm
>
>    // Assign locations to all of the incoming arguments.
>    SmallVector<CCValAssign, 16> ArgLocs;
> -  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
> -                 *DAG.getContext());
> +  HexagonCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs,
> *DAG.getContext(),
> +                        &MF.getFunction());
>
>    if (Subtarget.useHVXOps())
>      CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon_HVX);
>
> Added: llvm/trunk/test/CodeGen/Hexagon/vararg-formal.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/
> CodeGen/Hexagon/vararg-formal.ll?rev=325255&view=auto
> ============================================================
> ==================
> --- llvm/trunk/test/CodeGen/Hexagon/vararg-formal.ll (added)
> +++ llvm/trunk/test/CodeGen/Hexagon/vararg-formal.ll Thu Feb 15 07:47:53
> 2018
> @@ -0,0 +1,12 @@
> +; RUN: llc -march=hexagon < %s | FileCheck %s
> +
> +; Make sure that the first formal argument is not loaded from memory.
> +; CHECK-NOT: memw
> +
> +define i32 @fred(i32 %a0, ...) #0 {
> +b1:
> +  %v2 = add i32 %a0, 1
> +  ret i32 %v2
> +}
> +
> +attributes #0 = { nounwind }
>
>
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