[llvm] r325019 - [DAGCombiner] Add one use check to fold (not (and x, y)) -> (or (not x), (not y))

[Craig Topper via llvm-commits]

Author: ctopper
Date: Tue Feb 13 08:25:27 2018
New Revision: 325019

URL: http://llvm.org/viewvc/llvm-project?rev=325019&view=rev
Log:
[DAGCombiner] Add one use check to fold (not (and x, y)) -> (or (not x), (not y))

Summary:
If the and has an additional use we shouldn't invert it. That creates an additional instruction.

While there add a one use check to the transform above that looked similar.

Reviewers: spatel, RKSimon

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D43225

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/X86/tbm_patterns.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=325019&r1=325018&r2=325019&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Feb 13 08:25:27 2018
@@ -5398,7 +5398,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N)
   }
 
   // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
-  if (isOneConstant(N1) && VT == MVT::i1 &&
+  if (isOneConstant(N1) && VT == MVT::i1 && N0.hasOneUse() &&
       (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
     SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
     if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
@@ -5410,7 +5410,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N)
     }
   }
   // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
-  if (isAllOnesConstant(N1) &&
+  if (isAllOnesConstant(N1) && N0.hasOneUse() &&
       (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
     SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
     if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {

Modified: llvm/trunk/test/CodeGen/X86/tbm_patterns.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tbm_patterns.ll?rev=325019&r1=325018&r2=325019&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tbm_patterns.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tbm_patterns.ll Tue Feb 13 08:25:27 2018
@@ -907,17 +907,12 @@ entry:
   ret i64 %and
 }
 
-; This should select blcic
-; TODO: the xor is being combined with the mask and creating an or that's breaking this. Looks like a missing one use check.
+; Make sure the mask doesn't break our matching of blcic
 define  i64 @masked_blcic(i64) {
 ; CHECK-LABEL: masked_blcic:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movzwl %di, %eax
-; CHECK-NEXT:    # kill: def $edi killed $edi killed $rdi def $rdi
-; CHECK-NEXT:    notl %edi
-; CHECK-NEXT:    orq $-65536, %rdi # imm = 0xFFFF0000
-; CHECK-NEXT:    incq %rax
-; CHECK-NEXT:    andq %rdi, %rax
+; CHECK-NEXT:    blcicl %eax, %eax
 ; CHECK-NEXT:    retq
   %2 = and i64 %0, 65535
   %3 = xor i64 %2, -1