[PATCH] D42962: [ARM] Allow 64- and 128-bit types with 't' inline asm constraint

Renato Golin via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Feb 13 07:30:30 PST 2018

rengolin added a comment.

In https://reviews.llvm.org/D42962#1006217, @pbarrio wrote:

> In this case, the constraint handling code will happily allocate a Q register, but the compiler will fail with the following:
> `<inline asm>:1:6: error: invalid operand for instruction
>   vadd.f64 q0, q0, q1
> `
>  I think we don't need a new test for this case because this is already taken care of by the MC testing of instruction encodings.

What about 32-bit integers?

> Besides, I would argue that someone trying to pass a vector of doubles to vadd.f64 (or any other 32-bit ARM vector instruction) is doing something incorrect, but this is not a problem of the register constraint itself. Note that this problem also predates this patch, as the 'w' constraint also suffers from it.

When users do something wrong, we try our best to let them know. :)

If we don't have an error message for that, we should.



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