[PATCH] D43222: [X86] Add combine to shrink 64-bit ands when one input is an any_extend and the other input guarantees upper 32 bits are 0.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: spatel, RKSimon.

This gets the shift case from PR35792.


Repository:
  rL LLVM

https://reviews.llvm.org/D43222

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/bmi.ll
  test/CodeGen/X86/var-permute-256.ll

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