[PATCH] D42962: [ARM] Allow 64- and 128-bit types with 't' inline asm constraint

[Renato Golin via Phabricator via llvm-commits]

rengolin added a comment.

In https://reviews.llvm.org/D42962#1005356, @pbarrio wrote:

> However, I think the fact that it mentions sN registers doesn't mean to say it only allows sN registers. A similar thing happens to 'w', which is documented as "VFP floating-point registers d0-d31..." but also allows selecting Q regs. In fact, there is no constraint that mentions the Q registers: the way to select them is either through 'w' or 't'. At least that is how I understand the GCC documentation.


That's why I said: `Though it's not completely wrong to support the low part of D/Q registers`

It's not wrong to assume that we're not just using the lower parts of D0, or both as f32.

But I also said: `I'm not sure the code in question is making sure this is true.`

AFAICS, the current approach just checks the size of the type, not the size of the sub-type. f64 or even integer types could still leak in, no?

To prove they're not, we need tests making sure they break if you try.


Repository:
  rL LLVM

https://reviews.llvm.org/D42962