[PATCH] D42962: [ARM] Allow 64- and 128-bit types with 't' inline asm constraint

[Pablo Barrio via Phabricator via llvm-commits]

pbarrio added a comment.

In https://reviews.llvm.org/D42962#1005102, @rengolin wrote:

> This goes against the documentation, which only supports sN:
>  https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html#Machine-Constraints
>
> Though it's not completely wrong to support the low part of D/Q registers, I'm not sure the code in question is making sure this is true.


Thanks for flagging this up. What is shown in the documentation is not the behaviour shown by GCC, so I have opened a documentation bug report: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84343

However, I think the fact that it mentions sN registers doesn't mean to say it only allows sN registers. A similar thing happens to 'w', which is documented as "VFP floating-point registers d0-d31..." but also allows selecting Q regs. In fact, there is no constraint that mentions the Q registers: the way to select them is either through 'w' or 't'. At least that is how I understand the GCC documentation.


Repository:
  rL LLVM

https://reviews.llvm.org/D42962