[PATCH] D42962: [ARM] Allow 64- and 128-bit types with 't' inline asm constraint
Pablo Barrio via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 12 09:59:56 PST 2018
pbarrio added a comment.
In https://reviews.llvm.org/D42962#1000360, @pbarrio wrote:
> In https://reviews.llvm.org/D42962#999509, @efriedma wrote:
> > > This behaviour still differs from that of GCC but I think it is actually more correct, since LLVM picks up the right register type based on the datatype of x, while GCC would need an extra operand modifier to achieve the same result
> > If we're not going to match gcc, what's the point?
> This patch allows specifying the lower Q/D vector registers from inline assembly, which is something that can be done in GCC but not in LLVM. In order to mimic the GCC behaviour completely, we should also add support for the q/e/f operand modifiers with the 't' constraint. These modifiers are already allowed with the 'w' constraint for the complete vector register set, so it shouldn't be hard to do. However, I think it should be a separate patch with additional testing.
I was wrong when I said the GNU modifiers are q/e, which actually makes things easier. The correct operand modifiers to select a quad/double vector register in GCC are q/P. These already work in LLVM (they are just ignored according to the documentation and also my local testing). So, I think there is no need for an additional patch; we should be able to handle inline assembly written for GCC with the 't' constraint.
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