[llvm] r324728 - [InstCombine] Add constant vector support for X udiv C, where C >= signbit

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Fri Feb  9 02:43:59 2018
New Revision: 324728

URL: http://llvm.org/viewvc/llvm-project?rev=324728&view=rev
Log:
[InstCombine] Add constant vector support for X udiv C, where C >= signbit

Modified:
    llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
    llvm/trunk/test/Transforms/InstCombine/udiv_select_to_select_shift.ll
    llvm/trunk/test/Transforms/InstCombine/vector-udiv.ll

Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp?rev=324728&r1=324727&r2=324728&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp Fri Feb  9 02:43:59 2018
@@ -1067,8 +1067,7 @@ static Instruction *foldUDivPow2Cst(Valu
 // X udiv C, where C >= signbit
 static Instruction *foldUDivNegCst(Value *Op0, Value *Op1,
                                    const BinaryOperator &I, InstCombiner &IC) {
-  Value *ICI = IC.Builder.CreateICmpULT(Op0, cast<ConstantInt>(Op1));
-
+  Value *ICI = IC.Builder.CreateICmpULT(Op0, cast<Constant>(Op1));
   return SelectInst::Create(ICI, Constant::getNullValue(I.getType()),
                             ConstantInt::get(I.getType(), 1));
 }
@@ -1111,12 +1110,11 @@ static size_t visitUDivOperand(Value *Op
     return Actions.size();
   }
 
-  if (ConstantInt *C = dyn_cast<ConstantInt>(Op1))
-    // X udiv C, where C >= signbit
-    if (C->getValue().isNegative()) {
-      Actions.push_back(UDivFoldAction(foldUDivNegCst, C));
-      return Actions.size();
-    }
+  // X udiv C, where C >= signbit
+  if (match(Op1, m_Negative())) {
+    Actions.push_back(UDivFoldAction(foldUDivNegCst, Op1));
+    return Actions.size();
+  }
 
   // X udiv (C1 << N), where C1 is "1<<C2"  -->  X >> (N+C2)
   if (match(Op1, m_Shl(m_Power2(), m_Value())) ||

Modified: llvm/trunk/test/Transforms/InstCombine/udiv_select_to_select_shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/udiv_select_to_select_shift.ll?rev=324728&r1=324727&r2=324728&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/udiv_select_to_select_shift.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/udiv_select_to_select_shift.ll Fri Feb  9 02:43:59 2018
@@ -24,7 +24,8 @@ define i64 @test(i64 %X, i1 %Cond ) {
 
 define <2 x i32> @PR34856(<2 x i32> %t0, <2 x i32> %t1) {
 ; CHECK-LABEL: @PR34856(
-; CHECK-NEXT:    [[DIV1:%.*]] = udiv <2 x i32> [[T1:%.*]], <i32 -7, i32 -7>
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt <2 x i32> [[T1:%.*]], <i32 -8, i32 -8>
+; CHECK-NEXT:    [[DIV1:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i32>
 ; CHECK-NEXT:    ret <2 x i32> [[DIV1]]
 ;
   %cmp = icmp eq <2 x i32> %t0, <i32 1, i32 1>

Modified: llvm/trunk/test/Transforms/InstCombine/vector-udiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/vector-udiv.ll?rev=324728&r1=324727&r2=324728&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/vector-udiv.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/vector-udiv.ll Fri Feb  9 02:43:59 2018
@@ -22,8 +22,9 @@ define <4 x i32> @test_v4i32_const_pow2(
 ; X udiv C, where C >= signbit
 define <4 x i32> @test_v4i32_negconstsplat(<4 x i32> %a0) {
 ; CHECK-LABEL: @test_v4i32_negconstsplat(
-; CHECK-NEXT:    [[TMP1:%.*]] = udiv <4 x i32> [[A0:%.*]], <i32 -3, i32 -3, i32 -3, i32 -3>
-; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt <4 x i32> [[A0:%.*]], <i32 -4, i32 -4, i32 -4, i32 -4>
+; CHECK-NEXT:    [[TMP2:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32>
+; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 ;
   %1 = udiv <4 x i32> %a0, <i32 -3, i32 -3, i32 -3, i32 -3>
   ret <4 x i32> %1
@@ -31,8 +32,9 @@ define <4 x i32> @test_v4i32_negconstspl
 
 define <4 x i32> @test_v4i32_negconst(<4 x i32> %a0) {
 ; CHECK-LABEL: @test_v4i32_negconst(
-; CHECK-NEXT:    [[TMP1:%.*]] = udiv <4 x i32> [[A0:%.*]], <i32 -3, i32 -5, i32 -7, i32 -9>
-; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt <4 x i32> [[A0:%.*]], <i32 -4, i32 -6, i32 -8, i32 -10>
+; CHECK-NEXT:    [[TMP2:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32>
+; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 ;
   %1 = udiv <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 -9>
   ret <4 x i32> %1