[llvm] r324720 - [AArch64] Return true in enableMultipleCopyHints().
Jonas Paulsson via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 9 01:22:20 PST 2018
Author: jonpa
Date: Fri Feb 9 01:22:20 2018
New Revision: 324720
URL: http://llvm.org/viewvc/llvm-project?rev=324720&view=rev
Log:
[AArch64] Return true in enableMultipleCopyHints().
Enable multiple COPY hints to eliminate more COPYs during register allocation.
Note that this is something all targets should do, see
https://reviews.llvm.org/D38128.
Review: Martin Storsjö
Modified:
llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.h
llvm/trunk/test/CodeGen/AArch64/arm64-aapcs.ll
llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll
llvm/trunk/test/CodeGen/AArch64/swifterror.ll
llvm/trunk/test/CodeGen/AArch64/win64_vararg.ll
Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.h?rev=324720&r1=324719&r2=324720&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.h Fri Feb 9 01:22:20 2018
@@ -69,6 +69,8 @@ public:
const TargetRegisterClass *
getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
+ bool enableMultipleCopyHints() const override { return true; }
+
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
bool useFPForScavengingIndex(const MachineFunction &MF) const override;
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-aapcs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-aapcs.ll?rev=324720&r1=324719&r2=324720&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-aapcs.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-aapcs.ll Fri Feb 9 01:22:20 2018
@@ -5,20 +5,20 @@
; CHECK-LABEL: @test_i128_align
define i128 @test_i128_align(i32, i128 %arg, i32 %after) {
store i32 %after, i32* @var, align 4
-; CHECK: str w4, [{{x[0-9]+}}, :lo12:var]
+; CHECK-DAG: str w4, [{{x[0-9]+}}, :lo12:var]
ret i128 %arg
-; CHECK: mov x0, x2
-; CHECK: mov x1, x3
+; CHECK-DAG: mov x0, x2
+; CHECK-DAG: mov x1, x3
}
; CHECK-LABEL: @test_i64x2_align
define [2 x i64] @test_i64x2_align(i32, [2 x i64] %arg, i32 %after) {
store i32 %after, i32* @var, align 4
-; CHECK: str w3, [{{x[0-9]+}}, :lo12:var]
+; CHECK-DAG: str w3, [{{x[0-9]+}}, :lo12:var]
ret [2 x i64] %arg
-; CHECK: mov x0, x1
+; CHECK-DAG: mov x0, x1
; CHECK: mov x1, x2
}
Modified: llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll?rev=324720&r1=324719&r2=324720&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/func-argpassing.ll Fri Feb 9 01:22:20 2018
@@ -164,11 +164,11 @@ define void @stacked_fpu(float %var0, do
define i64 @check_i128_regalign(i32 %val0, i128 %val1, i64 %val2) {
; CHECK-LABEL: check_i128_regalign
store i128 %val1, i128* @var128
-; CHECK: add x[[VAR128:[0-9]+]], {{x[0-9]+}}, :lo12:var128
+; CHECK-DAG: add x[[VAR128:[0-9]+]], {{x[0-9]+}}, :lo12:var128
; CHECK-DAG: stp x2, x3, [x[[VAR128]]]
ret i64 %val2
-; CHECK: mov x0, x4
+; CHECK-DAG: mov x0, x4
}
define void @check_i128_stackalign(i32 %val0, i32 %val1, i32 %val2, i32 %val3,
Modified: llvm/trunk/test/CodeGen/AArch64/swifterror.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/swifterror.ll?rev=324720&r1=324719&r2=324720&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/swifterror.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/swifterror.ll Fri Feb 9 01:22:20 2018
@@ -40,11 +40,11 @@ define float @caller(i8* %error_ref) {
; CHECK-APPLE: mov [[ID:x[0-9]+]], x0
; CHECK-APPLE: mov x21, xzr
; CHECK-APPLE: bl {{.*}}foo
+; CHECK-APPLE: mov x0, x21
; CHECK-APPLE: cbnz x21
; Access part of the error object and save it to error_ref
-; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x21, #8]
+; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x0, #8]
; CHECK-APPLE: strb [[CODE]], [{{.*}}[[ID]]]
-; CHECK-APPLE: mov x0, x21
; CHECK-APPLE: bl {{.*}}free
; CHECK-O0-LABEL: caller:
@@ -263,11 +263,11 @@ define float @caller3(i8* %error_ref) {
; CHECK-APPLE: mov [[ID:x[0-9]+]], x0
; CHECK-APPLE: mov x21, xzr
; CHECK-APPLE: bl {{.*}}foo_sret
+; CHECK-APPLE: mov x0, x21
; CHECK-APPLE: cbnz x21
; Access part of the error object and save it to error_ref
-; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x21, #8]
+; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x0, #8]
; CHECK-APPLE: strb [[CODE]], [{{.*}}[[ID]]]
-; CHECK-APPLE: mov x0, x21
; CHECK-APPLE: bl {{.*}}free
; CHECK-O0-LABEL: caller3:
@@ -357,11 +357,11 @@ define float @caller4(i8* %error_ref) {
; CHECK-APPLE: mov x21, xzr
; CHECK-APPLE: bl {{.*}}foo_vararg
+; CHECK-APPLE: mov x0, x21
; CHECK-APPLE: cbnz x21
; Access part of the error object and save it to error_ref
-; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x21, #8]
+; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x0, #8]
; CHECK-APPLE: strb [[CODE]], [{{.*}}[[ID]]]
-; CHECK-APPLE: mov x0, x21
; CHECK-APPLE: bl {{.*}}free
entry:
%error_ptr_ref = alloca swifterror %swift_error*
Modified: llvm/trunk/test/CodeGen/AArch64/win64_vararg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/win64_vararg.ll?rev=324720&r1=324719&r2=324720&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/win64_vararg.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/win64_vararg.ll Fri Feb 9 01:22:20 2018
@@ -161,25 +161,25 @@ attributes #6 = { "no-frame-pointer-elim
; CHECK: add x8, x8, #15
; CHECK: mov x9, sp
; CHECK: and x8, x8, #0x1fffffff0
-; CHECK: sub x20, x9, x8
+; CHECK: sub [[REG:x[0-9]+]], x9, x8
; CHECK: mov x19, x1
-; CHECK: mov x23, sp
+; CHECK: mov [[REG2:x[0-9]+]], sp
; CHECK: stp x6, x7, [x29, #48]
; CHECK: stp x4, x5, [x29, #32]
; CHECK: stp x2, x3, [x29, #16]
-; CHECK: mov sp, x20
-; CHECK: ldur x21, [x29, #-40]
-; CHECK: sxtw x22, w0
+; CHECK: mov sp, [[REG]]
+; CHECK: ldur [[REG3:x[0-9]+]], [x29, #-40]
+; CHECK: sxtw [[REG4:x[0-9]+]], w0
; CHECK: bl __local_stdio_printf_options
; CHECK: ldr x8, [x0]
-; CHECK: mov x1, x20
-; CHECK: mov x2, x22
+; CHECK: mov x1, [[REG]]
+; CHECK: mov x2, [[REG4]]
; CHECK: mov x3, x19
; CHECK: orr x0, x8, #0x2
; CHECK: mov x4, xzr
-; CHECK: mov x5, x21
+; CHECK: mov x5, [[REG3]]
; CHECK: bl __stdio_common_vsprintf
-; CHECK: mov sp, x23
+; CHECK: mov sp, [[REG2]]
; CHECK: sub sp, x29, #48
; CHECK: ldp x29, x30, [sp, #48]
; CHECK: ldp x20, x19, [sp, #32]
@@ -255,17 +255,15 @@ define i32 @snprintf(i8*, i64, i8*, ...)
; CHECK-LABEL: fixed_params
; CHECK: sub sp, sp, #32
-; CHECK: mov w8, w3
-; CHECK: mov w9, w2
-; CHECK: mov w10, w1
+; CHECK-DAG: mov w6, w3
+; CHECK-DAG: mov [[REG1:w[0-9]+]], w2
+; CHECK: mov w2, w1
; CHECK: str w4, [sp]
; CHECK: fmov x1, d0
; CHECK: fmov x3, d1
; CHECK: fmov x5, d2
; CHECK: fmov x7, d3
-; CHECK: mov w2, w10
-; CHECK: mov w4, w9
-; CHECK: mov w6, w8
+; CHECK: mov w4, [[REG1]]
; CHECK: str x30, [sp, #16]
; CHECK: str d4, [sp, #8]
; CHECK: bl varargs
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