[PATCH] D35267: Pass Divergence Analysis data to selection DAG to drive divergence dependent instruction selection

Stanislav Mekhanoshin via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Feb 8 10:01:00 PST 2018


rampitec added inline comments.


================
Comment at: lib/Target/AMDGPU/AMDGPUISelLowering.cpp:786
+            RI->getRegClass(AMDGPU::VReg_256RegClassID)->contains(Reg) ||
+            RI->getRegClass(AMDGPU::VReg_512RegClassID)->contains(Reg);
+        }
----------------
alex-t wrote:
> rampitec wrote:
> > I am afraid that is not true to say that VGPR is necessarily divergent.
> That's not true.  Do we have a mean to detect that this is a splat vector?
> If not I'd stay with conservative approach that consider all VGPRs divergent.
> Alternatively we could add one more target hook to query for special VGPRs that are uniform.
I doubt you can reliably detect it. The concern is potential unneeded moves and readfirstlane instructions, one thing that we are trying to avoid here.


https://reviews.llvm.org/D35267





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