[PATCH] D43042: [MachineOperand][Target] Add target option to disable setting MachineOperand::isRenamable

[Geoff Berry via Phabricator via llvm-commits]

gberry created this revision.
gberry added reviewers: qcolombet, MatzeB.
Herald added subscribers: niosHD, sabuasal, apazos, jordy.potman.lists, simoncook, johnrusso, rbar, asb, fedor.sergeev, kbarton, kristof.beyls, arichardson, tpr, javed.absar, nhaehnle, sdardis, mcrosier, jyknight, arsenm, aemerson.

Add a target option AllowRegisterRenaming that is used to opt in to
post-register-allocation renaming of registers.  This is set to 0 by
default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
fields of all opcodes to be set to 1, inhibiting the setting of any
MachineOperand isRenamable flags to 1.

Set the AllowRegisterRenaming flag to 1 for all in-tree targets that
have lit tests that were effected by enabling COPY forwarding in
MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC,
RISCV, Sparc, SystemZ and X86).

Add some more comments describing the semantics of the
MachineOperand::isRenamable flag and how it is set and maintained.

Also, clear the isRenamable flag on operands when the opcode is changed
to one that has hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq set.


Repository:
  rL LLVM

https://reviews.llvm.org/D43042

Files:
  include/llvm/CodeGen/MachineInstr.h
  include/llvm/CodeGen/MachineOperand.h
  include/llvm/Target/Target.td
  lib/CodeGen/MachineInstr.cpp
  lib/Target/AArch64/AArch64.td
  lib/Target/AMDGPU/AMDGPU.td
  lib/Target/ARM/ARM.td
  lib/Target/Hexagon/Hexagon.td
  lib/Target/Mips/Mips.td
  lib/Target/PowerPC/PPC.td
  lib/Target/RISCV/RISCV.td
  lib/Target/Sparc/Sparc.td
  lib/Target/SystemZ/SystemZ.td
  lib/Target/X86/X86.td
  utils/TableGen/CodeGenTarget.cpp
  utils/TableGen/CodeGenTarget.h
  utils/TableGen/InstrInfoEmitter.cpp

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