[PATCH] D42738: [mips] Define certain instructions in microMIPS32r3

[Simon Dardis via Phabricator via llvm-commits]

sdardis accepted this revision.
sdardis added a comment.
This revision is now accepted and ready to land.

LGTM with two inline nits addressed.



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Comment at: test/CodeGen/Mips/llvm-ir/arith.ll:1
+; RUN: llc -march=mips -mcpu=mips32                           -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32
+; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64            -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64
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This file should be called 'fp-arith.ll' or something similar. 'arith.ll' suggests integer arithmetic to me, which we have test files already for.


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Comment at: test/CodeGen/Mips/llvm-ir/cp1move.ll:1
+; RUN: llc -march=mips -mcpu=mips32r2                         -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32R2
+; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64            -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64
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You can use the debug option "-mno-ldc1-sdc1" to disable the generation of ldc1 and sdc1. That along with simple bitcasts will generate mthc1 and mfhc1 instructions. Then this file can be called bitcast.ll

This is better than replying on inline asm as we want to test code generation from llvm ir.


https://reviews.llvm.org/D42738