[llvm] r324422 - [LivePhysRegs] Fix handling of return instructions.

Hans Wennborg via llvm-commits llvm-commits at lists.llvm.org
Wed Feb 7 02:03:00 PST 2018 

Merged to 6.0 in r324466.

On Wed, Feb 7, 2018 at 12:00 AM, Eli Friedman via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Author: efriedma
> Date: Tue Feb  6 15:00:17 2018
> New Revision: 324422
>
> URL: http://llvm.org/viewvc/llvm-project?rev=324422&view=rev
> Log:
> [LivePhysRegs] Fix handling of return instructions.
>
> See D42509 for the original version of this.
>
> Basically, there are two significant changes to behavior here:
>
> - addLiveOuts always adds all pristine registers (even if a block has
> no successors).
> - addLiveOuts and addLiveOutsNoPristines always add all callee-saved
> registers for return blocks (including conditional return blocks).
>
> I cleaned up the functions a bit to make it clear these properties hold.
>
> Differential Revision: https://reviews.llvm.org/D42655
>
>
> Added:
>     llvm/trunk/test/CodeGen/Thumb/stm-scavenging.ll
> Modified:
>     llvm/trunk/lib/CodeGen/LivePhysRegs.cpp
>     llvm/trunk/test/CodeGen/ARM/pr25838.ll
>
> Modified: llvm/trunk/lib/CodeGen/LivePhysRegs.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LivePhysRegs.cpp?rev=324422&r1=324421&r2=324422&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/LivePhysRegs.cpp (original)
> +++ llvm/trunk/lib/CodeGen/LivePhysRegs.cpp Tue Feb  6 15:00:17 2018
> @@ -205,14 +205,18 @@ void LivePhysRegs::addPristines(const Ma
>  }
>
>  void LivePhysRegs::addLiveOutsNoPristines(const MachineBasicBlock &MBB) {
> -  if (!MBB.succ_empty()) {
> -    // To get the live-outs we simply merge the live-ins of all successors.
> -    for (const MachineBasicBlock *Succ : MBB.successors())
> -      addBlockLiveIns(*Succ);
> -  } else if (MBB.isReturnBlock()) {
> -    // For the return block: Add all callee saved registers that are saved and
> -    // restored (somewhere); This does not include callee saved registers that
> -    // are unused and hence not saved and restored; they are called pristine.
> +  // To get the live-outs we simply merge the live-ins of all successors.
> +  for (const MachineBasicBlock *Succ : MBB.successors())
> +    addBlockLiveIns(*Succ);
> +  if (MBB.isReturnBlock()) {
> +    // Return blocks are a special case because we currently don't mark up
> +    // return instructions completely: specifically, there is no explicit
> +    // use for callee-saved registers. So we add all callee saved registers
> +    // that are saved and restored (somewhere). This does not include
> +    // callee saved registers that are unused and hence not saved and
> +    // restored; they are called pristine.
> +    // FIXME: PEI should add explicit markings to return instructions
> +    // instead of implicitly handling them here.
>      const MachineFunction &MF = *MBB.getParent();
>      const MachineFrameInfo &MFI = MF.getFrameInfo();
>      if (MFI.isCalleeSavedInfoValid()) {
> @@ -225,15 +229,8 @@ void LivePhysRegs::addLiveOutsNoPristine
>
>  void LivePhysRegs::addLiveOuts(const MachineBasicBlock &MBB) {
>    const MachineFunction &MF = *MBB.getParent();
> -  if (!MBB.succ_empty()) {
> -    addPristines(MF);
> -    addLiveOutsNoPristines(MBB);
> -  } else if (MBB.isReturnBlock()) {
> -    // For the return block: Add all callee saved registers.
> -    const MachineFrameInfo &MFI = MF.getFrameInfo();
> -    if (MFI.isCalleeSavedInfoValid())
> -      addCalleeSavedRegs(*this, MF);
> -  }
> +  addPristines(MF);
> +  addLiveOutsNoPristines(MBB);
>  }
>
>  void LivePhysRegs::addLiveIns(const MachineBasicBlock &MBB) {
>
> Modified: llvm/trunk/test/CodeGen/ARM/pr25838.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/pr25838.ll?rev=324422&r1=324421&r2=324422&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/pr25838.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/pr25838.ll Tue Feb  6 15:00:17 2018
> @@ -1,4 +1,4 @@
> -; RUN: llc < %s
> +; RUN: llc -verify-machineinstrs < %s
>  ; PR25838
>
>  target triple = "armv7--linux-android"
>
> Added: llvm/trunk/test/CodeGen/Thumb/stm-scavenging.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/stm-scavenging.ll?rev=324422&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Thumb/stm-scavenging.ll (added)
> +++ llvm/trunk/test/CodeGen/Thumb/stm-scavenging.ll Tue Feb  6 15:00:17 2018
> @@ -0,0 +1,46 @@
> +; RUN: llc < %s | FileCheck %s
> +target triple = "thumbv6---gnueabi"
> +
> +; Use STM to save the three registers
> +; CHECK-LABEL: use_stm:
> +; CHECK: .save   {r7, lr}
> +; CHECK: .setfp  r7, sp
> +; CHECK: stm r3!, {r0, r1, r2}
> +; CHECK: bl throws_1
> +define void @use_stm(i32 %a, i32 %b, i32 %c, i32* %d) local_unnamed_addr noreturn "no-frame-pointer-elim"="true" {
> +entry:
> +  %arrayidx = getelementptr inbounds i32, i32* %d, i32 2
> +  store i32 %a, i32* %arrayidx, align 4
> +  %arrayidx1 = getelementptr inbounds i32, i32* %d, i32 3
> +  store i32 %b, i32* %arrayidx1, align 4
> +  %arrayidx2 = getelementptr inbounds i32, i32* %d, i32 4
> +  store i32 %c, i32* %arrayidx2, align 4
> +  tail call void @throws_1(i32 %a, i32 %b, i32 %c) noreturn
> +  unreachable
> +}
> +
> +; Don't use STM: there is no available register to store
> +; the address. We could transform this with some extra math, but
> +; that currently isn't implemented.
> +; CHECK-LABEL: no_stm:
> +; CHECK: .save   {r7, lr}
> +; CHECK: .setfp  r7, sp
> +; CHECK: str r0,
> +; CHECK: str r1,
> +; CHECK: str r2,
> +; CHECK: bl throws_2
> +define void @no_stm(i32 %a, i32 %b, i32 %c, i32* %d) local_unnamed_addr noreturn "no-frame-pointer-elim"="true" {
> +entry:
> +  %arrayidx = getelementptr inbounds i32, i32* %d, i32 2
> +  store i32 %a, i32* %arrayidx, align 4
> +  %arrayidx1 = getelementptr inbounds i32, i32* %d, i32 3
> +  store i32 %b, i32* %arrayidx1, align 4
> +  %arrayidx2 = getelementptr inbounds i32, i32* %d, i32 4
> +  store i32 %c, i32* %arrayidx2, align 4
> +  tail call void @throws_2(i32 %a, i32 %b, i32 %c, i32* %d) noreturn
> +  unreachable
> +}
> +
> +
> +declare void @throws_1(i32, i32, i32) noreturn
> +declare void @throws_2(i32, i32, i32, i32*) noreturn
>
>
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