[PATCH] D35561: [SelectionDAG] Provide adequate register class for RegisterSDNode

[Jan Vesely via Phabricator via llvm-commits]

jvesely added a comment.

In https://reviews.llvm.org/D35561#999000, @sdardis wrote:

> Attached.F5808701: AMDGPU-D35561.diff <https://reviews.llvm.org/F5808701>


These look good. An additional MOV is inserted since MEMRAT_CACHELESS STORE_RAW includes constraint of using _X subreg for 32bit stores.
When you edit the test please make sure to test both the MOV from the correct id register and store of the right data.

thank you.


https://reviews.llvm.org/D35561