[PATCH] D42951: [CGP] Strength reduce cmp (xor (a, -1), xor(b, -1)) => cmp (b, a)

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Thanks for taking a look. I've been looking into this more today. At finding a sensible target hook to put this behind and/or perhaps making it more specific.  It's a great shame I can't just do this in ISel (right?), after selection has happened.

I agree it's not the best as it is, and there might be something else going on here. Not specifically register pressure related, just by knockon causing extra spills in the thumb1 case. It seems to be better for thumb2/aarch64 codegen too (where there are more registers), at least when put in a loop. Perhaps because it can reason it does not need to perform uxtb's / AND 0xff's? In other cases it can make things worse, even without an integer min/max instruction as in arm/aarch64. I know we have some issues with uxtbs where they are not necessary, but difficult to reason that they can be removed. Some of the guys here have been looking into that lately.

Note that the changes to make i8's instcombines legal got us ~12%. This gets us an extra 25% on top! At least on these targets, where it's hit us the hardest. Just from a one line change, switching the operators.


https://reviews.llvm.org/D42951