[PATCH] D42935: [X86] Use min/max for vector ult/ugt compares if avoids a sign flip.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

In https://reviews.llvm.org/D42935#999124, @craig.topper wrote:

> Maybe it's too early in the morning, but I'm not sure I followed. A lot of these cases aren't min/max how does custom handling help?


No, it might be me - I'm starting to see phantom minmax patterns everywhere....

But that test_ult_byte regression is annoying.



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Comment at: lib/Target/X86/X86ISelLowering.cpp:18008
+                                              VET == MVT::i32)) ||
+                    (Subtarget.hasSSE2() && (VET == MVT::i8)));
+  if (UseMinMax) {
----------------
Use IsOperationLegal instead? I think that'd add VLX v2i64/v4i64 support?


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Comment at: test/CodeGen/X86/vec_setcc-2.ll:150
+; CHECK-NEXT:    movdqa {{.*#+}} xmm1 = [11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11]
+; CHECK-NEXT:    pmaxub %xmm0, %xmm1
 ; CHECK-NEXT:    pcmpeqb %xmm1, %xmm0
----------------
Interesting that this didn't commute and fold the load? You'd need a MOVDQArr instead I guess.


https://reviews.llvm.org/D42935