[PATCH] D42970: [ARM] Fix PR35157: broken isel for VLD3/VLD4/VST3/VST4 with WB

[Thomas Preud'homme via Phabricator via llvm-commits]

thopre created this revision.
thopre added reviewers: rengolin, t.p.northover.
Herald added subscribers: llvm-commits, kristof.beyls, javed.absar, aemerson.

Selection of the right VLD/VST instruction is broken for load and store
of 3 and 4 v1i64 vectors. SelectVLD and SelectVST are called with MIR
opcode for fixed writeback (ie increment is access size) and call
getVLDSTRegisterUpdateOpcode() to select an opcode with register
writeback if base register update is of a different size. Since
getVLDSTRegisterUpdateOpcode() only knows about VLD1/VLD2/VST1/VST2 the
call is currently conditional on the number of element in the vector.

However, VLD1/VST1 is selected by SelectVLD/SelectVST's caller for load
and stores of 3 or 4 v1i64 vectors. Therefore the opcode is not updated
which later lead to a fixed writeback instruction being constructed with
an extra operand for the register writeback. This patch changes the
logic to call isVLDfixed and isVSTfixed to decide whether the opcode
should be updated.

The patch also rework the logic and comments for pushing the writeback
offset operand and r0 operand to clarify the logic: writeback offset
needs to be pushed if it's a register writeback, r0 needs to be pushed
if not and the instruction is a VLD1/VLD2/VST1/VST2.


Repository:
  rL LLVM

https://reviews.llvm.org/D42970

Files:
  lib/Target/ARM/ARMISelDAGToDAG.cpp
  test/CodeGen/ARM/pr35157.ll

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