[PATCH] D35561: [SelectionDAG] Provide adequate register class for RegisterSDNode

[Jan Vesely via Phabricator via llvm-commits]

jvesely added a comment.

In https://reviews.llvm.org/D35561#996084, @sdardis wrote:

> It appears this also fixes a machine verifier failure in test/CodeGen/AMDGPU/r600.work-item-intrinsics.ll, but I am unsure on the correctness of the changed assembly output. +CC'ing Jan Vesely who provided the test.


It'd help to see the diff. The test checks that certain registers are reserved and not allocated when thread IDs are used by the shader.
TIDIG.{x,y,z} is in T0.{x,y,z}, TGID.{x,y,z} is in T1.{x,y,z}.

It looks like this patch is OK other than introducing an extra MOV, I haven't looked into why that is.


https://reviews.llvm.org/D35561