[llvm] r324241 - [Hexagon] Use V6_vmpyih for halfword multiplication

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Mon Feb  5 07:40:06 2018
New Revision: 324241

URL: http://llvm.org/viewvc/llvm-project?rev=324241&view=rev
Log:
[Hexagon] Use V6_vmpyih for halfword multiplication

Unlike V6_vmpyhv, it produces the result in the exact form that is
expected without the need for a shuffle.

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
    llvm/trunk/test/CodeGen/Hexagon/autohvx/arith.ll

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp?rev=324241&r1=324240&r2=324241&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp Mon Feb  5 07:40:06 2018
@@ -864,14 +864,10 @@ HexagonTargetLowering::LowerHvxMul(SDVal
   SDValue Vt = Op.getOperand(1);
 
   switch (ElemTy.SimpleTy) {
-    case MVT::i8:
-    case MVT::i16: { // V6_vmpyih
+    case MVT::i8: {
       // For i8 vectors Vs = (a0, a1, ...), Vt = (b0, b1, ...),
       // V6_vmpybv Vs, Vt produces a pair of i16 vectors Hi:Lo,
       // where Lo = (a0*b0, a2*b2, ...), Hi = (a1*b1, a3*b3, ...).
-      // For i16, use V6_vmpyhv, which behaves in an analogous way to
-      // V6_vmpybv: results Lo and Hi are products of even/odd elements
-      // respectively.
       MVT ExtTy = typeExtElem(ResTy, 2);
       unsigned MpyOpc = ElemTy == MVT::i8 ? Hexagon::V6_vmpybv
                                           : Hexagon::V6_vmpyhv;
@@ -886,6 +882,11 @@ HexagonTargetLowering::LowerHvxMul(SDVal
       SDValue BS = getByteShuffle(dl, P.first, P.second, ShuffMask, DAG);
       return DAG.getBitcast(ResTy, BS);
     }
+    case MVT::i16:
+      // For i16 there is V6_vmpyih, which acts exactly like the MUL opcode.
+      // (There is also V6_vmpyhv, which behaves in an analogous way to
+      // V6_vmpybv.)
+      return getInstr(Hexagon::V6_vmpyih, dl, ResTy, {Vs, Vt}, DAG);
     case MVT::i32: {
       // Use the following sequence for signed word multiply:
       // T0 = V6_vmpyiowh Vs, Vt

Modified: llvm/trunk/test/CodeGen/Hexagon/autohvx/arith.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/autohvx/arith.ll?rev=324241&r1=324240&r2=324241&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/autohvx/arith.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/autohvx/arith.ll Mon Feb  5 07:40:06 2018
@@ -239,16 +239,14 @@ define <128 x i8> @mpyb_128(<128 x i8> %
 }
 
 ; CHECK-LABEL: mpyh_64:
-; CHECK: v[[H01:[0-9]+]]:[[L01:[0-9]+]].w = vmpy(v0.h,v1.h)
-; CHECK: vshuffe(v[[H01]].h,v[[L01]].h)
+; CHECK: vmpyi(v0.h,v1.h)
 define <32 x i16> @mpyh_64(<32 x i16> %v0, <32 x i16> %v1) #0 {
   %p = mul <32 x i16> %v0, %v1
   ret <32 x i16> %p
 }
 
 ; CHECK-LABEL: mpyh_128:
-; CHECK: v[[H11:[0-9]+]]:[[L11:[0-9]+]].w = vmpy(v0.h,v1.h)
-; CHECK: vshuffe(v[[H11]].h,v[[L11]].h)
+; CHECK: vmpyi(v0.h,v1.h)
 define <64 x i16> @mpyh_128(<64 x i16> %v0, <64 x i16> %v1) #1 {
   %p = mul <64 x i16> %v0, %v1
   ret <64 x i16> %p