[llvm] r324172 - [RISCV] Update two RISCV codegen tests after rL323991

[Alex Bradbury via llvm-commits]

Author: asb
Date: Sat Feb  3 05:02:30 2018
New Revision: 324172

URL: http://llvm.org/viewvc/llvm-project?rev=324172&view=rev
Log:
[RISCV] Update two RISCV codegen tests after rL323991

>From the discussion in D41835 it looks possible the change will be backed out, 
but for now let's fix the RISCV tests.

Modified:
    llvm/trunk/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
    llvm/trunk/test/CodeGen/RISCV/calls.ll

Modified: llvm/trunk/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll?rev=324172&r1=324171&r2=324172&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll Sat Feb  3 05:02:30 2018
@@ -278,7 +278,7 @@ define i64 @test_cttz_i64(i64 %a) nounwi
 ; RV32I-NEXT:    sw s8, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s3, a0
-; RV32I-NEXT:    addi a0, s3, -1
+; RV32I-NEXT:    addi a0, a0, -1
 ; RV32I-NEXT:    not a1, s3
 ; RV32I-NEXT:    and a0, a1, a0
 ; RV32I-NEXT:    lui a1, 349525
@@ -469,7 +469,7 @@ define i64 @test_cttz_i64_zero_undef(i64
 ; RV32I-NEXT:    sw s8, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s3, a0
-; RV32I-NEXT:    addi a0, s3, -1
+; RV32I-NEXT:    addi a0, a0, -1
 ; RV32I-NEXT:    not a1, s3
 ; RV32I-NEXT:    and a0, a1, a0
 ; RV32I-NEXT:    lui a1, 349525

Modified: llvm/trunk/test/CodeGen/RISCV/calls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/calls.ll?rev=324172&r1=324171&r2=324172&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/calls.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/calls.ll Sat Feb  3 05:02:30 2018
@@ -99,8 +99,8 @@ define i32 @test_call_external_many_args
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    sw s1, 8(sp)
 ; RV32I-NEXT:    mv s1, a0
-; RV32I-NEXT:    sw s1, 4(sp)
-; RV32I-NEXT:    sw s1, 0(sp)
+; RV32I-NEXT:    sw a0, 4(sp)
+; RV32I-NEXT:    sw a0, 0(sp)
 ; RV32I-NEXT:    lui a0, %hi(external_many_args)
 ; RV32I-NEXT:    addi t0, a0, %lo(external_many_args)
 ; RV32I-NEXT:    mv a0, s1