[llvm] r324005 - [PowerPC] Tell VSX swap removal that scalar conversions are lane-sensitive

Nemanja Ivanovic via llvm-commits llvm-commits at lists.llvm.org
Thu Feb 1 13:09:04 PST 2018


Author: nemanjai
Date: Thu Feb  1 13:09:04 2018
New Revision: 324005

URL: http://llvm.org/viewvc/llvm-project?rev=324005&view=rev
Log:
[PowerPC] Tell VSX swap removal that scalar conversions are lane-sensitive

This is a rather non-controversial change. We were missing these instructions
from the list of instructions that are lane-sensitive. These two put the result
into lane 0 (BE) or 3 (LE) regardless of the input. This patch fixes PR36068.

Added:
    llvm/trunk/test/CodeGen/PowerPC/pr36068.ll
Modified:
    llvm/trunk/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp?rev=324005&r1=324004&r2=324005&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp Thu Feb  1 13:09:04 2018
@@ -519,6 +519,8 @@ bool PPCVSXSwapRemoval::gatherVectorInst
       // permute control vectors (for shift values 1, 2, 3).  However,
       // VPERM has a more restrictive register class.
       case PPC::XXSLDWI:
+      case PPC::XSCVDPSPN:
+      case PPC::XSCVSPDPN:
         break;
       }
     }

Added: llvm/trunk/test/CodeGen/PowerPC/pr36068.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/pr36068.ll?rev=324005&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/pr36068.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/pr36068.ll Thu Feb  1 13:09:04 2018
@@ -0,0 +1,18 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s  | \
+; RUN:   FileCheck %s
+
+ at glob = common local_unnamed_addr global <4 x float> zeroinitializer, align 4
+
+; Function Attrs: norecurse nounwind
+define void @test(float %a, <4 x float>* nocapture readonly %b) {
+; CHECK-LABEL: test
+; CHECK: xscvdpspn [[REG:[0-9]+]], 1
+; CHECK: xxspltw {{[0-9]+}}, [[REG]], 0
+entry:
+  %splat.splatinsert = insertelement <4 x float> undef, float %a, i32 0
+  %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer
+  %0 = load <4 x float>, <4 x float>* %b, align 4
+  %mul = fmul <4 x float> %splat.splat, %0
+  store <4 x float> %mul, <4 x float>* @glob, align 4
+  ret void
+}




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