[PATCH] D42743: [ARM] FullFP16 LowerReturn Fix

[Sjoerd Meijer via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL323968: [ARM] FullFP16 LowerReturn Fix (authored by SjoerdMeijer, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D42743?vs=132346&id=132373#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D42743

Files:
  llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
  llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll


Index: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
@@ -2491,12 +2491,12 @@
       // t11 f16 = fadd ...
       // t12: i16 = bitcast t11
       //   t13: i32 = zero_extend t12
-      // t14: f32 = bitcast t13
+      // t14: f32 = bitcast t13  <~~~~~~~ Arg
       //
       // to avoid code generation for bitcasts, we simply set Arg to the node
       // that produces the f16 value, t11 in this case.
       //
-      if (Arg.getValueType() == MVT::f32) {
+      if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
         SDValue ZE = Arg.getOperand(0);
         if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
           SDValue BC = ZE.getOperand(0);
Index: llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll
===================================================================
--- llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll
+++ llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll
@@ -1,15 +1,27 @@
 ; SOFT:
-; RUN: llc < %s -mtriple=arm-none-eabi -float-abi=soft     | FileCheck %s --check-prefix=CHECK-SOFT
+; RUN: llc < %s -mtriple=arm-none-eabi -float-abi=soft     | FileCheck %s --check-prefixes=CHECK,CHECK-SOFT
 
 ; SOFTFP:
-; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+vfp3        | FileCheck %s --check-prefix=CHECK-SOFTFP-VFP3
-; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+vfp4        | FileCheck %s --check-prefix=CHECK-SOFTFP-FP16
-; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+fullfp16    | FileCheck %s --check-prefix=CHECK-SOFTFP-FULLFP16
+; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+vfp3        | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-VFP3
+; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+vfp4        | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-FP16
+; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+fullfp16    | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-FULLFP16
 
 ; HARD:
-; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+vfp3      | FileCheck %s --check-prefix=CHECK-HARDFP-VFP3
-; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+vfp4      | FileCheck %s --check-prefix=CHECK-HARDFP-FP16
-; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+fullfp16  | FileCheck %s --check-prefix=CHECK-HARDFP-FULLFP16
+; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+vfp3      | FileCheck %s --check-prefixes=CHECK,CHECK-HARDFP-VFP3
+; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+vfp4      | FileCheck %s --check-prefixes=CHECK,CHECK-HARDFP-FP16
+; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+fullfp16  | FileCheck %s --check-prefixes=CHECK,CHECK-HARDFP-FULLFP16
+
+
+define float @RetValBug(float %A.coerce) local_unnamed_addr {
+entry:
+  ret float undef
+; This expression is optimised away due to the undef value. Check that
+; LowerReturn can handle undef nodes (i.e. nodes which do not have any
+; operands) when FullFP16 is enabled.
+;
+; CHECK-LABEL:            RetValBug:
+; CHECK-HARDFP-FULLFP16:  mov pc, lr
+}
 
 define float @Add(float %a.coerce, float %b.coerce) local_unnamed_addr {
 entry:
@@ -25,6 +37,8 @@
   %5 = bitcast i32 %tmp4.0.insert.ext to float
   ret float %5
 
+; CHECK-LABEL: Add:
+
 ; CHECK-SOFT:  bl  __aeabi_h2f
 ; CHECK-SOFT:  bl  __aeabi_h2f
 ; CHECK-SOFT:  bl  __aeabi_fadd
@@ -64,5 +78,4 @@
 
 ; CHECK-HARDFP-FULLFP16:       vadd.f16  s0, s0, s1
 ; CHECK-HARDFP-FULLFP16-NEXT:  mov pc, lr
-
 }


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