[llvm] r323922 - Followup on Proposal to move MIR physical register namespace to '$' sigil.
Puyan Lotfi via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 31 14:04:29 PST 2018
Modified: llvm/trunk/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir Wed Jan 31 14:04:26 2018
@@ -8,8 +8,8 @@
...
# GCN-LABEL: name: shrink_add_vop3{{$}}
-# GCN: %29:vgpr_32, %9:sreg_64_xexec = V_ADD_I32_e64 %19, %17, implicit %exec
-# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit %exec
+# GCN: %29:vgpr_32, %9:sreg_64_xexec = V_ADD_I32_e64 %19, %17, implicit $exec
+# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit $exec
name: shrink_add_vop3
alignment: 0
exposesReturnsTwice: false
@@ -49,8 +49,8 @@ registers:
- { id: 28, class: vreg_64 }
- { id: 29, class: vgpr_32 }
liveins:
- - { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
- - { reg: '%vgpr0', virtual-reg: '%3' }
+ - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
+ - { reg: '$vgpr0', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -67,32 +67,32 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0:
- liveins: %sgpr0_sgpr1, %vgpr0
+ liveins: $sgpr0_sgpr1, $vgpr0
- %3 = COPY %vgpr0
- %0 = COPY %sgpr0_sgpr1
+ %3 = COPY $vgpr0
+ %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0
- %26 = V_ASHRREV_I32_e32 31, %3, implicit %exec
+ %26 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%27 = REG_SEQUENCE %3, 1, %26, 2
%10 = S_MOV_B32 61440
%11 = S_MOV_B32 0
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2
%13 = REG_SEQUENCE killed %5, 17, %12, 18
- %28 = V_LSHL_B64 killed %27, 2, implicit %exec
+ %28 = V_LSHL_B64 killed %27, 2, implicit $exec
%16 = REG_SEQUENCE killed %4, 17, %12, 18
- %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit %exec
- %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit %exec
- %29, %9 = V_ADD_I32_e64 %19, %17, implicit %exec
- %24 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit %exec
- BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit %exec
+ %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit $exec
+ %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit $exec
+ %29, %9 = V_ADD_I32_e64 %19, %17, implicit $exec
+ %24 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit $exec
+ BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM
...
---
# GCN-LABEL: name: shrink_sub_vop3{{$}}
-# GCN: %29:vgpr_32, %9:sreg_64_xexec = V_SUB_I32_e64 %19, %17, implicit %exec
-# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit %exec
+# GCN: %29:vgpr_32, %9:sreg_64_xexec = V_SUB_I32_e64 %19, %17, implicit $exec
+# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit $exec
name: shrink_sub_vop3
alignment: 0
@@ -133,8 +133,8 @@ registers:
- { id: 28, class: vreg_64 }
- { id: 29, class: vgpr_32 }
liveins:
- - { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
- - { reg: '%vgpr0', virtual-reg: '%3' }
+ - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
+ - { reg: '$vgpr0', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -151,32 +151,32 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0:
- liveins: %sgpr0_sgpr1, %vgpr0
+ liveins: $sgpr0_sgpr1, $vgpr0
- %3 = COPY %vgpr0
- %0 = COPY %sgpr0_sgpr1
+ %3 = COPY $vgpr0
+ %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0
- %26 = V_ASHRREV_I32_e32 31, %3, implicit %exec
+ %26 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%27 = REG_SEQUENCE %3, 1, %26, 2
%10 = S_MOV_B32 61440
%11 = S_MOV_B32 0
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2
%13 = REG_SEQUENCE killed %5, 17, %12, 18
- %28 = V_LSHL_B64 killed %27, 2, implicit %exec
+ %28 = V_LSHL_B64 killed %27, 2, implicit $exec
%16 = REG_SEQUENCE killed %4, 17, %12, 18
- %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit %exec
- %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit %exec
- %29, %9 = V_SUB_I32_e64 %19, %17, implicit %exec
- %24 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit %exec
- BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit %exec
+ %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit $exec
+ %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit $exec
+ %29, %9 = V_SUB_I32_e64 %19, %17, implicit $exec
+ %24 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit $exec
+ BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM
...
---
# GCN-LABEL: name: shrink_subrev_vop3{{$}}
-# GCN: %29:vgpr_32, %9:sreg_64_xexec = V_SUBREV_I32_e64 %19, %17, implicit %exec
-# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit %exec
+# GCN: %29:vgpr_32, %9:sreg_64_xexec = V_SUBREV_I32_e64 %19, %17, implicit $exec
+# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit $exec
name: shrink_subrev_vop3
alignment: 0
@@ -217,8 +217,8 @@ registers:
- { id: 28, class: vreg_64 }
- { id: 29, class: vgpr_32 }
liveins:
- - { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
- - { reg: '%vgpr0', virtual-reg: '%3' }
+ - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
+ - { reg: '$vgpr0', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -235,32 +235,32 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0:
- liveins: %sgpr0_sgpr1, %vgpr0
+ liveins: $sgpr0_sgpr1, $vgpr0
- %3 = COPY %vgpr0
- %0 = COPY %sgpr0_sgpr1
+ %3 = COPY $vgpr0
+ %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0
- %26 = V_ASHRREV_I32_e32 31, %3, implicit %exec
+ %26 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%27 = REG_SEQUENCE %3, 1, %26, 2
%10 = S_MOV_B32 61440
%11 = S_MOV_B32 0
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2
%13 = REG_SEQUENCE killed %5, 17, %12, 18
- %28 = V_LSHL_B64 killed %27, 2, implicit %exec
+ %28 = V_LSHL_B64 killed %27, 2, implicit $exec
%16 = REG_SEQUENCE killed %4, 17, %12, 18
- %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit %exec
- %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit %exec
- %29, %9 = V_SUBREV_I32_e64 %19, %17, implicit %exec
- %24 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit %exec
- BUFFER_STORE_DWORD_ADDR64 %29, %28, killed %16, 0, 0, 0, 0, 0, implicit %exec
+ %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit $exec
+ %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit $exec
+ %29, %9 = V_SUBREV_I32_e64 %19, %17, implicit $exec
+ %24 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit $exec
+ BUFFER_STORE_DWORD_ADDR64 %29, %28, killed %16, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM
...
---
# GCN-LABEL: name: check_addc_src2_vop3{{$}}
-# GCN: %29:vgpr_32, %vcc = V_ADDC_U32_e64 %19, %17, %9, implicit %exec
-# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 1, killed %vcc, implicit %exec
+# GCN: %29:vgpr_32, $vcc = V_ADDC_U32_e64 %19, %17, %9, implicit $exec
+# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 1, killed $vcc, implicit $exec
name: check_addc_src2_vop3
alignment: 0
exposesReturnsTwice: false
@@ -300,8 +300,8 @@ registers:
- { id: 28, class: vreg_64 }
- { id: 29, class: vgpr_32 }
liveins:
- - { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
- - { reg: '%vgpr0', virtual-reg: '%3' }
+ - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
+ - { reg: '$vgpr0', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -318,33 +318,33 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0:
- liveins: %sgpr0_sgpr1, %vgpr0
+ liveins: $sgpr0_sgpr1, $vgpr0
- %3 = COPY %vgpr0
- %0 = COPY %sgpr0_sgpr1
+ %3 = COPY $vgpr0
+ %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0
- %26 = V_ASHRREV_I32_e32 31, %3, implicit %exec
+ %26 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%27 = REG_SEQUENCE %3, 1, %26, 2
%10 = S_MOV_B32 61440
%11 = S_MOV_B32 0
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2
%13 = REG_SEQUENCE killed %5, 17, %12, 18
- %28 = V_LSHL_B64 killed %27, 2, implicit %exec
+ %28 = V_LSHL_B64 killed %27, 2, implicit $exec
%16 = REG_SEQUENCE killed %4, 17, %12, 18
- %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit %exec
- %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit %exec
+ %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit $exec
+ %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit $exec
%9 = S_MOV_B64 0
- %29, %vcc = V_ADDC_U32_e64 %19, %17, %9, implicit %exec
- %24 = V_CNDMASK_B32_e64 0, 1, killed %vcc, implicit %exec
- BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit %exec
+ %29, $vcc = V_ADDC_U32_e64 %19, %17, %9, implicit $exec
+ %24 = V_CNDMASK_B32_e64 0, 1, killed $vcc, implicit $exec
+ BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM
...
---
# GCN-LABEL: name: shrink_addc_vop3{{$}}
-# GCN: %29:vgpr_32 = V_ADDC_U32_e32 %19, %17, implicit-def %vcc, implicit %vcc, implicit %exec
-# GCN %24 = V_CNDMASK_B32_e64 0, 1, killed %vcc, implicit %exec
+# GCN: %29:vgpr_32 = V_ADDC_U32_e32 %19, %17, implicit-def $vcc, implicit $vcc, implicit $exec
+# GCN %24 = V_CNDMASK_B32_e64 0, 1, killed $vcc, implicit $exec
name: shrink_addc_vop3
alignment: 0
@@ -385,8 +385,8 @@ registers:
- { id: 28, class: vreg_64 }
- { id: 29, class: vgpr_32 }
liveins:
- - { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
- - { reg: '%vgpr0', virtual-reg: '%3' }
+ - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
+ - { reg: '$vgpr0', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -403,34 +403,34 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0:
- liveins: %sgpr0_sgpr1, %vgpr0
+ liveins: $sgpr0_sgpr1, $vgpr0
- %3 = COPY %vgpr0
- %0 = COPY %sgpr0_sgpr1
+ %3 = COPY $vgpr0
+ %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0
- %26 = V_ASHRREV_I32_e32 31, %3, implicit %exec
+ %26 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%27 = REG_SEQUENCE %3, 1, %26, 2
%10 = S_MOV_B32 61440
%11 = S_MOV_B32 0
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2
%13 = REG_SEQUENCE killed %5, 17, %12, 18
- %28 = V_LSHL_B64 killed %27, 2, implicit %exec
+ %28 = V_LSHL_B64 killed %27, 2, implicit $exec
%16 = REG_SEQUENCE killed %4, 17, %12, 18
- %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit %exec
- %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit %exec
- %vcc = S_MOV_B64 0
- %29, %vcc = V_ADDC_U32_e64 %19, %17, %vcc, implicit %exec
- %24 = V_CNDMASK_B32_e64 0, 1, killed %vcc, implicit %exec
- BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit %exec
+ %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit $exec
+ %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit $exec
+ $vcc = S_MOV_B64 0
+ %29, $vcc = V_ADDC_U32_e64 %19, %17, $vcc, implicit $exec
+ %24 = V_CNDMASK_B32_e64 0, 1, killed $vcc, implicit $exec
+ BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM
...
---
# GCN-LABEL: name: shrink_addc_undef_vcc{{$}}
-# GCN: %29:vgpr_32 = V_ADDC_U32_e32 %19, %17, implicit-def %vcc, implicit undef %vcc, implicit %exec
-# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 1, killed %vcc, implicit %exec
+# GCN: %29:vgpr_32 = V_ADDC_U32_e32 %19, %17, implicit-def $vcc, implicit undef $vcc, implicit $exec
+# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 1, killed $vcc, implicit $exec
name: shrink_addc_undef_vcc
alignment: 0
exposesReturnsTwice: false
@@ -470,8 +470,8 @@ registers:
- { id: 28, class: vreg_64 }
- { id: 29, class: vgpr_32 }
liveins:
- - { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
- - { reg: '%vgpr0', virtual-reg: '%3' }
+ - { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
+ - { reg: '$vgpr0', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -488,25 +488,25 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0:
- liveins: %sgpr0_sgpr1, %vgpr0
+ liveins: $sgpr0_sgpr1, $vgpr0
- %3 = COPY %vgpr0
- %0 = COPY %sgpr0_sgpr1
+ %3 = COPY $vgpr0
+ %0 = COPY $sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0
- %26 = V_ASHRREV_I32_e32 31, %3, implicit %exec
+ %26 = V_ASHRREV_I32_e32 31, %3, implicit $exec
%27 = REG_SEQUENCE %3, 1, %26, 2
%10 = S_MOV_B32 61440
%11 = S_MOV_B32 0
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2
%13 = REG_SEQUENCE killed %5, 17, %12, 18
- %28 = V_LSHL_B64 killed %27, 2, implicit %exec
+ %28 = V_LSHL_B64 killed %27, 2, implicit $exec
%16 = REG_SEQUENCE killed %4, 17, %12, 18
- %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit %exec
- %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit %exec
- %29, %vcc = V_ADDC_U32_e64 %19, %17, undef %vcc, implicit %exec
- %24 = V_CNDMASK_B32_e64 0, 1, killed %vcc, implicit %exec
- BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit %exec
+ %17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit $exec
+ %19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit $exec
+ %29, $vcc = V_ADDC_U32_e64 %19, %17, undef $vcc, implicit $exec
+ %24 = V_CNDMASK_B32_e64 0, 1, killed $vcc, implicit $exec
+ BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir Wed Jan 31 14:04:26 2018
@@ -19,21 +19,21 @@ body: |
; GCN-LABEL: name: phi_visit_order
; GCN: V_ADD_I32
bb.0:
- liveins: %vgpr0
- %7 = COPY %vgpr0
+ liveins: $vgpr0
+ %7 = COPY $vgpr0
%8 = S_MOV_B32 0
bb.1:
%0 = PHI %8, %bb.0, %0, %bb.1, %2, %bb.2
- %9 = V_MOV_B32_e32 9, implicit %exec
- %10 = V_CMP_EQ_U32_e64 %7, %9, implicit %exec
- %1 = SI_IF %10, %bb.2, implicit-def %exec, implicit-def %scc, implicit %exec
+ %9 = V_MOV_B32_e32 9, implicit $exec
+ %10 = V_CMP_EQ_U32_e64 %7, %9, implicit $exec
+ %1 = SI_IF %10, %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
S_BRANCH %bb.1
bb.2:
- SI_END_CF %1, implicit-def %exec, implicit-def %scc, implicit %exec
+ SI_END_CF %1, implicit-def $exec, implicit-def $scc, implicit $exec
%11 = S_MOV_B32 1
- %2 = S_ADD_I32 %0, %11, implicit-def %scc
+ %2 = S_ADD_I32 %0, %11, implicit-def $scc
S_BRANCH %bb.1
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll Wed Jan 31 14:04:26 2018
@@ -3,7 +3,7 @@
; register operands in the correct order when modifying the opcode of an
; instruction to V_ADD_I32_e32.
-; CHECK: %{{[0-9]+}}:vgpr_32 = V_ADD_I32_e32 %{{[0-9]+}}, %{{[0-9]+}}, implicit-def %vcc, implicit %exec
+; CHECK: %{{[0-9]+}}:vgpr_32 = V_ADD_I32_e32 %{{[0-9]+}}, %{{[0-9]+}}, implicit-def $vcc, implicit $exec
define amdgpu_kernel void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
entry:
Modified: llvm/trunk/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/spill-empty-live-interval.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/spill-empty-live-interval.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/spill-empty-live-interval.mir Wed Jan 31 14:04:26 2018
@@ -7,13 +7,13 @@
# CHECK-LABEL: name: expecting_non_empty_interval
-# CHECK: undef %7.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %7.sub1, implicit %exec
-# CHECK-NEXT: SI_SPILL_V64_SAVE %7, %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (store 8 into %stack.0, align 4)
-# CHECK-NEXT: undef %5.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit %exec
-# CHECK-NEXT: dead %2:vgpr_32 = V_MUL_F32_e32 0, %5.sub1, implicit %exec
+# CHECK: undef %7.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %7.sub1, implicit $exec
+# CHECK-NEXT: SI_SPILL_V64_SAVE %7, %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec :: (store 8 into %stack.0, align 4)
+# CHECK-NEXT: undef %5.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit $exec
+# CHECK-NEXT: dead %2:vgpr_32 = V_MUL_F32_e32 0, %5.sub1, implicit $exec
# CHECK: S_NOP 0, implicit %6.sub1
-# CHECK-NEXT: %8:vreg_64 = SI_SPILL_V64_RESTORE %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (load 8 from %stack.0, align 4)
+# CHECK-NEXT: %8:vreg_64 = SI_SPILL_V64_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec :: (load 8 from %stack.0, align 4)
# CHECK-NEXT: S_NOP 0, implicit %8.sub1
# CHECK-NEXT: S_NOP 0, implicit undef %9.sub0
@@ -27,9 +27,9 @@ registers:
body: |
bb.0:
successors: %bb.1
- undef %0.sub1 = V_MAC_F32_e32 0, undef %1, undef %0.sub1, implicit %exec
- undef %3.sub1 = V_MOV_B32_e32 1786773504, implicit %exec
- dead %2 = V_MUL_F32_e32 0, %3.sub1, implicit %exec
+ undef %0.sub1 = V_MAC_F32_e32 0, undef %1, undef %0.sub1, implicit $exec
+ undef %3.sub1 = V_MOV_B32_e32 1786773504, implicit $exec
+ dead %2 = V_MUL_F32_e32 0, %3.sub1, implicit $exec
bb.1:
S_NOP 0, implicit %3.sub1
@@ -44,12 +44,12 @@ body: |
# CHECK-LABEL: name: rematerialize_empty_interval_has_reference
# CHECK-NOT: MOV
-# CHECK: undef %3.sub2:vreg_128 = V_MOV_B32_e32 1786773504, implicit %exec
+# CHECK: undef %3.sub2:vreg_128 = V_MOV_B32_e32 1786773504, implicit $exec
# CHECK: bb.1:
# CHECK-NEXT: S_NOP 0, implicit %3.sub2
# CHECK-NEXT: S_NOP 0, implicit undef %6.sub0
-# CHECK-NEXT: undef %4.sub2:vreg_128 = V_MOV_B32_e32 0, implicit %exec
+# CHECK-NEXT: undef %4.sub2:vreg_128 = V_MOV_B32_e32 0, implicit $exec
# CHECK-NEXT: S_NOP 0, implicit %4.sub2
name: rematerialize_empty_interval_has_reference
tracksRegLiveness: true
@@ -62,8 +62,8 @@ body: |
bb.0:
successors: %bb.1
- undef %0.sub2 = V_MOV_B32_e32 0, implicit %exec
- undef %3.sub2 = V_MOV_B32_e32 1786773504, implicit %exec
+ undef %0.sub2 = V_MOV_B32_e32 0, implicit $exec
+ undef %3.sub2 = V_MOV_B32_e32 1786773504, implicit $exec
bb.1:
S_NOP 0, implicit %3.sub2
Modified: llvm/trunk/test/CodeGen/AMDGPU/splitkit.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/splitkit.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/splitkit.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/splitkit.mir Wed Jan 31 14:04:26 2018
@@ -22,7 +22,7 @@ body: |
S_NOP 0, implicit-def %0.sub3 : sreg_128
; Clobber registers
- S_NOP 0, implicit-def dead %sgpr0, implicit-def dead %sgpr1, implicit-def dead %sgpr2, implicit-def dead %sgpr3, implicit-def dead %sgpr4, implicit-def dead %sgpr5, implicit-def dead %sgpr6, implicit-def dead %sgpr7, implicit-def dead %sgpr8, implicit-def dead %sgpr9, implicit-def dead %sgpr10, implicit-def dead %sgpr11
+ S_NOP 0, implicit-def dead $sgpr0, implicit-def dead $sgpr1, implicit-def dead $sgpr2, implicit-def dead $sgpr3, implicit-def dead $sgpr4, implicit-def dead $sgpr5, implicit-def dead $sgpr6, implicit-def dead $sgpr7, implicit-def dead $sgpr8, implicit-def dead $sgpr9, implicit-def dead $sgpr10, implicit-def dead $sgpr11
S_NOP 0, implicit %0.sub0
S_NOP 0, implicit %0.sub3
@@ -34,31 +34,31 @@ body: |
# allocated to sgpr0_sgpr1 and the first to something else so we see two copies
# in between for the two subregisters that are alive.
# CHECK-LABEL: name: func1
-# CHECK: [[REG0:%sgpr[0-9]+]] = COPY %sgpr0
-# CHECK: [[REG1:%sgpr[0-9]+]] = COPY %sgpr2
+# CHECK: [[REG0:\$sgpr[0-9]+]] = COPY $sgpr0
+# CHECK: [[REG1:\$sgpr[0-9]+]] = COPY $sgpr2
# CHECK: S_NOP 0
# CHECK: S_NOP 0, implicit renamable [[REG0]]
# CHECK: S_NOP 0, implicit renamable [[REG1]]
-# CHECK: %sgpr0 = COPY renamable [[REG0]]
-# CHECK: %sgpr2 = COPY renamable [[REG1]]
+# CHECK: $sgpr0 = COPY renamable [[REG0]]
+# CHECK: $sgpr2 = COPY renamable [[REG1]]
# CHECK: S_NOP
-# CHECK: S_NOP 0, implicit renamable %sgpr0
-# CHECK: S_NOP 0, implicit renamable %sgpr2
+# CHECK: S_NOP 0, implicit renamable $sgpr0
+# CHECK: S_NOP 0, implicit renamable $sgpr2
name: func1
tracksRegLiveness: true
body: |
bb.0:
- liveins: %sgpr0, %sgpr1, %sgpr2
- undef %0.sub0 : sreg_128 = COPY %sgpr0
- %0.sub2 = COPY %sgpr2
+ liveins: $sgpr0, $sgpr1, $sgpr2
+ undef %0.sub0 : sreg_128 = COPY $sgpr0
+ %0.sub2 = COPY $sgpr2
- S_NOP 0, implicit-def dead %sgpr0, implicit-def dead %sgpr1
+ S_NOP 0, implicit-def dead $sgpr0, implicit-def dead $sgpr1
S_NOP 0, implicit %0.sub0
S_NOP 0, implicit %0.sub2
; Clobber everything but sgpr0-sgpr3
- S_NOP 0, implicit-def dead %sgpr4, implicit-def dead %sgpr5, implicit-def dead %sgpr6, implicit-def dead %sgpr7, implicit-def dead %sgpr8, implicit-def dead %sgpr9, implicit-def dead %sgpr10, implicit-def dead %sgpr11, implicit-def dead %sgpr12, implicit-def dead %sgpr13, implicit-def dead %sgpr14, implicit-def dead %sgpr15, implicit-def dead %vcc_lo, implicit-def dead %vcc_hi
+ S_NOP 0, implicit-def dead $sgpr4, implicit-def dead $sgpr5, implicit-def dead $sgpr6, implicit-def dead $sgpr7, implicit-def dead $sgpr8, implicit-def dead $sgpr9, implicit-def dead $sgpr10, implicit-def dead $sgpr11, implicit-def dead $sgpr12, implicit-def dead $sgpr13, implicit-def dead $sgpr14, implicit-def dead $sgpr15, implicit-def dead $vcc_lo, implicit-def dead $vcc_hi
S_NOP 0, implicit %0.sub0
S_NOP 0, implicit %0.sub2
@@ -67,8 +67,8 @@ body: |
# Check that copy hoisting out of loops works. This mainly should not crash the
# compiler when it hoists a subreg copy sequence.
# CHECK-LABEL: name: splitHoist
-# CHECK: S_NOP 0, implicit-def renamable %sgpr0
-# CHECK: S_NOP 0, implicit-def renamable %sgpr3
+# CHECK: S_NOP 0, implicit-def renamable $sgpr0
+# CHECK: S_NOP 0, implicit-def renamable $sgpr3
# CHECK-NEXT: SI_SPILL_S128_SAVE
name: splitHoist
tracksRegLiveness: true
@@ -78,7 +78,7 @@ body: |
S_NOP 0, implicit-def undef %0.sub0 : sreg_128
S_NOP 0, implicit-def %0.sub3 : sreg_128
- S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
+ S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
S_BRANCH %bb.2
bb.1:
@@ -86,15 +86,15 @@ body: |
S_NOP 0, implicit %0.sub0
; Clobber registers
- S_NOP 0, implicit-def dead %sgpr0, implicit-def dead %sgpr1, implicit-def dead %sgpr2, implicit-def dead %sgpr3, implicit-def dead %sgpr4, implicit-def dead %sgpr5, implicit-def dead %sgpr6, implicit-def dead %sgpr7, implicit-def dead %sgpr8, implicit-def dead %sgpr9, implicit-def dead %sgpr10, implicit-def dead %sgpr11
+ S_NOP 0, implicit-def dead $sgpr0, implicit-def dead $sgpr1, implicit-def dead $sgpr2, implicit-def dead $sgpr3, implicit-def dead $sgpr4, implicit-def dead $sgpr5, implicit-def dead $sgpr6, implicit-def dead $sgpr7, implicit-def dead $sgpr8, implicit-def dead $sgpr9, implicit-def dead $sgpr10, implicit-def dead $sgpr11
- S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
+ S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
S_BRANCH %bb.3
bb.2:
successors: %bb.3
; Clobber registers
- S_NOP 0, implicit-def dead %sgpr0, implicit-def dead %sgpr1, implicit-def dead %sgpr2, implicit-def dead %sgpr3, implicit-def dead %sgpr4, implicit-def dead %sgpr5, implicit-def dead %sgpr6, implicit-def dead %sgpr7, implicit-def dead %sgpr8, implicit-def dead %sgpr9, implicit-def dead %sgpr10, implicit-def dead %sgpr11
+ S_NOP 0, implicit-def dead $sgpr0, implicit-def dead $sgpr1, implicit-def dead $sgpr2, implicit-def dead $sgpr3, implicit-def dead $sgpr4, implicit-def dead $sgpr5, implicit-def dead $sgpr6, implicit-def dead $sgpr7, implicit-def dead $sgpr8, implicit-def dead $sgpr9, implicit-def dead $sgpr10, implicit-def dead $sgpr11
S_BRANCH %bb.3
bb.3:
Modified: llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir Wed Jan 31 14:04:26 2018
@@ -9,11 +9,11 @@
# CHECK: - { id: 1, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
# CHECK-NEXT: stack-id: 1,
-# CHECK: SI_SPILL_V32_SAVE killed %vgpr0, %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (store 4 into %stack.0)
-# CHECK: %vgpr0 = SI_SPILL_V32_RESTORE %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (load 4 from %stack.0)
+# CHECK: SI_SPILL_V32_SAVE killed $vgpr0, %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec :: (store 4 into %stack.0)
+# CHECK: $vgpr0 = SI_SPILL_V32_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec :: (load 4 from %stack.0)
-# CHECK: SI_SPILL_S32_SAVE killed renamable %sgpr6, %stack.1, implicit %exec, implicit %sgpr0_sgpr1_sgpr2_sgpr3, implicit %sgpr5, implicit-def dead %m0 :: (store 4 into %stack.1)
-# CHECK: %sgpr6 = SI_SPILL_S32_RESTORE %stack.1, implicit %exec, implicit %sgpr0_sgpr1_sgpr2_sgpr3, implicit %sgpr5, implicit-def dead %m0 :: (load 4 from %stack.1)
+# CHECK: SI_SPILL_S32_SAVE killed renamable $sgpr6, %stack.1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5, implicit-def dead $m0 :: (store 4 into %stack.1)
+# CHECK: $sgpr6 = SI_SPILL_S32_RESTORE %stack.1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5, implicit-def dead $m0 :: (load 4 from %stack.1)
name: no_merge_sgpr_vgpr_spill_slot
tracksRegLiveness: true
@@ -25,10 +25,10 @@ registers:
body: |
bb.0:
- %0 = FLAT_LOAD_DWORD undef %vgpr0_vgpr1, 0, 0, 0, implicit %flat_scr, implicit %exec
- %2 = FLAT_LOAD_DWORD undef %vgpr0_vgpr1, 0, 0, 0, implicit %flat_scr, implicit %exec
+ %0 = FLAT_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, 0, implicit $flat_scr, implicit $exec
+ %2 = FLAT_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, 0, implicit $flat_scr, implicit $exec
S_NOP 0, implicit %0
- %1 = S_LOAD_DWORD_IMM undef %sgpr0_sgpr1, 0, 0
- %3 = S_LOAD_DWORD_IMM undef %sgpr0_sgpr1, 0, 0
+ %1 = S_LOAD_DWORD_IMM undef $sgpr0_sgpr1, 0, 0
+ %3 = S_LOAD_DWORD_IMM undef $sgpr0_sgpr1, 0, 0
S_NOP 0, implicit %1
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/subreg-intervals.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/subreg-intervals.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/subreg-intervals.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/subreg-intervals.mir Wed Jan 31 14:04:26 2018
@@ -31,7 +31,7 @@ registers:
- { id: 0, class: sreg_64 }
body: |
bb.0:
- S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
+ S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
S_BRANCH %bb.2
bb.1:
Modified: llvm/trunk/test/CodeGen/AMDGPU/subreg_interference.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/subreg_interference.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/subreg_interference.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/subreg_interference.mir Wed Jan 31 14:04:26 2018
@@ -12,12 +12,12 @@
# sgpr0-sgpr3.
#
# CHECK-LABEL: func0
-# CHECK: S_NOP 0, implicit-def renamable %sgpr0
-# CHECK: S_NOP 0, implicit-def renamable %sgpr3
-# CHECK: S_NOP 0, implicit-def renamable %sgpr1
-# CHECK: S_NOP 0, implicit-def renamable %sgpr2
-# CHECK: S_NOP 0, implicit renamable %sgpr0, implicit renamable %sgpr3
-# CHECK: S_NOP 0, implicit renamable %sgpr1, implicit renamable %sgpr2
+# CHECK: S_NOP 0, implicit-def renamable $sgpr0
+# CHECK: S_NOP 0, implicit-def renamable $sgpr3
+# CHECK: S_NOP 0, implicit-def renamable $sgpr1
+# CHECK: S_NOP 0, implicit-def renamable $sgpr2
+# CHECK: S_NOP 0, implicit renamable $sgpr0, implicit renamable $sgpr3
+# CHECK: S_NOP 0, implicit renamable $sgpr1, implicit renamable $sgpr2
name: func0
body: |
bb.0:
Modified: llvm/trunk/test/CodeGen/AMDGPU/syncscopes.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/syncscopes.ll?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/syncscopes.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/syncscopes.ll Wed Jan 31 14:04:26 2018
@@ -1,9 +1,9 @@
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -stop-before=si-debugger-insert-nops < %s | FileCheck --check-prefix=GCN %s
; GCN-LABEL: name: syncscopes
-; GCN: FLAT_STORE_DWORD killed renamable %vgpr1_vgpr2, killed renamable %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("agent") seq_cst 4 into %ir.agent_out, addrspace 4)
-; GCN: FLAT_STORE_DWORD killed renamable %vgpr4_vgpr5, killed renamable %vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out, addrspace 4)
-; GCN: FLAT_STORE_DWORD killed renamable %vgpr7_vgpr8, killed renamable %vgpr6, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out, addrspace 4)
+; GCN: FLAT_STORE_DWORD killed renamable $vgpr1_vgpr2, killed renamable $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile store syncscope("agent") seq_cst 4 into %ir.agent_out, addrspace 4)
+; GCN: FLAT_STORE_DWORD killed renamable $vgpr4_vgpr5, killed renamable $vgpr3, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out, addrspace 4)
+; GCN: FLAT_STORE_DWORD killed renamable $vgpr7_vgpr8, killed renamable $vgpr6, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out, addrspace 4)
define void @syncscopes(
i32 %agent,
i32 addrspace(4)* %agent_out,
Modified: llvm/trunk/test/CodeGen/AMDGPU/twoaddr-mad.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/twoaddr-mad.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/twoaddr-mad.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/twoaddr-mad.mir Wed Jan 31 14:04:26 2018
@@ -1,7 +1,7 @@
# RUN: llc -march=amdgcn %s -run-pass twoaddressinstruction -verify-machineinstrs -o - | FileCheck -check-prefix=GCN %s
# GCN-LABEL: name: test_madmk_reg_imm_f32
-# GCN: V_MADMK_F32 killed %0.sub0, 1078523331, killed %1, implicit %exec
+# GCN: V_MADMK_F32 killed %0.sub0, 1078523331, killed %1, implicit $exec
---
name: test_madmk_reg_imm_f32
registers:
@@ -14,13 +14,13 @@ body: |
%0 = IMPLICIT_DEF
%1 = COPY %0.sub1
- %2 = V_MOV_B32_e32 1078523331, implicit %exec
- %3 = V_MAC_F32_e32 killed %0.sub0, %2, killed %1, implicit %exec
+ %2 = V_MOV_B32_e32 1078523331, implicit $exec
+ %3 = V_MAC_F32_e32 killed %0.sub0, %2, killed %1, implicit $exec
...
# GCN-LABEL: name: test_madmk_imm_reg_f32
-# GCN: V_MADMK_F32 killed %0.sub0, 1078523331, killed %1, implicit %exec
+# GCN: V_MADMK_F32 killed %0.sub0, 1078523331, killed %1, implicit $exec
---
name: test_madmk_imm_reg_f32
registers:
@@ -33,13 +33,13 @@ body: |
%0 = IMPLICIT_DEF
%1 = COPY %0.sub1
- %2 = V_MOV_B32_e32 1078523331, implicit %exec
- %3 = V_MAC_F32_e32 %2, killed %0.sub0, killed %1, implicit %exec
+ %2 = V_MOV_B32_e32 1078523331, implicit $exec
+ %3 = V_MAC_F32_e32 %2, killed %0.sub0, killed %1, implicit $exec
...
# GCN-LABEL: name: test_madak_f32
-# GCN: V_MADAK_F32 killed %0.sub0, %0.sub1, 1078523331, implicit %exec
+# GCN: V_MADAK_F32 killed %0.sub0, %0.sub1, 1078523331, implicit $exec
---
name: test_madak_f32
registers:
@@ -50,13 +50,13 @@ body: |
bb.0:
%0 = IMPLICIT_DEF
- %1 = V_MOV_B32_e32 1078523331, implicit %exec
- %2 = V_MAC_F32_e32 killed %0.sub0, %0.sub1, %1, implicit %exec
+ %1 = V_MOV_B32_e32 1078523331, implicit $exec
+ %2 = V_MAC_F32_e32 killed %0.sub0, %0.sub1, %1, implicit $exec
...
# GCN-LABEL: name: test_madmk_reg_imm_f16
-# GCN: V_MADMK_F16 killed %0.sub0, 1078523331, killed %1, implicit %exec
+# GCN: V_MADMK_F16 killed %0.sub0, 1078523331, killed %1, implicit $exec
---
name: test_madmk_reg_imm_f16
registers:
@@ -69,13 +69,13 @@ body: |
%0 = IMPLICIT_DEF
%1 = COPY %0.sub1
- %2 = V_MOV_B32_e32 1078523331, implicit %exec
- %3 = V_MAC_F16_e32 killed %0.sub0, %2, killed %1, implicit %exec
+ %2 = V_MOV_B32_e32 1078523331, implicit $exec
+ %3 = V_MAC_F16_e32 killed %0.sub0, %2, killed %1, implicit $exec
...
# GCN-LABEL: name: test_madmk_imm_reg_f16
-# GCN: V_MADMK_F16 killed %0.sub0, 1078523331, killed %1, implicit %exec
+# GCN: V_MADMK_F16 killed %0.sub0, 1078523331, killed %1, implicit $exec
---
name: test_madmk_imm_reg_f16
registers:
@@ -88,13 +88,13 @@ body: |
%0 = IMPLICIT_DEF
%1 = COPY %0.sub1
- %2 = V_MOV_B32_e32 1078523331, implicit %exec
- %3 = V_MAC_F16_e32 %2, killed %0.sub0, killed %1, implicit %exec
+ %2 = V_MOV_B32_e32 1078523331, implicit $exec
+ %3 = V_MAC_F16_e32 %2, killed %0.sub0, killed %1, implicit $exec
...
# GCN-LABEL: name: test_madak_f16
-# GCN: V_MADAK_F16 killed %0.sub0, %0.sub1, 1078523331, implicit %exec
+# GCN: V_MADAK_F16 killed %0.sub0, %0.sub1, 1078523331, implicit $exec
---
name: test_madak_f16
registers:
@@ -105,15 +105,15 @@ body: |
bb.0:
%0 = IMPLICIT_DEF
- %1 = V_MOV_B32_e32 1078523331, implicit %exec
- %2 = V_MAC_F16_e32 killed %0.sub0, %0.sub1, %1, implicit %exec
+ %1 = V_MOV_B32_e32 1078523331, implicit $exec
+ %2 = V_MAC_F16_e32 killed %0.sub0, %0.sub1, %1, implicit $exec
...
# Make sure constant bus restriction isn't violated if src0 is an SGPR.
# GCN-LABEL: name: test_madak_sgpr_src0_f32
-# GCN: %1:vgpr_32 = V_MOV_B32_e32 1078523331, implicit %exec
-# GCN: %2:vgpr_32 = V_MAD_F32 0, killed %0, 0, %1, 0, %3:vgpr_32, 0, 0, implicit %exec
+# GCN: %1:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec
+# GCN: %2:vgpr_32 = V_MAD_F32 0, killed %0, 0, %1, 0, %3:vgpr_32, 0, 0, implicit $exec
---
name: test_madak_sgpr_src0_f32
@@ -126,15 +126,15 @@ body: |
bb.0:
%0 = IMPLICIT_DEF
- %1 = V_MOV_B32_e32 1078523331, implicit %exec
- %2 = V_MAC_F32_e32 killed %0, %1, %3, implicit %exec
+ %1 = V_MOV_B32_e32 1078523331, implicit $exec
+ %2 = V_MAC_F32_e32 killed %0, %1, %3, implicit $exec
...
# This can still fold if this is an inline immediate.
# GCN-LABEL: name: test_madak_inlineimm_src0_f32
-# GCN: %1:vgpr_32 = V_MADMK_F32 1073741824, 1078523331, %2:vgpr_32, implicit %exec
+# GCN: %1:vgpr_32 = V_MADMK_F32 1073741824, 1078523331, %2:vgpr_32, implicit $exec
---
name: test_madak_inlineimm_src0_f32
@@ -145,14 +145,14 @@ registers:
body: |
bb.0:
- %0 = V_MOV_B32_e32 1078523331, implicit %exec
- %1 = V_MAC_F32_e32 1073741824, %0, %2, implicit %exec
+ %0 = V_MOV_B32_e32 1078523331, implicit $exec
+ %1 = V_MAC_F32_e32 1073741824, %0, %2, implicit $exec
...
# Non-inline immediate uses constant bus already.
# GCN-LABEL: name: test_madak_otherimm_src0_f32
-# GCN: %1:vgpr_32 = V_MAC_F32_e32 1120403456, %0, %1, implicit %exec
+# GCN: %1:vgpr_32 = V_MAC_F32_e32 1120403456, %0, %1, implicit $exec
---
name: test_madak_otherimm_src0_f32
@@ -163,14 +163,14 @@ registers:
body: |
bb.0:
- %0 = V_MOV_B32_e32 1078523331, implicit %exec
- %1 = V_MAC_F32_e32 1120403456, %0, %2, implicit %exec
+ %0 = V_MOV_B32_e32 1078523331, implicit $exec
+ %1 = V_MAC_F32_e32 1120403456, %0, %2, implicit $exec
...
# Non-inline immediate uses constant bus already.
# GCN-LABEL: name: test_madak_other_constantlike_src0_f32
-# GCN: %1:vgpr_32 = V_MAC_F32_e32 %stack.0, %0, %1, implicit %exec
+# GCN: %1:vgpr_32 = V_MAC_F32_e32 %stack.0, %0, %1, implicit $exec
---
name: test_madak_other_constantlike_src0_f32
registers:
@@ -184,7 +184,7 @@ stack:
body: |
bb.0:
- %0 = V_MOV_B32_e32 1078523331, implicit %exec
- %1 = V_MAC_F32_e32 %stack.0, %0, %2, implicit %exec
+ %0 = V_MOV_B32_e32 1078523331, implicit $exec
+ %1 = V_MAC_F32_e32 %stack.0, %0, %2, implicit $exec
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir Wed Jan 31 14:04:26 2018
@@ -17,10 +17,10 @@
# leaving a spill of the undefined register.
# CHECK-LABEL: name: undefined_physreg_sgpr_spill
-# CHECK: %sgpr0_sgpr1 = COPY %exec, implicit-def %exec
-# CHECK-NEXT: SI_SPILL_S64_SAVE %sgpr0_sgpr1,
-# CHECK-NEXT: %sgpr2_sgpr3 = S_AND_B64 killed %sgpr0_sgpr1, killed %vcc, implicit-def dead %scc
-# CHECK: %exec = COPY killed %sgpr2_sgpr3
+# CHECK: $sgpr0_sgpr1 = COPY $exec, implicit-def $exec
+# CHECK-NEXT: SI_SPILL_S64_SAVE $sgpr0_sgpr1,
+# CHECK-NEXT: $sgpr2_sgpr3 = S_AND_B64 killed $sgpr0_sgpr1, killed $vcc, implicit-def dead $scc
+# CHECK: $exec = COPY killed $sgpr2_sgpr3
name: undefined_physreg_sgpr_spill
alignment: 0
exposesReturnsTwice: false
@@ -30,8 +30,8 @@ selected: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '%vgpr0', virtual-reg: '' }
- - { reg: '%sgpr4_sgpr5', virtual-reg: '' }
+ - { reg: '$vgpr0', virtual-reg: '' }
+ - { reg: '$sgpr4_sgpr5', virtual-reg: '' }
stack:
- { id: 0, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
stack-id: 1, callee-saved-register: '', callee-saved-restored: true,
@@ -40,39 +40,39 @@ constants:
body: |
bb.0:
successors: %bb.1, %bb.2
- liveins: %vgpr0, %sgpr4_sgpr5
+ liveins: $vgpr0, $sgpr4_sgpr5
- %vgpr1_vgpr2 = COPY killed %sgpr4_sgpr5, implicit %exec
- %vgpr1 = GLOBAL_LOAD_UBYTE killed %vgpr1_vgpr2, 0, 0, 0, implicit %exec :: (non-temporal dereferenceable invariant load 1 from `i1 addrspace(2)* undef`)
- %vcc = V_CMP_NE_U32_e64 0, %vgpr0, implicit %exec
- %sgpr0_sgpr1 = V_CMP_EQ_U32_e64 1, killed %vgpr1, implicit %exec
- %vgpr1 = V_CNDMASK_B32_e64 0, -1, killed %sgpr0_sgpr1, implicit %exec
- %sgpr0_sgpr1 = COPY %exec, implicit-def %exec
- SI_SPILL_S64_SAVE %sgpr0_sgpr1, %stack.0, implicit %exec, implicit %sgpr8_sgpr9_sgpr10_sgpr11, implicit %sgpr13, implicit-def dead %m0 :: (store 8 into %stack.0, align 4)
- %sgpr2_sgpr3 = S_AND_B64 killed %sgpr0_sgpr1, killed %vcc, implicit-def dead %scc
- %exec = S_MOV_B64_term killed %sgpr2_sgpr3
- SI_MASK_BRANCH %bb.2, implicit %exec
+ $vgpr1_vgpr2 = COPY killed $sgpr4_sgpr5, implicit $exec
+ $vgpr1 = GLOBAL_LOAD_UBYTE killed $vgpr1_vgpr2, 0, 0, 0, implicit $exec :: (non-temporal dereferenceable invariant load 1 from `i1 addrspace(2)* undef`)
+ $vcc = V_CMP_NE_U32_e64 0, $vgpr0, implicit $exec
+ $sgpr0_sgpr1 = V_CMP_EQ_U32_e64 1, killed $vgpr1, implicit $exec
+ $vgpr1 = V_CNDMASK_B32_e64 0, -1, killed $sgpr0_sgpr1, implicit $exec
+ $sgpr0_sgpr1 = COPY $exec, implicit-def $exec
+ SI_SPILL_S64_SAVE $sgpr0_sgpr1, %stack.0, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $sgpr13, implicit-def dead $m0 :: (store 8 into %stack.0, align 4)
+ $sgpr2_sgpr3 = S_AND_B64 killed $sgpr0_sgpr1, killed $vcc, implicit-def dead $scc
+ $exec = S_MOV_B64_term killed $sgpr2_sgpr3
+ SI_MASK_BRANCH %bb.2, implicit $exec
S_BRANCH %bb.1
bb.1:
successors: %bb.3(0x80000000)
- liveins: %vgpr0, %vgpr1
+ liveins: $vgpr0, $vgpr1
- %sgpr2_sgpr3 = S_MOV_B64 0
- %vgpr2 = V_MOV_B32_e32 0, implicit %exec
- %sgpr4_sgpr5 = IMPLICIT_DEF
+ $sgpr2_sgpr3 = S_MOV_B64 0
+ $vgpr2 = V_MOV_B32_e32 0, implicit $exec
+ $sgpr4_sgpr5 = IMPLICIT_DEF
S_BRANCH %bb.3
bb.2:
successors:
- %sgpr0_sgpr1 = SI_SPILL_S64_RESTORE %stack.0, implicit %exec, implicit %sgpr8_sgpr9_sgpr10_sgpr11, implicit %sgpr13, implicit-def dead %m0 :: (load 8 from %stack.0, align 4)
- %exec = S_OR_B64 %exec, killed %sgpr0_sgpr1, implicit-def %scc
+ $sgpr0_sgpr1 = SI_SPILL_S64_RESTORE %stack.0, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $sgpr13, implicit-def dead $m0 :: (load 8 from %stack.0, align 4)
+ $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
bb.3:
- liveins: %vgpr0, %vgpr1, %vgpr2, %sgpr2_sgpr3, %sgpr4_sgpr5
+ liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr2_sgpr3, $sgpr4_sgpr5
- %vcc = COPY %vgpr1
+ $vcc = COPY $vgpr1
S_ENDPGM
...
@@ -80,10 +80,10 @@ body: |
# Move spill to after future save instruction
# CHECK-LABEL: {{^}}name: undefined_physreg_sgpr_spill_reorder
-# CHECK: %sgpr0_sgpr1 = COPY %exec, implicit-def %exec
-# CHECK: %sgpr2_sgpr3 = S_AND_B64 %sgpr0_sgpr1, killed %vcc, implicit-def dead %scc
-# CHECK: SI_SPILL_S64_SAVE killed %sgpr0_sgpr1, %stack.0, implicit %exec, implicit %sgpr8_sgpr9_sgpr10_sgpr11, implicit %sgpr13, implicit-def dead %m0 :: (store 8 into %stack.0, align 4)
-# CHECK: %exec = COPY killed %sgpr2_sgpr3
+# CHECK: $sgpr0_sgpr1 = COPY $exec, implicit-def $exec
+# CHECK: $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def dead $scc
+# CHECK: SI_SPILL_S64_SAVE killed $sgpr0_sgpr1, %stack.0, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $sgpr13, implicit-def dead $m0 :: (store 8 into %stack.0, align 4)
+# CHECK: $exec = COPY killed $sgpr2_sgpr3
name: undefined_physreg_sgpr_spill_reorder
alignment: 0
exposesReturnsTwice: false
@@ -93,8 +93,8 @@ selected: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '%vgpr0', virtual-reg: '' }
- - { reg: '%sgpr4_sgpr5', virtual-reg: '' }
+ - { reg: '$vgpr0', virtual-reg: '' }
+ - { reg: '$sgpr4_sgpr5', virtual-reg: '' }
stack:
- { id: 0, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
stack-id: 1, callee-saved-register: '', callee-saved-restored: true,
@@ -103,39 +103,39 @@ constants:
body: |
bb.0:
successors: %bb.1, %bb.2
- liveins: %vgpr0, %sgpr4_sgpr5
+ liveins: $vgpr0, $sgpr4_sgpr5
- %vgpr1_vgpr2 = COPY killed %sgpr4_sgpr5, implicit %exec
- %vgpr1 = GLOBAL_LOAD_UBYTE killed %vgpr1_vgpr2, 0, 0, 0, implicit %exec :: (non-temporal dereferenceable invariant load 1 from `i1 addrspace(2)* undef`)
- %vcc = V_CMP_NE_U32_e64 0, %vgpr0, implicit %exec
- %sgpr0_sgpr1 = V_CMP_EQ_U32_e64 1, killed %vgpr1, implicit %exec
- %vgpr1 = V_CNDMASK_B32_e64 0, -1, killed %sgpr0_sgpr1, implicit %exec
- %sgpr0_sgpr1 = COPY %exec, implicit-def %exec
- %sgpr2_sgpr3 = S_AND_B64 %sgpr0_sgpr1, killed %vcc, implicit-def dead %scc
- SI_SPILL_S64_SAVE killed %sgpr0_sgpr1, %stack.0, implicit %exec, implicit %sgpr8_sgpr9_sgpr10_sgpr11, implicit %sgpr13, implicit-def dead %m0 :: (store 8 into %stack.0, align 4)
- %exec = S_MOV_B64_term killed %sgpr2_sgpr3
- SI_MASK_BRANCH %bb.2, implicit %exec
+ $vgpr1_vgpr2 = COPY killed $sgpr4_sgpr5, implicit $exec
+ $vgpr1 = GLOBAL_LOAD_UBYTE killed $vgpr1_vgpr2, 0, 0, 0, implicit $exec :: (non-temporal dereferenceable invariant load 1 from `i1 addrspace(2)* undef`)
+ $vcc = V_CMP_NE_U32_e64 0, $vgpr0, implicit $exec
+ $sgpr0_sgpr1 = V_CMP_EQ_U32_e64 1, killed $vgpr1, implicit $exec
+ $vgpr1 = V_CNDMASK_B32_e64 0, -1, killed $sgpr0_sgpr1, implicit $exec
+ $sgpr0_sgpr1 = COPY $exec, implicit-def $exec
+ $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def dead $scc
+ SI_SPILL_S64_SAVE killed $sgpr0_sgpr1, %stack.0, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $sgpr13, implicit-def dead $m0 :: (store 8 into %stack.0, align 4)
+ $exec = S_MOV_B64_term killed $sgpr2_sgpr3
+ SI_MASK_BRANCH %bb.2, implicit $exec
S_BRANCH %bb.1
bb.1:
successors: %bb.3(0x80000000)
- liveins: %vgpr0, %vgpr1
+ liveins: $vgpr0, $vgpr1
- %sgpr2_sgpr3 = S_MOV_B64 0
- %vgpr2 = V_MOV_B32_e32 0, implicit %exec
- %sgpr4_sgpr5 = IMPLICIT_DEF
+ $sgpr2_sgpr3 = S_MOV_B64 0
+ $vgpr2 = V_MOV_B32_e32 0, implicit $exec
+ $sgpr4_sgpr5 = IMPLICIT_DEF
S_BRANCH %bb.3
bb.2:
successors:
- %sgpr0_sgpr1 = SI_SPILL_S64_RESTORE %stack.0, implicit %exec, implicit %sgpr8_sgpr9_sgpr10_sgpr11, implicit %sgpr13, implicit-def dead %m0 :: (load 8 from %stack.0, align 4)
- %exec = S_OR_B64 %exec, killed %sgpr0_sgpr1, implicit-def %scc
+ $sgpr0_sgpr1 = SI_SPILL_S64_RESTORE %stack.0, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $sgpr13, implicit-def dead $m0 :: (load 8 from %stack.0, align 4)
+ $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
bb.3:
- liveins: %vgpr0, %vgpr1, %vgpr2, %sgpr2_sgpr3, %sgpr4_sgpr5
+ liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr2_sgpr3, $sgpr4_sgpr5
- %vcc = COPY %vgpr1
+ $vcc = COPY $vgpr1
S_ENDPGM
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir Wed Jan 31 14:04:26 2018
@@ -46,9 +46,9 @@
...
---
# CHECK-LABEL: name: vccz_corrupt_workaround
-# CHECK: %vcc = V_CMP_EQ_F32
-# CHECK-NEXT: %vcc = S_MOV_B64 %vcc
-# CHECK-NEXT: S_CBRANCH_VCCZ %bb.2, implicit killed %vcc
+# CHECK: $vcc = V_CMP_EQ_F32
+# CHECK-NEXT: $vcc = S_MOV_B64 $vcc
+# CHECK-NEXT: S_CBRANCH_VCCZ %bb.2, implicit killed $vcc
name: vccz_corrupt_workaround
alignment: 0
@@ -58,7 +58,7 @@ regBankSelected: false
selected: false
tracksRegLiveness: true
liveins:
- - { reg: '%sgpr0_sgpr1' }
+ - { reg: '$sgpr0_sgpr1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -75,43 +75,43 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %sgpr0_sgpr1
+ liveins: $sgpr0_sgpr1
- %sgpr2 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 9, 0 :: (non-temporal dereferenceable invariant load 4 from `float addrspace(2)* undef`)
- %sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
- %sgpr7 = S_MOV_B32 61440
- %sgpr6 = S_MOV_B32 -1
- %vcc = V_CMP_EQ_F32_e64 0, 0, 0, %sgpr2, 0, implicit %exec
- S_CBRANCH_VCCZ %bb.1, implicit killed %vcc
+ $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 9, 0 :: (non-temporal dereferenceable invariant load 4 from `float addrspace(2)* undef`)
+ $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
+ $sgpr7 = S_MOV_B32 61440
+ $sgpr6 = S_MOV_B32 -1
+ $vcc = V_CMP_EQ_F32_e64 0, 0, 0, $sgpr2, 0, implicit $exec
+ S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
bb.2.if:
- liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
+ liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
- %vgpr0 = V_MOV_B32_e32 9, implicit %exec
- BUFFER_STORE_DWORD_OFFSET killed %vgpr0, killed %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `i32 addrspace(1)* undef`)
- %vgpr0 = V_MOV_B32_e32 0, implicit %exec
+ $vgpr0 = V_MOV_B32_e32 9, implicit $exec
+ BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`)
+ $vgpr0 = V_MOV_B32_e32 0, implicit $exec
S_BRANCH %bb.3
bb.1.else:
- liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
+ liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
- %vgpr0 = V_MOV_B32_e32 100, implicit %exec
- BUFFER_STORE_DWORD_OFFSET killed %vgpr0, killed %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `i32 addrspace(1)* undef`)
- %vgpr0 = V_MOV_B32_e32 1, implicit %exec
+ $vgpr0 = V_MOV_B32_e32 100, implicit $exec
+ BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`)
+ $vgpr0 = V_MOV_B32_e32 1, implicit $exec
bb.3.done:
- liveins: %vgpr0, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
+ liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
- %sgpr3 = S_MOV_B32 61440
- %sgpr2 = S_MOV_B32 -1
- BUFFER_STORE_DWORD_OFFSET killed %vgpr0, killed %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec :: (store 4 into %ir.out)
+ $sgpr3 = S_MOV_B32 61440
+ $sgpr2 = S_MOV_B32 -1
+ BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.out)
S_ENDPGM
...
---
# CHECK-LABEL: name: vccz_corrupt_undef_vcc
# CHECK: S_WAITCNT
-# CHECK-NEXT: S_CBRANCH_VCCZ %bb.2, implicit undef %vcc
+# CHECK-NEXT: S_CBRANCH_VCCZ %bb.2, implicit undef $vcc
name: vccz_corrupt_undef_vcc
alignment: 0
@@ -121,7 +121,7 @@ regBankSelected: false
selected: false
tracksRegLiveness: true
liveins:
- - { reg: '%sgpr0_sgpr1' }
+ - { reg: '$sgpr0_sgpr1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -138,34 +138,34 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %sgpr0_sgpr1
+ liveins: $sgpr0_sgpr1
- %sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
- %sgpr7 = S_MOV_B32 61440
- %sgpr6 = S_MOV_B32 -1
- S_CBRANCH_VCCZ %bb.1, implicit undef %vcc
+ $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
+ $sgpr7 = S_MOV_B32 61440
+ $sgpr6 = S_MOV_B32 -1
+ S_CBRANCH_VCCZ %bb.1, implicit undef $vcc
bb.2.if:
- liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
+ liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
- %vgpr0 = V_MOV_B32_e32 9, implicit %exec
- BUFFER_STORE_DWORD_OFFSET killed %vgpr0, killed %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `i32 addrspace(1)* undef`)
- %vgpr0 = V_MOV_B32_e32 0, implicit %exec
+ $vgpr0 = V_MOV_B32_e32 9, implicit $exec
+ BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`)
+ $vgpr0 = V_MOV_B32_e32 0, implicit $exec
S_BRANCH %bb.3
bb.1.else:
- liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
+ liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
- %vgpr0 = V_MOV_B32_e32 100, implicit %exec
- BUFFER_STORE_DWORD_OFFSET killed %vgpr0, killed %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `i32 addrspace(1)* undef`)
- %vgpr0 = V_MOV_B32_e32 1, implicit %exec
+ $vgpr0 = V_MOV_B32_e32 100, implicit $exec
+ BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`)
+ $vgpr0 = V_MOV_B32_e32 1, implicit $exec
bb.3.done:
- liveins: %vgpr0, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
+ liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
- %sgpr3 = S_MOV_B32 61440
- %sgpr2 = S_MOV_B32 -1
- BUFFER_STORE_DWORD_OFFSET killed %vgpr0, killed %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec :: (store 4 into %ir.out)
+ $sgpr3 = S_MOV_B32 61440
+ $sgpr2 = S_MOV_B32 -1
+ BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.out)
S_ENDPGM
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir Wed Jan 31 14:04:26 2018
@@ -35,7 +35,7 @@
# GCN-LABEL: name: fold_fi_vgpr{{$}}
# GCN: %1:vgpr_32 = IMPLICIT_DEF
-# GCN: %2:vgpr_32 = V_ADD_I32_e32 %stack.0.alloca, %1, implicit-def %vcc, implicit %exec
+# GCN: %2:vgpr_32 = V_ADD_I32_e32 %stack.0.alloca, %1, implicit-def $vcc, implicit $exec
name: fold_fi_vgpr
tracksRegLiveness: true
registers:
@@ -48,15 +48,15 @@ stack:
di-location: '' }
body: |
bb.0:
- %0 = V_MOV_B32_e32 %stack.0.alloca, implicit %exec
+ %0 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
%1 = IMPLICIT_DEF
- %2, %vcc = V_ADD_I32_e64 %0, %1, implicit %exec
+ %2, $vcc = V_ADD_I32_e64 %0, %1, implicit $exec
S_ENDPGM
...
# GCN-LABEL: name: fold_vgpr_fi{{$}}
# GCN: %1:vgpr_32 = IMPLICIT_DEF
-# GCN: %2:vgpr_32 = V_ADD_I32_e32 %stack.0.alloca, %1, implicit-def %vcc, implicit %exec
+# GCN: %2:vgpr_32 = V_ADD_I32_e32 %stack.0.alloca, %1, implicit-def $vcc, implicit $exec
name: fold_vgpr_fi
tracksRegLiveness: true
registers:
@@ -69,16 +69,16 @@ stack:
di-location: '' }
body: |
bb.0:
- %0 = V_MOV_B32_e32 %stack.0.alloca, implicit %exec
+ %0 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
%1 = IMPLICIT_DEF
- %2, %vcc = V_ADD_I32_e64 %1, %0, implicit %exec
+ %2, $vcc = V_ADD_I32_e64 %1, %0, implicit $exec
S_ENDPGM
...
# GCN-LABEL: name: fold_sgpr_fi{{$}}
-# GCN: %0:vgpr_32 = V_MOV_B32_e32 %stack.0.alloca, implicit %exec
+# GCN: %0:vgpr_32 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
# GCN: %1:sgpr_32 = IMPLICIT_DEF
-# GCN: %2:vgpr_32 = V_ADD_I32_e32 %1, %0, implicit-def %vcc, implicit %exec
+# GCN: %2:vgpr_32 = V_ADD_I32_e32 %1, %0, implicit-def $vcc, implicit $exec
name: fold_sgpr_fi
tracksRegLiveness: true
registers:
@@ -91,16 +91,16 @@ stack:
di-location: '' }
body: |
bb.0:
- %0 = V_MOV_B32_e32 %stack.0.alloca, implicit %exec
+ %0 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
%1 = IMPLICIT_DEF
- %2, %vcc = V_ADD_I32_e64 %1, %0, implicit %exec
+ %2, $vcc = V_ADD_I32_e64 %1, %0, implicit $exec
S_ENDPGM
...
# GCN-LABEL: name: fold_fi_sgpr{{$}}
-# GCN: %0:vgpr_32 = V_MOV_B32_e32 %stack.0.alloca, implicit %exec
+# GCN: %0:vgpr_32 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
# GCN: %1:sgpr_32 = IMPLICIT_DEF
-# GCN: %2:vgpr_32 = V_ADD_I32_e32 %1, %0, implicit-def %vcc, implicit %exec
+# GCN: %2:vgpr_32 = V_ADD_I32_e32 %1, %0, implicit-def $vcc, implicit $exec
name: fold_fi_sgpr
tracksRegLiveness: true
registers:
@@ -113,15 +113,15 @@ stack:
di-location: '' }
body: |
bb.0:
- %0 = V_MOV_B32_e32 %stack.0.alloca, implicit %exec
+ %0 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
%1 = IMPLICIT_DEF
- %2, %vcc = V_ADD_I32_e64 %0, %1, implicit %exec
+ %2, $vcc = V_ADD_I32_e64 %0, %1, implicit $exec
S_ENDPGM
...
# TODO: Should probably prefer folding immediate first
# GCN-LABEL: name: fold_fi_imm{{$}}
-# GCN: %1:vgpr_32 = V_MOV_B32_e32 999, implicit %exec
-# GCN: %2:vgpr_32 = V_ADD_I32_e32 %stack.0.alloca, %1, implicit-def %vcc, implicit %exec
+# GCN: %1:vgpr_32 = V_MOV_B32_e32 999, implicit $exec
+# GCN: %2:vgpr_32 = V_ADD_I32_e32 %stack.0.alloca, %1, implicit-def $vcc, implicit $exec
name: fold_fi_imm
tracksRegLiveness: true
registers:
@@ -134,15 +134,15 @@ stack:
di-location: '' }
body: |
bb.0:
- %0 = V_MOV_B32_e32 %stack.0.alloca, implicit %exec
- %1 = V_MOV_B32_e32 999, implicit %exec
- %2, %vcc = V_ADD_I32_e64 %0, %1, implicit %exec
+ %0 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
+ %1 = V_MOV_B32_e32 999, implicit $exec
+ %2, $vcc = V_ADD_I32_e64 %0, %1, implicit $exec
S_ENDPGM
...
# GCN-LABEL: name: fold_imm_fi{{$}}
-# GCN: %0:vgpr_32 = V_MOV_B32_e32 %stack.0.alloca, implicit %exec
-# GCN: %2:vgpr_32 = V_ADD_I32_e32 999, %0, implicit-def %vcc, implicit %exec
+# GCN: %0:vgpr_32 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
+# GCN: %2:vgpr_32 = V_ADD_I32_e32 999, %0, implicit-def $vcc, implicit $exec
name: fold_imm_fi
tracksRegLiveness: true
registers:
@@ -155,7 +155,7 @@ stack:
di-location: '' }
body: |
bb.0:
- %0 = V_MOV_B32_e32 %stack.0.alloca, implicit %exec
- %1 = V_MOV_B32_e32 999, implicit %exec
- %2, %vcc = V_ADD_I32_e64 %1, %0, implicit %exec
+ %0 = V_MOV_B32_e32 %stack.0.alloca, implicit $exec
+ %1 = V_MOV_B32_e32 999, implicit $exec
+ %2, $vcc = V_ADD_I32_e64 %1, %0, implicit $exec
S_ENDPGM
Modified: llvm/trunk/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir Wed Jan 31 14:04:26 2018
@@ -1,8 +1,8 @@
# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
...
# GCN-LABEL: name: fold_imm_non_ssa{{$}}
-# GCN: %0:vgpr_32 = V_MOV_B32_e32 123, implicit %exec
-# GCN: %2:vgpr_32 = V_ADD_I32_e32 456, %0, implicit-def %vcc, implicit %exec
+# GCN: %0:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
+# GCN: %2:vgpr_32 = V_ADD_I32_e32 456, %0, implicit-def $vcc, implicit $exec
name: fold_imm_non_ssa
tracksRegLiveness: true
@@ -14,15 +14,15 @@ registers:
body: |
bb.0:
%0 = COPY undef %0
- %0 = V_MOV_B32_e32 123, implicit %exec
- %1 = V_MOV_B32_e32 456, implicit %exec
- %2, %vcc = V_ADD_I32_e64 %0, %1, implicit %exec
+ %0 = V_MOV_B32_e32 123, implicit $exec
+ %1 = V_MOV_B32_e32 456, implicit $exec
+ %2, $vcc = V_ADD_I32_e64 %0, %1, implicit $exec
S_ENDPGM
...
# GCN-LABEL: name: fold_partially_defined_superreg{{$}}
-# GCN: %1:vgpr_32 = V_MOV_B32_e32 456, implicit %exec
-# GCN: %2:vgpr_32 = V_ADD_I32_e32 123, %1, implicit-def %vcc, implicit %exec
+# GCN: %1:vgpr_32 = V_MOV_B32_e32 456, implicit $exec
+# GCN: %2:vgpr_32 = V_ADD_I32_e32 123, %1, implicit-def $vcc, implicit $exec
name: fold_partially_defined_superreg
tracksRegLiveness: true
registers:
@@ -32,9 +32,9 @@ registers:
- { id: 3, class: vreg_64 }
body: |
bb.0:
- undef %3.sub0 = V_MOV_B32_e32 123, implicit %exec, implicit-def %3
- %1 = V_MOV_B32_e32 456, implicit %exec
- %2, %vcc = V_ADD_I32_e64 %3.sub0, %1, implicit %exec
+ undef %3.sub0 = V_MOV_B32_e32 123, implicit $exec, implicit-def %3
+ %1 = V_MOV_B32_e32 456, implicit $exec
+ %2, $vcc = V_ADD_I32_e64 %3.sub0, %1, implicit $exec
S_ENDPGM
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/waitcnt-permute.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/waitcnt-permute.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/waitcnt-permute.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/waitcnt-permute.mir Wed Jan 31 14:04:26 2018
@@ -7,15 +7,15 @@
name: waitcnt-permute
liveins:
- - { reg: '%vgpr0' }
- - { reg: '%vgpr1' }
- - { reg: '%sgpr30_sgpr31' }
+ - { reg: '$vgpr0' }
+ - { reg: '$vgpr1' }
+ - { reg: '$sgpr30_sgpr31' }
body: |
bb.0:
- liveins: %vgpr0, %vgpr1, %sgpr30_sgpr31
+ liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
- %vgpr0 = DS_BPERMUTE_B32 killed %vgpr0, killed %vgpr1, 0, implicit %exec
- %vgpr0 = V_ADD_F32_e32 1065353216, killed %vgpr0, implicit %exec
- S_SETPC_B64_return killed %sgpr30_sgpr31, implicit killed %vgpr0
+ $vgpr0 = DS_BPERMUTE_B32 killed $vgpr0, killed $vgpr1, 0, implicit $exec
+ $vgpr0 = V_ADD_F32_e32 1065353216, killed $vgpr0, implicit $exec
+ S_SETPC_B64_return killed $sgpr30_sgpr31, implicit killed $vgpr0
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/waitcnt.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/waitcnt.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/waitcnt.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/waitcnt.mir Wed Jan 31 14:04:26 2018
@@ -51,22 +51,22 @@ name: flat_zero_waitcnt
body: |
bb.0:
successors: %bb.1
- %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.global4)
- %vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 %vgpr7_vgpr8, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 16 from %ir.global16)
- %vgpr0 = V_MOV_B32_e32 %vgpr1, implicit %exec
+ $vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.global4)
+ $vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 $vgpr7_vgpr8, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 16 from %ir.global16)
+ $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec
S_BRANCH %bb.1
bb.1:
successors: %bb.2
- %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, 0, implicit %exec, implicit %flat_scr
- %vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 %vgpr7_vgpr8, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 16 from %ir.global16)
- %vgpr0 = V_MOV_B32_e32 %vgpr1, implicit %exec
+ $vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr
+ $vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 $vgpr7_vgpr8, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 16 from %ir.global16)
+ $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec
S_BRANCH %bb.2
bb.2:
- %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.flat4)
- %vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 %vgpr7_vgpr8, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 16 from %ir.flat16)
- %vgpr0 = V_MOV_B32_e32 %vgpr1, implicit %exec
+ $vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.flat4)
+ $vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 $vgpr7_vgpr8, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 16 from %ir.flat16)
+ $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec
S_ENDPGM
...
---
@@ -74,7 +74,7 @@ body: |
# need to wait immediately.
# CHECK-LABEL: name: single_fallthrough_successor_no_end_block_wait
-# CHECK: %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2
+# CHECK: $vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2
# CHECK-NOT: S_WAITCNT
# CHECK: bb.1:
@@ -86,11 +86,11 @@ name: single_fallthrough_successor_no_en
body: |
bb.0:
successors: %bb.1
- %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, 0, implicit %exec, implicit %flat_scr
+ $vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr
bb.1:
- %vgpr3_vgpr4 = V_LSHLREV_B64 4, %vgpr7_vgpr8, implicit %exec
- FLAT_STORE_DWORD %vgpr3_vgpr4, %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr
+ $vgpr3_vgpr4 = V_LSHLREV_B64 4, $vgpr7_vgpr8, implicit $exec
+ FLAT_STORE_DWORD $vgpr3_vgpr4, $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM
...
---
@@ -99,7 +99,7 @@ body: |
# CHECK-LABEL: name: single_branch_successor_not_next_block
-# CHECK: %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2
+# CHECK: $vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2
# CHECK-NEXT: S_WAITCNT 112
# CHECK: bb.1
@@ -114,15 +114,15 @@ name: single_branch_successor_not_next_b
body: |
bb.0:
successors: %bb.2
- %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, 0, implicit %exec, implicit %flat_scr
+ $vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, implicit $exec, implicit $flat_scr
S_BRANCH %bb.2
bb.1:
- FLAT_STORE_DWORD %vgpr8_vgpr9, %vgpr10, 0, 0, 0, implicit %exec, implicit %flat_scr
+ FLAT_STORE_DWORD $vgpr8_vgpr9, $vgpr10, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM
bb.2:
- %vgpr3_vgpr4 = V_LSHLREV_B64 4, %vgpr7_vgpr8, implicit %exec
- FLAT_STORE_DWORD %vgpr3_vgpr4, %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr
+ $vgpr3_vgpr4 = V_LSHLREV_B64 4, $vgpr7_vgpr8, implicit $exec
+ FLAT_STORE_DWORD $vgpr3_vgpr4, $vgpr0, 0, 0, 0, implicit $exec, implicit $flat_scr
S_ENDPGM
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/wqm.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/wqm.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/wqm.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/wqm.mir Wed Jan 31 14:04:26 2018
@@ -28,23 +28,23 @@ registers:
- { id: 11, class: vgpr_32, preferred-register: '' }
- { id: 12, class: vgpr_32, preferred-register: '' }
liveins:
- - { reg: '%sgpr0', virtual-reg: '%0' }
- - { reg: '%sgpr1', virtual-reg: '%1' }
- - { reg: '%sgpr2', virtual-reg: '%2' }
- - { reg: '%vgpr0', virtual-reg: '%3' }
+ - { reg: '$sgpr0', virtual-reg: '%0' }
+ - { reg: '$sgpr1', virtual-reg: '%1' }
+ - { reg: '$sgpr2', virtual-reg: '%2' }
+ - { reg: '$vgpr0', virtual-reg: '%3' }
body: |
bb.0:
- liveins: %sgpr0, %sgpr1, %sgpr2, %vgpr0
+ liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0
- %3 = COPY %vgpr0
- %2 = COPY %sgpr2
- %1 = COPY %sgpr1
- %0 = COPY %sgpr0
- S_CMP_LT_I32 0, %0, implicit-def %scc
- %12 = V_ADD_I32_e32 %3, %3, implicit-def %vcc, implicit %exec
- %5 = S_CSELECT_B32 %2, %1, implicit %scc
- %11 = V_ADD_I32_e32 %5, %12, implicit-def %vcc, implicit %exec
- %vgpr0 = WWM %11, implicit %exec
- SI_RETURN_TO_EPILOG %vgpr0
+ %3 = COPY $vgpr0
+ %2 = COPY $sgpr2
+ %1 = COPY $sgpr1
+ %0 = COPY $sgpr0
+ S_CMP_LT_I32 0, %0, implicit-def $scc
+ %12 = V_ADD_I32_e32 %3, %3, implicit-def $vcc, implicit $exec
+ %5 = S_CSELECT_B32 %2, %1, implicit $scc
+ %11 = V_ADD_I32_e32 %5, %12, implicit-def $vcc, implicit $exec
+ $vgpr0 = WWM %11, implicit $exec
+ SI_RETURN_TO_EPILOG $vgpr0
...
Modified: llvm/trunk/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll Wed Jan 31 14:04:26 2018
@@ -4,7 +4,7 @@
define void @vst(i8* %m, [4 x i64] %v) {
entry:
; CHECK: vst:
-; CHECK: VST1d64Q killed %r{{[0-9]+}}, 8, %d{{[0-9]+}}, 14, %noreg, implicit killed %q{{[0-9]+}}_q{{[0-9]+}}
+; CHECK: VST1d64Q killed $r{{[0-9]+}}, 8, $d{{[0-9]+}}, 14, $noreg, implicit killed $q{{[0-9]+}}_q{{[0-9]+}}
%v0 = extractvalue [4 x i64] %v, 0
%v1 = extractvalue [4 x i64] %v, 1
@@ -37,7 +37,7 @@ entry:
%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind {
; CHECK: vtbx4:
-; CHECK: VTBX4 {{.*}}, 14, %noreg, implicit %q{{[0-9]+}}_q{{[0-9]+}}
+; CHECK: VTBX4 {{.*}}, 14, $noreg, implicit $q{{[0-9]+}}_q{{[0-9]+}}
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load %struct.__neon_int8x8x4_t, %struct.__neon_int8x8x4_t* %B
%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
Modified: llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir Wed Jan 31 14:04:26 2018
@@ -81,24 +81,24 @@ alignment: 1
exposesReturnsTwice: false
tracksRegLiveness: true
liveins:
- - { reg: '%r0' }
- - { reg: '%r1' }
- - { reg: '%r2' }
- - { reg: '%r3' }
-calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13',
- '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4',
- '%r5', '%r6', '%r7', '%r8', '%r9', '%r10', '%r11',
- '%s16', '%s17', '%s18', '%s19', '%s20', '%s21',
- '%s22', '%s23', '%s24', '%s25', '%s26', '%s27',
- '%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11',
- '%d10_d12', '%d11_d13', '%d12_d14', '%d13_d15',
- '%q4_q5', '%q5_q6', '%q6_q7', '%q4_q5_q6_q7', '%r4_r5',
- '%r6_r7', '%r8_r9', '%r10_r11', '%d8_d9_d10', '%d9_d10_d11',
- '%d10_d11_d12', '%d11_d12_d13', '%d12_d13_d14',
- '%d13_d14_d15', '%d8_d10_d12', '%d9_d11_d13', '%d10_d12_d14',
- '%d11_d13_d15', '%d8_d10_d12_d14', '%d9_d11_d13_d15',
- '%d9_d10', '%d11_d12', '%d13_d14', '%d9_d10_d11_d12',
- '%d11_d12_d13_d14' ]
+ - { reg: '$r0' }
+ - { reg: '$r1' }
+ - { reg: '$r2' }
+ - { reg: '$r3' }
+calleeSavedRegisters: [ '$lr', '$d8', '$d9', '$d10', '$d11', '$d12', '$d13',
+ '$d14', '$d15', '$q4', '$q5', '$q6', '$q7', '$r4',
+ '$r5', '$r6', '$r7', '$r8', '$r9', '$r10', '$r11',
+ '$s16', '$s17', '$s18', '$s19', '$s20', '$s21',
+ '$s22', '$s23', '$s24', '$s25', '$s26', '$s27',
+ '$s28', '$s29', '$s30', '$s31', '$d8_d10', '$d9_d11',
+ '$d10_d12', '$d11_d13', '$d12_d14', '$d13_d15',
+ '$q4_q5', '$q5_q6', '$q6_q7', '$q4_q5_q6_q7', '$r4_r5',
+ '$r6_r7', '$r8_r9', '$r10_r11', '$d8_d9_d10', '$d9_d10_d11',
+ '$d10_d11_d12', '$d11_d12_d13', '$d12_d13_d14',
+ '$d13_d14_d15', '$d8_d10_d12', '$d9_d11_d13', '$d10_d12_d14',
+ '$d11_d13_d15', '$d8_d10_d12_d14', '$d9_d11_d13_d15',
+ '$d9_d10', '$d11_d12', '$d13_d14', '$d9_d10_d11_d12',
+ '$d11_d12_d13_d14' ]
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -114,46 +114,46 @@ frameInfo:
hasVAStart: false
hasMustTailInVarArgFunc: false
stack:
- - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr', callee-saved-restored: false }
- - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7', callee-saved-restored: true }
+ - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '$lr', callee-saved-restored: false }
+ - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '$r7', callee-saved-restored: true }
body: |
bb.0.entry:
- liveins: %r0, %r1, %r2, %r3, %lr, %r7
+ liveins: $r0, $r1, $r2, $r3, $lr, $r7
- DBG_VALUE debug-use %r0, debug-use %noreg, !18, !27, debug-location !28
- DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
- DBG_VALUE debug-use %r2, debug-use %noreg, !20, !27, debug-location !28
- DBG_VALUE debug-use %r3, debug-use %noreg, !21, !27, debug-location !28
- t2CMPri %r3, 4, 14, %noreg, implicit-def %cpsr, debug-location !31
- t2Bcc %bb.2.if.end, 2, killed %cpsr
+ DBG_VALUE debug-use $r0, debug-use $noreg, !18, !27, debug-location !28
+ DBG_VALUE debug-use $r1, debug-use $noreg, !19, !27, debug-location !28
+ DBG_VALUE debug-use $r2, debug-use $noreg, !20, !27, debug-location !28
+ DBG_VALUE debug-use $r3, debug-use $noreg, !21, !27, debug-location !28
+ t2CMPri $r3, 4, 14, $noreg, implicit-def $cpsr, debug-location !31
+ t2Bcc %bb.2.if.end, 2, killed $cpsr
bb.1:
- liveins: %lr, %r7
+ liveins: $lr, $r7
- DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
- %r0 = t2MOVi -1, 14, %noreg, %noreg
- DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
- tBX_RET 14, %noreg, implicit %r0, debug-location !34
+ DBG_VALUE debug-use $r1, debug-use $noreg, !19, !27, debug-location !28
+ $r0 = t2MOVi -1, 14, $noreg, $noreg
+ DBG_VALUE debug-use $r1, debug-use $noreg, !19, !27, debug-location !28
+ tBX_RET 14, $noreg, implicit $r0, debug-location !34
bb.2.if.end:
- liveins: %r0, %r2, %r3, %r7, %lr
+ liveins: $r0, $r2, $r3, $r7, $lr
- %sp = frame-setup t2STMDB_UPD %sp, 14, %noreg, killed %r7, killed %lr
+ $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr
frame-setup CFI_INSTRUCTION def_cfa_offset 8
- frame-setup CFI_INSTRUCTION offset %lr, -4
- frame-setup CFI_INSTRUCTION offset %r7, -8
- DBG_VALUE debug-use %r0, debug-use %noreg, !18, !27, debug-location !28
- DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
- DBG_VALUE debug-use %r2, debug-use %noreg, !20, !27, debug-location !28
- DBG_VALUE debug-use %r3, debug-use %noreg, !21, !27, debug-location !28
- %r1 = COPY killed %r2, debug-location !32
- DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
- %r2 = COPY killed %r3, debug-location !32
- tBL 14, %noreg, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32
- %r0 = t2MOVi 0, 14, %noreg, %noreg
- %sp = t2LDMIA_UPD %sp, 14, %noreg, def %r7, def %lr
- tBX_RET 14, %noreg, implicit %r0, debug-location !34
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r7, -8
+ DBG_VALUE debug-use $r0, debug-use $noreg, !18, !27, debug-location !28
+ DBG_VALUE debug-use $r1, debug-use $noreg, !19, !27, debug-location !28
+ DBG_VALUE debug-use $r2, debug-use $noreg, !20, !27, debug-location !28
+ DBG_VALUE debug-use $r3, debug-use $noreg, !21, !27, debug-location !28
+ $r1 = COPY killed $r2, debug-location !32
+ DBG_VALUE debug-use $r1, debug-use $noreg, !19, !27, debug-location !28
+ $r2 = COPY killed $r3, debug-location !32
+ tBL 14, $noreg, @g, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp, debug-location !32
+ $r0 = t2MOVi 0, 14, $noreg, $noreg
+ $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr
+ tBX_RET 14, $noreg, implicit $r0, debug-location !34
# Verify that the DBG_VALUE is ignored.
-# CHECK: %sp = t2LDMIA_RET %sp, 14, %noreg, def %r7, def %pc, implicit %r0
+# CHECK: $sp = t2LDMIA_RET $sp, 14, $noreg, def $r7, def $pc, implicit $r0
...
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll Wed Jan 31 14:04:26 2018
@@ -4,14 +4,14 @@
define arm_aapcscc void @test_indirect_call(void() *%fptr) {
; CHECK-LABEL: name: test_indirect_call
-; V5T: %[[FPTR:[0-9]+]]:gpr(p0) = COPY %r0
-; V4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY %r0
-; NOV4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY %r0
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; V5T: BLX %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
-; V4T: BX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
-; NOV4T: BMOVPCRX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
-; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; V5T: %[[FPTR:[0-9]+]]:gpr(p0) = COPY $r0
+; V4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY $r0
+; NOV4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY $r0
+; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; V5T: BLX %[[FPTR]](p0), csr_aapcs, implicit-def $lr, implicit $sp
+; V4T: BX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def $lr, implicit $sp
+; NOV4T: BMOVPCRX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def $lr, implicit $sp
+; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
entry:
notail call arm_aapcscc void %fptr()
ret void
@@ -21,9 +21,9 @@ declare arm_aapcscc void @call_target()
define arm_aapcscc void @test_direct_call() {
; CHECK-LABEL: name: test_direct_call
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: BL @call_target, csr_aapcs, implicit-def %lr, implicit %sp
-; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK: BL @call_target, csr_aapcs, implicit-def $lr, implicit $sp
+; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
entry:
notail call arm_aapcscc void @call_target()
ret void
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir Wed Jan 31 14:04:26 2018
@@ -64,23 +64,23 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_eq_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(eq), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_ne_s32
@@ -94,23 +94,23 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_ne_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(ne), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_ugt_s32
@@ -124,23 +124,23 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_ugt_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(ugt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_uge_s32
@@ -154,23 +154,23 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_uge_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 2, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 2, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(uge), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_ult_s32
@@ -184,23 +184,23 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_ult_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 3, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 3, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(ult), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_ule_s32
@@ -214,23 +214,23 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_ule_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(ule), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_sgt_s32
@@ -244,23 +244,23 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_sgt_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(sgt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_sge_s32
@@ -274,23 +274,23 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_sge_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(sge), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_slt_s32
@@ -304,23 +304,23 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_slt_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(slt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_sle_s32
@@ -334,23 +334,23 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; CHECK-LABEL: name: test_icmp_sle_s32
- ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(sle), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_true_s32
@@ -364,19 +364,19 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_true_s32
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, %noreg, %noreg
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, $noreg, $noreg
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(true), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_false_s32
@@ -390,19 +390,19 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_false_s32
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(false), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_oeq_s32
@@ -416,24 +416,24 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_oeq_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(oeq), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ogt_s32
@@ -447,24 +447,24 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_ogt_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(ogt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_oge_s32
@@ -478,24 +478,24 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_oge_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(oge), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_olt_s32
@@ -509,24 +509,24 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_olt_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(olt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ole_s32
@@ -540,24 +540,24 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_ole_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(ole), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ord_s32
@@ -571,24 +571,24 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_ord_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(ord), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ugt_s32
@@ -602,24 +602,24 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_ugt_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(ugt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_uge_s32
@@ -633,24 +633,24 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_uge_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(uge), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ult_s32
@@ -664,24 +664,24 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_ult_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(ult), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ule_s32
@@ -695,24 +695,24 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_ule_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(ule), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_une_s32
@@ -726,24 +726,24 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_une_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(une), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_uno_s32
@@ -757,24 +757,24 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_uno_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(uno), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_one_s32
@@ -788,27 +788,27 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_one_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, $cpsr
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(one), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ueq_s32
@@ -822,27 +822,27 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
; CHECK-LABEL: name: test_fcmp_ueq_s32
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
- ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, $cpsr
+ ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(ueq), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_true_s64
@@ -856,19 +856,19 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_true_s64
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, %noreg, %noreg
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, $noreg, $noreg
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(true), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_false_s64
@@ -882,19 +882,19 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_false_s64
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(false), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_oeq_s64
@@ -908,24 +908,24 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_oeq_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(oeq), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ogt_s64
@@ -939,24 +939,24 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_ogt_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(ogt), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_oge_s64
@@ -970,24 +970,24 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_oge_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(oge), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_olt_s64
@@ -1001,24 +1001,24 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_olt_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(olt), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ole_s64
@@ -1032,24 +1032,24 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_ole_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(ole), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ord_s64
@@ -1063,24 +1063,24 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_ord_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(ord), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ugt_s64
@@ -1094,24 +1094,24 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_ugt_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(ugt), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_uge_s64
@@ -1125,24 +1125,24 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_uge_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(uge), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ult_s64
@@ -1156,24 +1156,24 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_ult_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(ult), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ule_s64
@@ -1187,24 +1187,24 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_ule_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(ule), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_une_s64
@@ -1218,24 +1218,24 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_une_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(une), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_uno_s64
@@ -1249,24 +1249,24 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_uno_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(uno), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_one_s64
@@ -1280,27 +1280,27 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_one_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, $cpsr
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(one), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ueq_s64
@@ -1314,25 +1314,25 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
; CHECK-LABEL: name: test_fcmp_ueq_s64
- ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
- ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
- ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
- ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
- ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6, %cpsr
- ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, %noreg, %noreg
- ; CHECK: %r0 = COPY [[ANDri]]
- ; CHECK: BX_RET 14, %noreg, implicit %r0
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, $cpsr
+ ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv
+ ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
+ ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6, $cpsr
+ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, $noreg, $noreg
+ ; CHECK: $r0 = COPY [[ANDri]]
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(ueq), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir Wed Jan 31 14:04:26 2018
@@ -63,24 +63,24 @@ registers:
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
- ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
- ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY %r2
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
+ ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY $r2
%3(s32) = G_MUL %0, %1
%4(s32) = G_ADD %3, %2
- ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg, $noreg
- %r0 = COPY %4(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %4(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_mla_commutative
@@ -97,24 +97,24 @@ registers:
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
- ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
- ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY %r2
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
+ ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY $r2
%3(s32) = G_MUL %0, %1
%4(s32) = G_ADD %2, %3
- ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg, $noreg
- %r0 = COPY %4(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %4(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_mla_v5
@@ -131,24 +131,24 @@ registers:
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
- ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
- ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY %r2
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
+ ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY $r2
%3(s32) = G_MUL %0, %1
%4(s32) = G_ADD %3, %2
- ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLAv5 [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLAv5 [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg, $noreg
- %r0 = COPY %4(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %4(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_mls
@@ -165,24 +165,24 @@ registers:
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
- ; CHECK: [[VREGZ:%[0-9]+]]:gpr = COPY %r2
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK: [[VREGZ:%[0-9]+]]:gpr = COPY $r2
%3(s32) = G_MUL %0, %1
%4(s32) = G_SUB %2, %3
- ; CHECK: [[VREGR:%[0-9]+]]:gpr = MLS [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gpr = MLS [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg
- %r0 = COPY %4(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %4(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_no_mls
@@ -199,25 +199,25 @@ registers:
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
- ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
- ; CHECK: [[VREGZ:%[0-9]+]]:gpr = COPY %r2
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
+ ; CHECK: [[VREGZ:%[0-9]+]]:gpr = COPY $r2
%3(s32) = G_MUL %0, %1
%4(s32) = G_SUB %2, %3
- ; CHECK: [[VREGM:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, %noreg, %noreg
- ; CHECK: [[VREGR:%[0-9]+]]:gpr = SUBrr [[VREGZ]], [[VREGM]], 14, %noreg, %noreg
+ ; CHECK: [[VREGM:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, $noreg, $noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gpr = SUBrr [[VREGZ]], [[VREGM]], 14, $noreg, $noreg
- %r0 = COPY %4(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %4(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_shifts_to_revsh
@@ -239,10 +239,10 @@ registers:
- { id: 9, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 24
%2(s32) = G_SHL %0(s32), %1(s32)
@@ -259,11 +259,11 @@ body: |
%9(s32) = G_OR %4(s32), %8(s32)
; CHECK: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]]
- %r0 = COPY %9(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %9(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_shifts_to_revsh_commutative
@@ -285,10 +285,10 @@ registers:
- { id: 9, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 24
%2(s32) = G_SHL %0(s32), %1(s32)
@@ -305,11 +305,11 @@ body: |
%9(s32) = G_OR %8(s32), %4(s32)
; CHECK: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]]
- %r0 = COPY %9(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %9(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_shifts_no_revsh_features
@@ -331,9 +331,9 @@ registers:
- { id: 9, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s32) = G_CONSTANT i32 24
%2(s32) = G_SHL %0(s32), %1(s32)
@@ -351,9 +351,9 @@ body: |
; We don't really care how this is folded as long as it's not into a REVSH.
; CHECK-NOT: REVSH
- %r0 = COPY %9(s32)
+ $r0 = COPY %9(s32)
- BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_shifts_no_revsh_constants
@@ -375,9 +375,9 @@ registers:
- { id: 9, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s32) = G_CONSTANT i32 16 ; REVSH needs 24 here
%2(s32) = G_SHL %0(s32), %1(s32)
@@ -395,9 +395,9 @@ body: |
; We don't really care how this is folded as long as it's not into a REVSH.
; CHECK-NOT: REVSH
- %r0 = COPY %9(s32)
+ $r0 = COPY %9(s32)
- BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_bicrr
@@ -414,23 +414,23 @@ registers:
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %1, %2
%4(s32) = G_AND %0, %3
- ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
- %r0 = COPY %4(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %4(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_bicrr_commutative
@@ -447,23 +447,23 @@ registers:
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %1, %2
%4(s32) = G_AND %3, %0
- ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
- %r0 = COPY %4(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %4(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_bicri
@@ -480,10 +480,10 @@ registers:
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
; This test and the following ones are a bit contrived, since they use a
; G_XOR that can be constant-folded. They exist mostly to validate the
@@ -495,13 +495,13 @@ body: |
%2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %1, %2
%4(s32) = G_AND %0, %3
- ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, $noreg, $noreg
- %r0 = COPY %4(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %4(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_bicri_commutative_xor
@@ -518,23 +518,23 @@ registers:
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 192
%2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %2, %1
%4(s32) = G_AND %0, %3
- ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, $noreg, $noreg
- %r0 = COPY %4(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %4(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_bicri_commutative_and
@@ -551,23 +551,23 @@ registers:
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 192
%2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %1, %2
%4(s32) = G_AND %3, %0
- ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, $noreg, $noreg
- %r0 = COPY %4(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %4(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_bicri_commutative_both
@@ -584,23 +584,23 @@ registers:
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 192
%2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %2, %1
%4(s32) = G_AND %3, %0
- ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, $noreg, $noreg
- %r0 = COPY %4(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %4(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_pkhbt
@@ -621,12 +621,12 @@ registers:
- { id: 8, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
%2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
%3(s32) = G_AND %0, %2
@@ -637,13 +637,13 @@ body: |
%7(s32) = G_AND %5, %6
%8(s32) = G_OR %3, %7
- ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14, $noreg
- %r0 = COPY %8(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %8(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_pkhbt_commutative
@@ -664,12 +664,12 @@ registers:
- { id: 8, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
%2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
%3(s32) = G_AND %0, %2
@@ -680,13 +680,13 @@ body: |
%7(s32) = G_AND %5, %6
%8(s32) = G_OR %7, %3
- ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14, $noreg
- %r0 = COPY %8(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %8(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_pkhbt_imm16_31
@@ -705,12 +705,12 @@ registers:
- { id: 6, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
%2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
%3(s32) = G_AND %0, %2
@@ -719,13 +719,13 @@ body: |
%5(s32) = G_SHL %1, %4
%6(s32) = G_OR %3, %5
- ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 17, 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 17, 14, $noreg
- %r0 = COPY %6(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %6(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_pkhbt_unshifted
@@ -744,12 +744,12 @@ registers:
- { id: 6, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
%2(s32) = G_CONSTANT i32 65535 ; 0xFFFF
%3(s32) = G_AND %0, %2
@@ -758,13 +758,13 @@ body: |
%5(s32) = G_AND %1, %4
%6(s32) = G_OR %3, %5
- ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 0, 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 0, 14, $noreg
- %r0 = COPY %6(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %6(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_pkhtb_imm16
@@ -783,12 +783,12 @@ registers:
- { id: 6, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
%2(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
%3(s32) = G_AND %0, %2
@@ -797,13 +797,13 @@ body: |
%5(s32) = G_LSHR %1, %4
%6(s32) = G_OR %3, %5
- ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 16, 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 16, 14, $noreg
- %r0 = COPY %6(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %6(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_pkhtb_imm1_15
@@ -824,12 +824,12 @@ registers:
- { id: 8, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
%2(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
%3(s32) = G_AND %0, %2
@@ -840,13 +840,13 @@ body: |
%7(s32) = G_AND %5, %6
%8(s32) = G_OR %3, %7
- ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 7, 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 7, 14, $noreg
- %r0 = COPY %8(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %8(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_movti16_0xffff
@@ -861,21 +861,21 @@ registers:
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000
%2(s32) = G_OR %0, %1
- ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MOVTi16 [[VREGX]], 65535, 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MOVTi16 [[VREGX]], 65535, 14, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_vnmuls
@@ -891,22 +891,22 @@ registers:
- { id: 3, class: fprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY %s0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY %s1
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FMUL %0, %1
%3(s32) = G_FNEG %2
- ; CHECK: [[VREGR:%[0-9]+]]:spr = VNMULS [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:spr = VNMULS [[VREGX]], [[VREGY]], 14, $noreg
- %s0 = COPY %3(s32)
- ; CHECK: %s0 = COPY [[VREGR]]
+ $s0 = COPY %3(s32)
+ ; CHECK: $s0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_vnmuls_reassociate
@@ -922,22 +922,22 @@ registers:
- { id: 3, class: fprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY %s0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY %s1
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FNEG %0
%3(s32) = G_FMUL %1, %2
- ; CHECK: [[VREGR:%[0-9]+]]:spr = VNMULS [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:spr = VNMULS [[VREGX]], [[VREGY]], 14, $noreg
- %s0 = COPY %3(s32)
- ; CHECK: %s0 = COPY [[VREGR]]
+ $s0 = COPY %3(s32)
+ ; CHECK: $s0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_vnmuld
@@ -953,22 +953,22 @@ registers:
- { id: 3, class: fprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:dpr = COPY %d0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:dpr = COPY %d1
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_FMUL %0, %1
%3(s64) = G_FNEG %2
- ; CHECK: [[VREGR:%[0-9]+]]:dpr = VNMULD [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:dpr = VNMULD [[VREGX]], [[VREGY]], 14, $noreg
- %d0 = COPY %3(s64)
- ; CHECK: %d0 = COPY [[VREGR]]
+ $d0 = COPY %3(s64)
+ ; CHECK: $d0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_vfnmas
@@ -985,24 +985,24 @@ registers:
- { id: 4, class: fprb }
body: |
bb.0:
- liveins: %s0, %s1, %s2
+ liveins: $s0, $s1, $s2
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
- %2(s32) = COPY %s2
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY %s0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY %s1
- ; CHECK-DAG: [[VREGZ:%[0-9]+]]:spr = COPY %s2
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
+ %2(s32) = COPY $s2
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1
+ ; CHECK-DAG: [[VREGZ:%[0-9]+]]:spr = COPY $s2
%3(s32) = G_FMA %0, %1, %2
%4(s32) = G_FNEG %3
- ; CHECK: [[VREGR:%[0-9]+]]:spr = VFNMAS [[VREGZ]], [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:spr = VFNMAS [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
- %s0 = COPY %4(s32)
- ; CHECK: %s0 = COPY [[VREGR]]
+ $s0 = COPY %4(s32)
+ ; CHECK: $s0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_vfnmad
@@ -1020,25 +1020,25 @@ registers:
- { id: 5, class: fprb }
body: |
bb.0:
- liveins: %d0, %d1, %d2
+ liveins: $d0, $d1, $d2
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
- %2(s64) = COPY %d2
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:dpr = COPY %d0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:dpr = COPY %d1
- ; CHECK-DAG: [[VREGZ:%[0-9]+]]:dpr = COPY %d2
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
+ %2(s64) = COPY $d2
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK-DAG: [[VREGZ:%[0-9]+]]:dpr = COPY $d2
%3(s64) = G_FNEG %0
%4(s64) = G_FNEG %2
%5(s64) = G_FMA %3, %1, %4
- ; CHECK: [[VREGR:%[0-9]+]]:dpr = VFNMAD [[VREGZ]], [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:dpr = VFNMAD [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
- %d0 = COPY %5(s64)
- ; CHECK: %d0 = COPY [[VREGR]]
+ $d0 = COPY %5(s64)
+ ; CHECK: $d0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_vfmss
@@ -1055,24 +1055,24 @@ registers:
- { id: 4, class: fprb }
body: |
bb.0:
- liveins: %s0, %s1, %s2
+ liveins: $s0, $s1, $s2
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
- %2(s32) = COPY %s2
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY %s0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY %s1
- ; CHECK-DAG: [[VREGZ:%[0-9]+]]:spr = COPY %s2
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
+ %2(s32) = COPY $s2
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1
+ ; CHECK-DAG: [[VREGZ:%[0-9]+]]:spr = COPY $s2
%3(s32) = G_FNEG %0
%4(s32) = G_FMA %3, %1, %2
- ; CHECK: [[VREGR:%[0-9]+]]:spr = VFMSS [[VREGZ]], [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:spr = VFMSS [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
- %s0 = COPY %4(s32)
- ; CHECK: %s0 = COPY [[VREGR]]
+ $s0 = COPY %4(s32)
+ ; CHECK: $s0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_vfmsd
@@ -1089,24 +1089,24 @@ registers:
- { id: 4, class: fprb }
body: |
bb.0:
- liveins: %d0, %d1, %d2
+ liveins: $d0, $d1, $d2
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
- %2(s64) = COPY %d2
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:dpr = COPY %d0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:dpr = COPY %d1
- ; CHECK-DAG: [[VREGZ:%[0-9]+]]:dpr = COPY %d2
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
+ %2(s64) = COPY $d2
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:dpr = COPY $d1
+ ; CHECK-DAG: [[VREGZ:%[0-9]+]]:dpr = COPY $d2
%3(s64) = G_FNEG %1
%4(s64) = G_FMA %0, %3, %2
- ; CHECK: [[VREGR:%[0-9]+]]:dpr = VFMSD [[VREGZ]], [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:dpr = VFMSD [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
- %d0 = COPY %4(s64)
- ; CHECK: %d0 = COPY [[VREGR]]
+ $d0 = COPY %4(s64)
+ ; CHECK: $d0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_vfnmss
@@ -1123,22 +1123,22 @@ registers:
- { id: 4, class: fprb }
body: |
bb.0:
- liveins: %s0, %s1, %s2
+ liveins: $s0, $s1, $s2
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
- %2(s32) = COPY %s2
- ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY %s0
- ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY %s1
- ; CHECK-DAG: [[VREGZ:%[0-9]+]]:spr = COPY %s2
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
+ %2(s32) = COPY $s2
+ ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0
+ ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1
+ ; CHECK-DAG: [[VREGZ:%[0-9]+]]:spr = COPY $s2
%3(s32) = G_FNEG %2
%4(s32) = G_FMA %0, %1, %3
- ; CHECK: [[VREGR:%[0-9]+]]:spr = VFNMSS [[VREGZ]], [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:spr = VFNMSS [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
- %s0 = COPY %4(s32)
- ; CHECK: %s0 = COPY [[VREGR]]
+ $s0 = COPY %4(s32)
+ ; CHECK: $s0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir Wed Jan 31 14:04:26 2018
@@ -101,21 +101,21 @@ registers:
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s1) = G_TRUNC %0(s32)
%2(s32) = G_ZEXT %1(s1)
- ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, %noreg, %noreg
+ ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGEXT]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGEXT]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_trunc_and_sext_s1
@@ -130,22 +130,22 @@ registers:
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s1) = G_TRUNC %0(s32)
%2(s32) = G_SEXT %1(s1)
- ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, %noreg, %noreg
- ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = RSBri [[VREGAND]], 0, 14, %noreg, %noreg
+ ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, $noreg, $noreg
+ ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = RSBri [[VREGAND]], 0, 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGEXT]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGEXT]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_trunc_and_sext_s8
@@ -160,22 +160,22 @@ registers:
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s8) = G_TRUNC %0(s32)
; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]]
%2(s32) = G_SEXT %1(s8)
- ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = SXTB [[VREGTRUNC]], 0, 14, %noreg
+ ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = SXTB [[VREGTRUNC]], 0, 14, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGEXT]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGEXT]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_trunc_and_zext_s16
@@ -190,22 +190,22 @@ registers:
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s16) = G_TRUNC %0(s32)
; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]]
%2(s32) = G_ZEXT %1(s16)
- ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = UXTH [[VREGTRUNC]], 0, 14, %noreg
+ ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = UXTH [[VREGTRUNC]], 0, 14, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGEXT]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGEXT]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_trunc_and_anyext_s8
@@ -220,20 +220,20 @@ registers:
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s8) = G_TRUNC %0(s32)
%2(s32) = G_ANYEXT %1(s8)
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREG]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREG]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_trunc_and_anyext_s16
@@ -248,20 +248,20 @@ registers:
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
%1(s16) = G_TRUNC %0(s32)
%2(s32) = G_ANYEXT %1(s16)
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREG]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREG]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_trunc_s64
@@ -276,22 +276,22 @@ registers:
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %d0
+ liveins: $r0, $d0
- %0(s64) = COPY %d0
- ; CHECK: [[VREG:%[0-9]+]]:dpr = COPY %d0
+ %0(s64) = COPY $d0
+ ; CHECK: [[VREG:%[0-9]+]]:dpr = COPY $d0
- %2(p0) = COPY %r0
- ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY %r0
+ %2(p0) = COPY $r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_TRUNC %0(s64)
; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr, [[UNINTERESTING:%[0-9]+]]:gpr = VMOVRRD [[VREG]]
G_STORE %1(s32), %2 :: (store 4)
- ; CHECK: STRi12 [[VREGTRUNC]], [[PTR]], 0, 14, %noreg
+ ; CHECK: STRi12 [[VREGTRUNC]], [[PTR]], 0, 14, $noreg
- BX_RET 14, %noreg
- ; CHECK: BX_RET 14, %noreg
+ BX_RET 14, $noreg
+ ; CHECK: BX_RET 14, $noreg
...
---
name: test_add_s32
@@ -306,22 +306,22 @@ registers:
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
- %1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_ADD %0, %1
- ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGSUM]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_add_fold_imm_s32
@@ -336,20 +336,20 @@ registers:
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 255
%2(s32) = G_ADD %0, %1
- ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDri [[VREGX]], 255, 14, %noreg, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDri [[VREGX]], 255, 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGSUM]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_add_no_fold_imm_s32
@@ -364,22 +364,22 @@ registers:
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 65535
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = MOVi16 65535, 14, %noreg
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = MOVi16 65535, 14, $noreg
%2(s32) = G_ADD %0, %1
- ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGSUM]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_fadd_s32
@@ -394,22 +394,22 @@ registers:
- { id: 2, class: fprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
- %0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
+ %0(s32) = COPY $s0
+ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
- %1(s32) = COPY %s1
- ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
+ %1(s32) = COPY $s1
+ ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FADD %0, %1
- ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VADDS [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VADDS [[VREGX]], [[VREGY]], 14, $noreg
- %s0 = COPY %2(s32)
- ; CHECK: %s0 = COPY [[VREGSUM]]
+ $s0 = COPY %2(s32)
+ ; CHECK: $s0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fadd_s64
@@ -424,22 +424,22 @@ registers:
- { id: 2, class: fprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
- %0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
+ %0(s64) = COPY $d0
+ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
- %1(s64) = COPY %d1
- ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
+ %1(s64) = COPY $d1
+ ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_FADD %0, %1
- ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDD [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDD [[VREGX]], [[VREGY]], 14, $noreg
- %d0 = COPY %2(s64)
- ; CHECK: %d0 = COPY [[VREGSUM]]
+ $d0 = COPY %2(s64)
+ ; CHECK: $d0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fsub_s32
@@ -454,22 +454,22 @@ registers:
- { id: 2, class: fprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
- %0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
+ %0(s32) = COPY $s0
+ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
- %1(s32) = COPY %s1
- ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
+ %1(s32) = COPY $s1
+ ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FSUB %0, %1
- ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VSUBS [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VSUBS [[VREGX]], [[VREGY]], 14, $noreg
- %s0 = COPY %2(s32)
- ; CHECK: %s0 = COPY [[VREGSUM]]
+ $s0 = COPY %2(s32)
+ ; CHECK: $s0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fsub_s64
@@ -484,22 +484,22 @@ registers:
- { id: 2, class: fprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
- %0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
+ %0(s64) = COPY $d0
+ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
- %1(s64) = COPY %d1
- ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
+ %1(s64) = COPY $d1
+ ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_FSUB %0, %1
- ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBD [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBD [[VREGX]], [[VREGY]], 14, $noreg
- %d0 = COPY %2(s64)
- ; CHECK: %d0 = COPY [[VREGSUM]]
+ $d0 = COPY %2(s64)
+ ; CHECK: $d0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fmul_s32
@@ -514,22 +514,22 @@ registers:
- { id: 2, class: fprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
- %0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
+ %0(s32) = COPY $s0
+ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
- %1(s32) = COPY %s1
- ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
+ %1(s32) = COPY $s1
+ ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FMUL %0, %1
- ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VMULS [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VMULS [[VREGX]], [[VREGY]], 14, $noreg
- %s0 = COPY %2(s32)
- ; CHECK: %s0 = COPY [[VREGSUM]]
+ $s0 = COPY %2(s32)
+ ; CHECK: $s0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fmul_s64
@@ -544,22 +544,22 @@ registers:
- { id: 2, class: fprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
- %0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
+ %0(s64) = COPY $d0
+ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
- %1(s64) = COPY %d1
- ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
+ %1(s64) = COPY $d1
+ ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_FMUL %0, %1
- ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VMULD [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VMULD [[VREGX]], [[VREGY]], 14, $noreg
- %d0 = COPY %2(s64)
- ; CHECK: %d0 = COPY [[VREGSUM]]
+ $d0 = COPY %2(s64)
+ ; CHECK: $d0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fdiv_s32
@@ -574,22 +574,22 @@ registers:
- { id: 2, class: fprb }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
- %0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
+ %0(s32) = COPY $s0
+ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
- %1(s32) = COPY %s1
- ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
+ %1(s32) = COPY $s1
+ ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
%2(s32) = G_FDIV %0, %1
- ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VDIVS [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VDIVS [[VREGX]], [[VREGY]], 14, $noreg
- %s0 = COPY %2(s32)
- ; CHECK: %s0 = COPY [[VREGSUM]]
+ $s0 = COPY %2(s32)
+ ; CHECK: $s0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fdiv_s64
@@ -604,22 +604,22 @@ registers:
- { id: 2, class: fprb }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
- %0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
+ %0(s64) = COPY $d0
+ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
- %1(s64) = COPY %d1
- ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
+ %1(s64) = COPY $d1
+ ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
%2(s64) = G_FDIV %0, %1
- ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VDIVD [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VDIVD [[VREGX]], [[VREGY]], 14, $noreg
- %d0 = COPY %2(s64)
- ; CHECK: %d0 = COPY [[VREGSUM]]
+ $d0 = COPY %2(s64)
+ ; CHECK: $d0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fneg_s32
@@ -633,19 +633,19 @@ registers:
- { id: 1, class: fprb }
body: |
bb.0:
- liveins: %s0
+ liveins: $s0
- %0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
+ %0(s32) = COPY $s0
+ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = G_FNEG %0
- ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VNEGS [[VREGX]], 14, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VNEGS [[VREGX]], 14, $noreg
- %s0 = COPY %1(s32)
- ; CHECK: %s0 = COPY [[VREGSUM]]
+ $s0 = COPY %1(s32)
+ ; CHECK: $s0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fneg_s64
@@ -660,19 +660,19 @@ registers:
- { id: 2, class: fprb }
body: |
bb.0:
- liveins: %d0
+ liveins: $d0
- %0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
+ %0(s64) = COPY $d0
+ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s64) = G_FNEG %0
- ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VNEGD [[VREGX]], 14, %noreg
+ ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VNEGD [[VREGX]], 14, $noreg
- %d0 = COPY %1(s64)
- ; CHECK: %d0 = COPY [[VREGSUM]]
+ $d0 = COPY %1(s64)
+ ; CHECK: $d0 = COPY [[VREGSUM]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fma_s32
@@ -688,25 +688,25 @@ registers:
- { id: 3, class: fprb }
body: |
bb.0:
- liveins: %s0, %s1, %s2
+ liveins: $s0, $s1, $s2
- %0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
+ %0(s32) = COPY $s0
+ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
- %1(s32) = COPY %s1
- ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
+ %1(s32) = COPY $s1
+ ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1
- %2(s32) = COPY %s2
- ; CHECK: [[VREGZ:%[0-9]+]]:spr = COPY %s2
+ %2(s32) = COPY $s2
+ ; CHECK: [[VREGZ:%[0-9]+]]:spr = COPY $s2
%3(s32) = G_FMA %0, %1, %2
- ; CHECK: [[VREGR:%[0-9]+]]:spr = VFMAS [[VREGZ]], [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:spr = VFMAS [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
- %s0 = COPY %3(s32)
- ; CHECK: %s0 = COPY [[VREGR]]
+ $s0 = COPY %3(s32)
+ ; CHECK: $s0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fma_s64
@@ -722,25 +722,25 @@ registers:
- { id: 3, class: fprb }
body: |
bb.0:
- liveins: %d0, %d1, %d2
+ liveins: $d0, $d1, $d2
- %0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
+ %0(s64) = COPY $d0
+ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
- %1(s64) = COPY %d1
- ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
+ %1(s64) = COPY $d1
+ ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1
- %2(s64) = COPY %d2
- ; CHECK: [[VREGZ:%[0-9]+]]:dpr = COPY %d2
+ %2(s64) = COPY $d2
+ ; CHECK: [[VREGZ:%[0-9]+]]:dpr = COPY $d2
%3(s64) = G_FMA %0, %1, %2
- ; CHECK: [[VREGR:%[0-9]+]]:dpr = VFMAD [[VREGZ]], [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:dpr = VFMAD [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg
- %d0 = COPY %3(s64)
- ; CHECK: %d0 = COPY [[VREGR]]
+ $d0 = COPY %3(s64)
+ ; CHECK: $d0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fpext_s32_to_s64
@@ -754,19 +754,19 @@ registers:
- { id: 1, class: fprb }
body: |
bb.0:
- liveins: %s0
+ liveins: $s0
- %0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
+ %0(s32) = COPY $s0
+ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s64) = G_FPEXT %0(s32)
- ; CHECK: [[VREGR:%[0-9]+]]:dpr = VCVTDS [[VREGX]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:dpr = VCVTDS [[VREGX]], 14, $noreg
- %d0 = COPY %1(s64)
- ; CHECK: %d0 = COPY [[VREGR]]
+ $d0 = COPY %1(s64)
+ ; CHECK: $d0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_fptrunc_s64_to_s32
@@ -780,19 +780,19 @@ registers:
- { id: 1, class: fprb }
body: |
bb.0:
- liveins: %d0
+ liveins: $d0
- %0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
+ %0(s64) = COPY $d0
+ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s32) = G_FPTRUNC %0(s64)
- ; CHECK: [[VREGR:%[0-9]+]]:spr = VCVTSD [[VREGX]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:spr = VCVTSD [[VREGX]], 14, $noreg
- %s0 = COPY %1(s32)
- ; CHECK: %s0 = COPY [[VREGR]]
+ $s0 = COPY %1(s32)
+ ; CHECK: $s0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_fptosi_s32
@@ -806,20 +806,20 @@ registers:
- { id: 1, class: gprb }
body: |
bb.0:
- liveins: %s0
+ liveins: $s0
- %0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
+ %0(s32) = COPY $s0
+ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = G_FPTOSI %0(s32)
- ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZS [[VREGX]], 14, %noreg
+ ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZS [[VREGX]], 14, $noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]]
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_fptosi_s64
@@ -833,20 +833,20 @@ registers:
- { id: 1, class: gprb }
body: |
bb.0:
- liveins: %d0
+ liveins: $d0
- %0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
+ %0(s64) = COPY $d0
+ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s32) = G_FPTOSI %0(s64)
- ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZD [[VREGX]], 14, %noreg
+ ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZD [[VREGX]], 14, $noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]]
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_fptoui_s32
@@ -860,20 +860,20 @@ registers:
- { id: 1, class: gprb }
body: |
bb.0:
- liveins: %s0
+ liveins: $s0
- %0(s32) = COPY %s0
- ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
+ %0(s32) = COPY $s0
+ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0
%1(s32) = G_FPTOUI %0(s32)
- ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZS [[VREGX]], 14, %noreg
+ ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZS [[VREGX]], 14, $noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]]
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_fptoui_s64
@@ -887,20 +887,20 @@ registers:
- { id: 1, class: gprb }
body: |
bb.0:
- liveins: %d0
+ liveins: $d0
- %0(s64) = COPY %d0
- ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
+ %0(s64) = COPY $d0
+ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0
%1(s32) = G_FPTOUI %0(s64)
- ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZD [[VREGX]], 14, %noreg
+ ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZD [[VREGX]], 14, $noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]]
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[VREGR]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_sitofp_s32
@@ -914,20 +914,20 @@ registers:
- { id: 1, class: fprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_SITOFP %0(s32)
; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
- ; CHECK: [[VREGR:%[0-9]+]]:spr = VSITOS [[VREGF]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:spr = VSITOS [[VREGF]], 14, $noreg
- %s0 = COPY %1(s32)
- ; CHECK: %s0 = COPY [[VREGR]]
+ $s0 = COPY %1(s32)
+ ; CHECK: $s0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_sitofp_s64
@@ -941,20 +941,20 @@ registers:
- { id: 1, class: fprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s64) = G_SITOFP %0(s32)
; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
- ; CHECK: [[VREGR:%[0-9]+]]:dpr = VSITOD [[VREGF]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:dpr = VSITOD [[VREGF]], 14, $noreg
- %d0 = COPY %1(s64)
- ; CHECK: %d0 = COPY [[VREGR]]
+ $d0 = COPY %1(s64)
+ ; CHECK: $d0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_uitofp_s32
@@ -968,20 +968,20 @@ registers:
- { id: 1, class: fprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_UITOFP %0(s32)
; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
- ; CHECK: [[VREGR:%[0-9]+]]:spr = VUITOS [[VREGF]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:spr = VUITOS [[VREGF]], 14, $noreg
- %s0 = COPY %1(s32)
- ; CHECK: %s0 = COPY [[VREGR]]
+ $s0 = COPY %1(s32)
+ ; CHECK: $s0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_uitofp_s64
@@ -995,20 +995,20 @@ registers:
- { id: 1, class: fprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s64) = G_UITOFP %0(s32)
; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]]
- ; CHECK: [[VREGR:%[0-9]+]]:dpr = VUITOD [[VREGF]], 14, %noreg
+ ; CHECK: [[VREGR:%[0-9]+]]:dpr = VUITOD [[VREGF]], 14, $noreg
- %d0 = COPY %1(s64)
- ; CHECK: %d0 = COPY [[VREGR]]
+ $d0 = COPY %1(s64)
+ ; CHECK: $d0 = COPY [[VREGR]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_sub_s32
@@ -1023,22 +1023,22 @@ registers:
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
- %1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_SUB %0, %1
- ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
+ ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGRES]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGRES]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_sub_imm_s32
@@ -1053,20 +1053,20 @@ registers:
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 17
%2(s32) = G_SUB %0, %1
- ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBri [[VREGX]], 17, 14, %noreg, %noreg
+ ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBri [[VREGX]], 17, 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGRES]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGRES]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_sub_rev_imm_s32
@@ -1081,20 +1081,20 @@ registers:
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
%1(s32) = G_CONSTANT i32 17
%2(s32) = G_SUB %1, %0
- ; CHECK: [[VREGRES:%[0-9]+]]:gpr = RSBri [[VREGX]], 17, 14, %noreg, %noreg
+ ; CHECK: [[VREGRES:%[0-9]+]]:gpr = RSBri [[VREGX]], 17, 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGRES]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGRES]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_mul_s32
@@ -1109,22 +1109,22 @@ registers:
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
- %1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
%2(s32) = G_MUL %0, %1
- ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MUL [[VREGX]], [[VREGY]], 14, %noreg, %noreg
+ ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MUL [[VREGX]], [[VREGY]], 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGRES]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGRES]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_mulv5_s32
@@ -1139,22 +1139,22 @@ registers:
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
- %1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1
%2(s32) = G_MUL %0, %1
- ; CHECK: early-clobber [[VREGRES:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, %noreg, %noreg
+ ; CHECK: early-clobber [[VREGRES:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGRES]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGRES]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_sdiv_s32
@@ -1169,22 +1169,22 @@ registers:
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
- %1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_SDIV %0, %1
- ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SDIV [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SDIV [[VREGX]], [[VREGY]], 14, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGRES]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGRES]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_udiv_s32
@@ -1199,22 +1199,22 @@ registers:
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
- %1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_UDIV %0, %1
- ; CHECK: [[VREGRES:%[0-9]+]]:gpr = UDIV [[VREGX]], [[VREGY]], 14, %noreg
+ ; CHECK: [[VREGRES:%[0-9]+]]:gpr = UDIV [[VREGX]], [[VREGY]], 14, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGRES]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGRES]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_lshr_s32
@@ -1229,22 +1229,22 @@ registers:
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
- %1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_LSHR %0, %1
- ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 3, 14, %noreg, %noreg
+ ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 3, 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGRES]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGRES]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_ashr_s32
@@ -1259,22 +1259,22 @@ registers:
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
- %1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_ASHR %0, %1
- ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 1, 14, %noreg, %noreg
+ ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 1, 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGRES]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGRES]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_shl_s32
@@ -1289,22 +1289,22 @@ registers:
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
- %1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s32) = G_SHL %0, %1
- ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 2, 14, %noreg, %noreg
+ ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 2, 14, $noreg, $noreg
- %r0 = COPY %2(s32)
- ; CHECK: %r0 = COPY [[VREGRES]]
+ $r0 = COPY %2(s32)
+ ; CHECK: $r0 = COPY [[VREGRES]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_load_from_stack
@@ -1327,31 +1327,31 @@ fixedStack:
# CHECK-DAG: id: [[FI32:[0-9]+]], type: default, offset: 8
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
%0(p0) = G_FRAME_INDEX %fixed-stack.2
- ; CHECK: [[FI32VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI32]], 0, 14, %noreg, %noreg
+ ; CHECK: [[FI32VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI32]], 0, 14, $noreg, $noreg
%1(s32) = G_LOAD %0(p0) :: (load 4)
- ; CHECK: [[LD32VREG:%[0-9]+]]:gpr = LDRi12 [[FI32VREG]], 0, 14, %noreg
+ ; CHECK: [[LD32VREG:%[0-9]+]]:gpr = LDRi12 [[FI32VREG]], 0, 14, $noreg
- %r0 = COPY %1
- ; CHECK: %r0 = COPY [[LD32VREG]]
+ $r0 = COPY %1
+ ; CHECK: $r0 = COPY [[LD32VREG]]
%2(p0) = G_FRAME_INDEX %fixed-stack.0
- ; CHECK: [[FI1VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI1]], 0, 14, %noreg, %noreg
+ ; CHECK: [[FI1VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI1]], 0, 14, $noreg, $noreg
%3(s1) = G_LOAD %2(p0) :: (load 1)
- ; CHECK: [[LD1VREG:%[0-9]+]]:gprnopc = LDRBi12 [[FI1VREG]], 0, 14, %noreg
+ ; CHECK: [[LD1VREG:%[0-9]+]]:gprnopc = LDRBi12 [[FI1VREG]], 0, 14, $noreg
%4(s32) = G_ANYEXT %3(s1)
; CHECK: [[RES:%[0-9]+]]:gpr = COPY [[LD1VREG]]
- %r0 = COPY %4
- ; CHECK: %r0 = COPY [[RES]]
+ $r0 = COPY %4
+ ; CHECK: $r0 = COPY [[RES]]
- BX_RET 14, %noreg
- ; CHECK: BX_RET 14, %noreg
+ BX_RET 14, $noreg
+ ; CHECK: BX_RET 14, $noreg
...
---
name: test_load_f32
@@ -1365,19 +1365,19 @@ registers:
- { id: 1, class: fprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(p0) = COPY %r0
- ; CHECK: %[[P:[0-9]+]]:gpr = COPY %r0
+ %0(p0) = COPY $r0
+ ; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0
%1(s32) = G_LOAD %0(p0) :: (load 4)
- ; CHECK: %[[V:[0-9]+]]:spr = VLDRS %[[P]], 0, 14, %noreg
+ ; CHECK: %[[V:[0-9]+]]:spr = VLDRS %[[P]], 0, 14, $noreg
- %s0 = COPY %1
- ; CHECK: %s0 = COPY %[[V]]
+ $s0 = COPY %1
+ ; CHECK: $s0 = COPY %[[V]]
- BX_RET 14, %noreg, implicit %s0
- ; CHECK: BX_RET 14, %noreg, implicit %s0
+ BX_RET 14, $noreg, implicit $s0
+ ; CHECK: BX_RET 14, $noreg, implicit $s0
...
---
name: test_load_f64
@@ -1391,19 +1391,19 @@ registers:
- { id: 1, class: fprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(p0) = COPY %r0
- ; CHECK: %[[P:[0-9]+]]:gpr = COPY %r0
+ %0(p0) = COPY $r0
+ ; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0
%1(s64) = G_LOAD %0(p0) :: (load 8)
- ; CHECK: %[[V:[0-9]+]]:dpr = VLDRD %[[P]], 0, 14, %noreg
+ ; CHECK: %[[V:[0-9]+]]:dpr = VLDRD %[[P]], 0, 14, $noreg
- %d0 = COPY %1
- ; CHECK: %d0 = COPY %[[V]]
+ $d0 = COPY %1
+ ; CHECK: $d0 = COPY %[[V]]
- BX_RET 14, %noreg, implicit %d0
- ; CHECK: BX_RET 14, %noreg, implicit %d0
+ BX_RET 14, $noreg, implicit $d0
+ ; CHECK: BX_RET 14, $noreg, implicit $d0
...
---
name: test_stores
@@ -1427,31 +1427,31 @@ registers:
# CHECK: id: [[F64:[0-9]+]], class: dpr
body: |
bb.0:
- liveins: %r0, %r1, %s0, %d0
+ liveins: $r0, $r1, $s0, $d0
- %0(p0) = COPY %r0
- %3(s32) = COPY %r1
- %4(s32) = COPY %s0
- %5(s64) = COPY %d2
+ %0(p0) = COPY $r0
+ %3(s32) = COPY $r1
+ %4(s32) = COPY $s0
+ %5(s64) = COPY $d2
%1(s8) = G_TRUNC %3(s32)
%2(s16) = G_TRUNC %3(s32)
G_STORE %1(s8), %0(p0) :: (store 1)
- ; CHECK: STRBi12 %[[I8]], %[[P]], 0, 14, %noreg
+ ; CHECK: STRBi12 %[[I8]], %[[P]], 0, 14, $noreg
G_STORE %2(s16), %0(p0) :: (store 2)
- ; CHECK: STRH %[[I32]], %[[P]], %noreg, 0, 14, %noreg
+ ; CHECK: STRH %[[I32]], %[[P]], $noreg, 0, 14, $noreg
G_STORE %3(s32), %0(p0) :: (store 4)
- ; CHECK: STRi12 %[[I32]], %[[P]], 0, 14, %noreg
+ ; CHECK: STRi12 %[[I32]], %[[P]], 0, 14, $noreg
G_STORE %4(s32), %0(p0) :: (store 4)
- ; CHECK: VSTRS %[[F32]], %[[P]], 0, 14, %noreg
+ ; CHECK: VSTRS %[[F32]], %[[P]], 0, 14, $noreg
G_STORE %5(s64), %0(p0) :: (store 8)
- ; CHECK: VSTRD %[[F64]], %[[P]], 0, 14, %noreg
+ ; CHECK: VSTRD %[[F64]], %[[P]], 0, 14, $noreg
- BX_RET 14, %noreg
+ BX_RET 14, $noreg
...
---
name: test_gep
@@ -1466,19 +1466,19 @@ registers:
- { id: 2, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
- ; CHECK: %[[PTR:[0-9]+]]:gpr = COPY %r0
+ %0(p0) = COPY $r0
+ ; CHECK: %[[PTR:[0-9]+]]:gpr = COPY $r0
- %1(s32) = COPY %r1
- ; CHECK: %[[OFF:[0-9]+]]:gpr = COPY %r1
+ %1(s32) = COPY $r1
+ ; CHECK: %[[OFF:[0-9]+]]:gpr = COPY $r1
%2(p0) = G_GEP %0, %1(s32)
- ; CHECK: %[[GEP:[0-9]+]]:gpr = ADDrr %[[PTR]], %[[OFF]], 14, %noreg, %noreg
+ ; CHECK: %[[GEP:[0-9]+]]:gpr = ADDrr %[[PTR]], %[[OFF]], 14, $noreg, $noreg
- %r0 = COPY %2(p0)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(p0)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_constant_imm
@@ -1492,10 +1492,10 @@ registers:
body: |
bb.0:
%0(s32) = G_CONSTANT 42
- ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, %noreg, %noreg
+ ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, $noreg, $noreg
- %r0 = COPY %0(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %0(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_constant_cimm
@@ -1511,10 +1511,10 @@ body: |
; Adding a type on G_CONSTANT changes its operand from an Imm into a CImm.
; We still want to see the same thing in the output though.
%0(s32) = G_CONSTANT i32 42
- ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, %noreg, %noreg
+ ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, $noreg, $noreg
- %r0 = COPY %0(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %0(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_pointer_constant_unconstrained
@@ -1528,11 +1528,11 @@ registers:
body: |
bb.0:
%0(p0) = G_CONSTANT i32 0
- ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
+ ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
; This leaves %0 unconstrained before the G_CONSTANT is selected.
- %r0 = COPY %0(p0)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %0(p0)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_pointer_constant_constrained
@@ -1546,7 +1546,7 @@ registers:
body: |
bb.0:
%0(p0) = G_CONSTANT i32 0
- ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
+ ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg
; This constrains %0 before the G_CONSTANT is selected.
G_STORE %0(p0), %0(p0) :: (store 4)
@@ -1563,16 +1563,16 @@ registers:
- { id: 1, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(p0) = G_INTTOPTR %0(s32)
- ; CHECK: [[INT:%[0-9]+]]:gpr = COPY %r0
+ ; CHECK: [[INT:%[0-9]+]]:gpr = COPY $r0
- %r0 = COPY %1(p0)
- ; CHECK: %r0 = COPY [[INT]]
+ $r0 = COPY %1(p0)
+ ; CHECK: $r0 = COPY [[INT]]
- BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_ptrtoint_s32
@@ -1586,16 +1586,16 @@ registers:
- { id: 1, class: gprb }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s32) = G_PTRTOINT %0(p0)
- ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY %r0
+ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[PTR]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[PTR]]
- BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_select_s32
@@ -1611,25 +1611,25 @@ registers:
- { id: 3, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
- %1(s32) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
+ %1(s32) = COPY $r1
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
%2(s1) = G_TRUNC %1(s32)
%3(s32) = G_SELECT %2(s1), %0, %1
- ; CHECK: CMPri [[VREGY]], 0, 14, %noreg, implicit-def %cpsr
- ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, %cpsr
+ ; CHECK: CMPri [[VREGY]], 0, 14, $noreg, implicit-def $cpsr
+ ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, $cpsr
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[RES]]
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[RES]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_select_ptr
@@ -1646,28 +1646,28 @@ registers:
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(p0) = COPY %r0
- ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+ %0(p0) = COPY $r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
- %1(p0) = COPY %r1
- ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
+ %1(p0) = COPY $r1
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1
- %2(s32) = COPY %r2
- ; CHECK: [[VREGC:%[0-9]+]]:gpr = COPY %r2
+ %2(s32) = COPY $r2
+ ; CHECK: [[VREGC:%[0-9]+]]:gpr = COPY $r2
%3(s1) = G_TRUNC %2(s32)
%4(p0) = G_SELECT %3(s1), %0, %1
- ; CHECK: CMPri [[VREGC]], 0, 14, %noreg, implicit-def %cpsr
- ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, %cpsr
+ ; CHECK: CMPri [[VREGC]], 0, 14, $noreg, implicit-def $cpsr
+ ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, $cpsr
- %r0 = COPY %4(p0)
- ; CHECK: %r0 = COPY [[RES]]
+ $r0 = COPY %4(p0)
+ ; CHECK: $r0 = COPY [[RES]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_br
@@ -1683,15 +1683,15 @@ body: |
bb.0:
; CHECK: bb.0
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
- ; CHECK: [[COND32:%[0-9]+]]:gpr = COPY %r0
+ %0(s32) = COPY $r0
+ ; CHECK: [[COND32:%[0-9]+]]:gpr = COPY $r0
%1(s1) = G_TRUNC %0(s32)
G_BRCOND %1(s1), %bb.1
- ; CHECK: TSTri [[COND32]], 1, 14, %noreg, implicit-def %cpsr
- ; CHECK: Bcc %bb.1, 1, %cpsr
+ ; CHECK: TSTri [[COND32]], 1, 14, $noreg, implicit-def $cpsr
+ ; CHECK: Bcc %bb.1, 1, $cpsr
G_BR %bb.2
; CHECK: B %bb.2
@@ -1705,8 +1705,8 @@ body: |
bb.2:
; CHECK: bb.2
- BX_RET 14, %noreg
- ; CHECK: BX_RET 14, %noreg
+ BX_RET 14, $noreg
+ ; CHECK: BX_RET 14, $noreg
...
---
name: test_phi_s32
@@ -1726,15 +1726,15 @@ body: |
bb.0:
; CHECK: [[BB1:bb.0]]:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
- %2(s32) = COPY %r1
- %3(s32) = COPY %r2
- ; CHECK: [[V1:%[0-9]+]]:gpr = COPY %r1
- ; CHECK: [[V2:%[0-9]+]]:gpr = COPY %r2
+ %2(s32) = COPY $r1
+ %3(s32) = COPY $r2
+ ; CHECK: [[V1:%[0-9]+]]:gpr = COPY $r1
+ ; CHECK: [[V2:%[0-9]+]]:gpr = COPY $r2
G_BRCOND %1(s1), %bb.1
G_BR %bb.2
@@ -1751,8 +1751,8 @@ body: |
%4(s32) = G_PHI %2(s32), %bb.0, %3(s32), %bb.1
; CHECK: {{%[0-9]+}}:gpr = PHI [[V1]], %[[BB1]], [[V2]], %[[BB2]]
- %r0 = COPY %4(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %4(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_phi_s64
@@ -1772,15 +1772,15 @@ body: |
bb.0:
; CHECK: [[BB1:bb.0]]:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: %r0, %d0, %d1
+ liveins: $r0, $d0, $d1
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
- %2(s64) = COPY %d0
- %3(s64) = COPY %d1
- ; CHECK: [[V1:%[0-9]+]]:dpr = COPY %d0
- ; CHECK: [[V2:%[0-9]+]]:dpr = COPY %d1
+ %2(s64) = COPY $d0
+ %3(s64) = COPY $d1
+ ; CHECK: [[V1:%[0-9]+]]:dpr = COPY $d0
+ ; CHECK: [[V2:%[0-9]+]]:dpr = COPY $d1
G_BRCOND %1(s1), %bb.1
G_BR %bb.2
@@ -1797,8 +1797,8 @@ body: |
%4(s64) = G_PHI %2(s64), %bb.0, %3(s64), %bb.1
; CHECK: {{%[0-9]+}}:dpr = PHI [[V1]], %[[BB1]], [[V2]], %[[BB2]]
- %d0 = COPY %4(s64)
- BX_RET 14, %noreg, implicit %d0
+ $d0 = COPY %4(s64)
+ BX_RET 14, $noreg, implicit $d0
...
---
name: test_soft_fp_double
@@ -1815,13 +1815,13 @@ registers:
- { id: 4, class: gprb }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r2
- ; CHECK: [[IN1:%[0-9]+]]:gpr = COPY %r2
+ %0(s32) = COPY $r2
+ ; CHECK: [[IN1:%[0-9]+]]:gpr = COPY $r2
- %1(s32) = COPY %r3
- ; CHECK: [[IN2:%[0-9]+]]:gpr = COPY %r3
+ %1(s32) = COPY $r3
+ ; CHECK: [[IN2:%[0-9]+]]:gpr = COPY $r3
%2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
; CHECK: %[[DREG:[0-9]+]]:dpr = VMOVDRR [[IN1]], [[IN2]]
@@ -1829,12 +1829,12 @@ body: |
%3(s32), %4(s32) = G_UNMERGE_VALUES %2(s64)
; CHECK: [[OUT1:%[0-9]+]]:gpr, [[OUT2:%[0-9]+]]:gpr = VMOVRRD %[[DREG]]
- %r0 = COPY %3
- ; CHECK: %r0 = COPY [[OUT1]]
+ $r0 = COPY %3
+ ; CHECK: $r0 = COPY [[OUT1]]
- %r1 = COPY %4
- ; CHECK: %r1 = COPY [[OUT2]]
+ $r1 = COPY %4
+ ; CHECK: $r1 = COPY [[OUT2]]
- BX_RET 14, %noreg, implicit %r0, implicit %r1
- ; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
+ ; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1
...
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll Wed Jan 31 14:04:26 2018
@@ -4,22 +4,22 @@
define void @test_void_return() {
; CHECK-LABEL: name: test_void_return
-; CHECK: BX_RET 14, %noreg
+; CHECK: BX_RET 14, $noreg
entry:
ret void
}
define signext i1 @test_add_i1(i1 %x, i1 %y) {
; CHECK-LABEL: name: test_add_i1
-; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: liveins: $r0, $r1
+; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s1) = G_TRUNC [[VREGR0]]
-; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s1) = G_TRUNC [[VREGR1]]
; CHECK: [[SUM:%[0-9]+]]:_(s1) = G_ADD [[VREGX]], [[VREGY]]
; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_SEXT [[SUM]]
-; CHECK: %r0 = COPY [[EXT]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[EXT]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%sum = add i1 %x, %y
ret i1 %sum
@@ -27,15 +27,15 @@ entry:
define i8 @test_add_i8(i8 %x, i8 %y) {
; CHECK-LABEL: name: test_add_i8
-; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: liveins: $r0, $r1
+; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]
-; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR1]]
; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGX]], [[VREGY]]
; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
-; CHECK: %r0 = COPY [[SUM_EXT]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[SUM_EXT]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%sum = add i8 %x, %y
ret i8 %sum
@@ -43,15 +43,15 @@ entry:
define i8 @test_sub_i8(i8 %x, i8 %y) {
; CHECK-LABEL: name: test_sub_i8
-; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: liveins: $r0, $r1
+; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]
-; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR1]]
; CHECK: [[RES:%[0-9]+]]:_(s8) = G_SUB [[VREGX]], [[VREGY]]
; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]
-; CHECK: %r0 = COPY [[RES_EXT]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[RES_EXT]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%res = sub i8 %x, %y
ret i8 %res
@@ -59,27 +59,27 @@ entry:
define signext i8 @test_return_sext_i8(i8 %x) {
; CHECK-LABEL: name: test_return_sext_i8
-; CHECK: liveins: %r0
-; CHECK: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: liveins: $r0
+; CHECK: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: [[VREG:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]
; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_SEXT [[VREG]]
-; CHECK: %r0 = COPY [[VREGEXT]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[VREGEXT]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
ret i8 %x
}
define i16 @test_add_i16(i16 %x, i16 %y) {
; CHECK-LABEL: name: test_add_i16
-; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: liveins: $r0, $r1
+; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]
-; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]]
; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGX]], [[VREGY]]
; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
-; CHECK: %r0 = COPY [[SUM_EXT]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[SUM_EXT]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%sum = add i16 %x, %y
ret i16 %sum
@@ -87,15 +87,15 @@ entry:
define i16 @test_sub_i16(i16 %x, i16 %y) {
; CHECK-LABEL: name: test_sub_i16
-; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: liveins: $r0, $r1
+; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]
-; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]]
; CHECK: [[RES:%[0-9]+]]:_(s16) = G_SUB [[VREGX]], [[VREGY]]
; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]
-; CHECK: %r0 = COPY [[RES_EXT]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[RES_EXT]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%res = sub i16 %x, %y
ret i16 %res
@@ -103,24 +103,24 @@ entry:
define zeroext i16 @test_return_zext_i16(i16 %x) {
; CHECK-LABEL: name: test_return_zext_i16
-; CHECK: liveins: %r0
-; CHECK: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: liveins: $r0
+; CHECK: [[VREGR0:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: [[VREG:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]
; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREG]]
-; CHECK: %r0 = COPY [[VREGEXT]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[VREGEXT]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
ret i16 %x
}
define i32 @test_add_i32(i32 %x, i32 %y) {
; CHECK-LABEL: name: test_add_i32
-; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: liveins: $r0, $r1
+; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGX]], [[VREGY]]
-; CHECK: %r0 = COPY [[SUM]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[SUM]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%sum = add i32 %x, %y
ret i32 %sum
@@ -128,12 +128,12 @@ entry:
define i32 @test_sub_i32(i32 %x, i32 %y) {
; CHECK-LABEL: name: test_sub_i32
-; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: liveins: $r0, $r1
+; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SUB [[VREGX]], [[VREGY]]
-; CHECK: %r0 = COPY [[RES]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[RES]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%res = sub i32 %x, %y
ret i32 %res
@@ -144,13 +144,13 @@ define i32 @test_stack_args(i32 %p0, i32
; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 4
; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 4
-; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK: [[VREGP2:%[0-9]+]]:_(s32) = COPY %r2
+; CHECK: liveins: $r0, $r1, $r2, $r3
+; CHECK: [[VREGP2:%[0-9]+]]:_(s32) = COPY $r2
; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]]{{.*}}load 4
; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGP2]], [[VREGP5]]
-; CHECK: %r0 = COPY [[SUM]]
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[SUM]]
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%sum = add i32 %p2, %p5
ret i32 %sum
@@ -162,16 +162,16 @@ define i16 @test_stack_args_signext(i32
; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1
; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2
-; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: liveins: $r0, $r1, $r2, $r3
+; CHECK: [[VREGR1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[VREGP1:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]]
; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
; CHECK: [[VREGP5EXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4
; CHECK: [[VREGP5:%[0-9]+]]:_(s16) = G_TRUNC [[VREGP5EXT]]
; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGP1]], [[VREGP5]]
; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
-; CHECK: %r0 = COPY [[SUM_EXT]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[SUM_EXT]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%sum = add i16 %p1, %p5
ret i16 %sum
@@ -183,16 +183,16 @@ define i8 @test_stack_args_zeroext(i32 %
; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1
; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2
-; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK: [[VREGR2:%[0-9]+]]:_(s32) = COPY %r2
+; CHECK: liveins: $r0, $r1, $r2, $r3
+; CHECK: [[VREGR2:%[0-9]+]]:_(s32) = COPY $r2
; CHECK: [[VREGP2:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR2]]
; CHECK: [[FIP4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P4]]
; CHECK: [[VREGP4EXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP4]](p0){{.*}}load 4
; CHECK: [[VREGP4:%[0-9]+]]:_(s8) = G_TRUNC [[VREGP4EXT]]
; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[VREGP4]]
; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
-; CHECK: %r0 = COPY [[SUM_EXT]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[SUM_EXT]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%sum = add i8 %p2, %p4
ret i8 %sum
@@ -204,15 +204,15 @@ define i8 @test_stack_args_noext(i32 %p0
; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1
; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2
-; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK: [[VREGR2:%[0-9]+]]:_(s32) = COPY %r2
+; CHECK: liveins: $r0, $r1, $r2, $r3
+; CHECK: [[VREGR2:%[0-9]+]]:_(s32) = COPY $r2
; CHECK: [[VREGP2:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR2]]
; CHECK: [[FIP4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P4]]
; CHECK: [[VREGP4:%[0-9]+]]:_(s8) = G_LOAD [[FIP4]](p0){{.*}}load 1
; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[VREGP4]]
; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
-; CHECK: %r0 = COPY [[SUM_EXT]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[SUM_EXT]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%sum = add i8 %p2, %p4
ret i8 %sum
@@ -224,21 +224,21 @@ define zeroext i16 @test_stack_args_exte
; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1
; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2
-; CHECK: liveins: %r0, %r1, %r2, %r3
+; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
; CHECK: [[VREGP5SEXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4
; CHECK: [[VREGP5:%[0-9]+]]:_(s16) = G_TRUNC [[VREGP5SEXT]]
; CHECK: [[VREGP5ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREGP5]]
-; CHECK: %r0 = COPY [[VREGP5ZEXT]]
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[VREGP5ZEXT]]
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
ret i16 %p5
}
define i16 @test_ptr_arg(i16* %p) {
; CHECK-LABEL: name: test_ptr_arg
-; CHECK: liveins: %r0
-; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY %r0
+; CHECK: liveins: $r0
+; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY $r0
; CHECK: [[VREGV:%[0-9]+]]:_(s16) = G_LOAD [[VREGP]](p0){{.*}}load 2
entry:
%v = load i16, i16* %p
@@ -248,11 +248,11 @@ entry:
define i32* @test_ptr_ret(i32** %p) {
; Test pointer returns and pointer-to-pointer arguments
; CHECK-LABEL: name: test_ptr_ret
-; CHECK: liveins: %r0
-; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY %r0
+; CHECK: liveins: $r0
+; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY $r0
; CHECK: [[VREGV:%[0-9]+]]:_(p0) = G_LOAD [[VREGP]](p0){{.*}}load 4
-; CHECK: %r0 = COPY [[VREGV]]
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[VREGV]]
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%v = load i32*, i32** %p
ret i32* %v
@@ -262,12 +262,12 @@ define i32 @test_ptr_arg_on_stack(i32 %a
; CHECK-LABEL: name: test_ptr_arg_on_stack
; CHECK: fixedStack:
; CHECK: id: [[P:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4
-; CHECK: liveins: %r0, %r1, %r2, %r3
+; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: [[FIP:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P]]
; CHECK: [[VREGP:%[0-9]+]]:_(p0) = G_LOAD [[FIP]](p0){{.*}}load 4
; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_LOAD [[VREGP]](p0){{.*}}load 4
-; CHECK: %r0 = COPY [[VREGV]]
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[VREGV]]
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%v = load i32, i32* %p
ret i32 %v
@@ -279,13 +279,13 @@ define arm_aapcscc float @test_float_aap
; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4
; CHECK-DAG: id: [[P5:[0-9]+]]{{.*}}offset: 4{{.*}}size: 4
-; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK: [[VREGP1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: liveins: $r0, $r1, $r2, $r3
+; CHECK: [[VREGP1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4
; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGP5]]
-; CHECK: %r0 = COPY [[VREGV]]
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[VREGV]]
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%v = fadd float %p1, %p5
ret float %v
@@ -308,13 +308,13 @@ define arm_aapcs_vfpcc float @test_float
; CHECK: fixedStack:
; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4
; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 4{{.*}}size: 4
-; CHECK: liveins: %s0, %s1, %s2, %s3, %s4, %s5, %s6, %s7, %s8, %s9, %s10, %s11, %s12, %s13, %s14, %s15
-; CHECK: [[VREGP1:%[0-9]+]]:_(s32) = COPY %s1
+; CHECK: liveins: $s0, $s1, $s2, $s3, $s4, $s5, $s6, $s7, $s8, $s9, $s10, $s11, $s12, $s13, $s14, $s15
+; CHECK: [[VREGP1:%[0-9]+]]:_(s32) = COPY $s1
; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]
; CHECK: [[VREGQ1:%[0-9]+]]:_(s32) = G_LOAD [[FIQ1]](p0){{.*}}load 4
; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGQ1]]
-; CHECK: %s0 = COPY [[VREGV]]
-; CHECK: BX_RET 14, %noreg, implicit %s0
+; CHECK: $s0 = COPY [[VREGV]]
+; CHECK: BX_RET 14, $noreg, implicit $s0
entry:
%v = fadd float %p1, %q1
ret float %v
@@ -329,13 +329,13 @@ define arm_aapcs_vfpcc double @test_doub
; CHECK: fixedStack:
; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 8{{.*}}size: 8
-; CHECK: liveins: %d0, %d1, %d2, %d3, %d4, %d5, %d6, %d7
-; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = COPY %d1
+; CHECK: liveins: $d0, $d1, $d2, $d3, $d4, $d5, $d6, $d7
+; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = COPY $d1
; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]
; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8
; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]]
-; CHECK: %d0 = COPY [[VREGV]]
-; CHECK: BX_RET 14, %noreg, implicit %d0
+; CHECK: $d0 = COPY [[VREGV]]
+; CHECK: BX_RET 14, $noreg, implicit $d0
entry:
%v = fadd double %p1, %q1
ret double %v
@@ -349,9 +349,9 @@ define arm_aapcscc double @test_double_a
; CHECK-DAG: id: [[P3:[0-9]+]]{{.*}}offset: 8{{.*}}size: 8
; CHECK-DAG: id: [[P4:[0-9]+]]{{.*}}offset: 16{{.*}}size: 8
; CHECK-DAG: id: [[P5:[0-9]+]]{{.*}}offset: 24{{.*}}size: 8
-; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK-DAG: [[VREGP1LO:%[0-9]+]]:_(s32) = COPY %r2
-; CHECK-DAG: [[VREGP1HI:%[0-9]+]]:_(s32) = COPY %r3
+; CHECK: liveins: $r0, $r1, $r2, $r3
+; CHECK-DAG: [[VREGP1LO:%[0-9]+]]:_(s32) = COPY $r2
+; CHECK-DAG: [[VREGP1HI:%[0-9]+]]:_(s32) = COPY $r3
; LITTLE: [[VREGP1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP1LO]](s32), [[VREGP1HI]](s32)
; BIG: [[VREGP1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP1HI]](s32), [[VREGP1LO]](s32)
; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
@@ -359,9 +359,9 @@ define arm_aapcscc double @test_double_a
; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGP5]]
; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
-; CHECK-DAG: %r0 = COPY [[VREGVLO]]
-; CHECK-DAG: %r1 = COPY [[VREGVHI]]
-; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
+; CHECK-DAG: $r0 = COPY [[VREGVLO]]
+; CHECK-DAG: $r1 = COPY [[VREGVHI]]
+; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1
entry:
%v = fadd double %p1, %p5
ret double %v
@@ -377,13 +377,13 @@ define arm_aapcs_vfpcc double @test_doub
; CHECK: fixedStack:
; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 8{{.*}}size: 8
-; CHECK: liveins: %d0, %d2, %d3, %d4, %d5, %d6, %d7, %s2
-; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = COPY %d2
+; CHECK: liveins: $d0, $d2, $d3, $d4, $d5, $d6, $d7, $s2
+; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = COPY $d2
; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]
; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8
; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]]
-; CHECK: %d0 = COPY [[VREGV]]
-; CHECK: BX_RET 14, %noreg, implicit %d0
+; CHECK: $d0 = COPY [[VREGV]]
+; CHECK: BX_RET 14, $noreg, implicit $d0
entry:
%v = fadd double %p1, %q1
ret double %v
@@ -394,9 +394,9 @@ define arm_aapcscc double @test_double_g
; CHECK-LABEL: name: test_double_gap_aapcscc
; CHECK: fixedStack:
; CHECK-DAG: id: [[P1:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
-; CHECK: liveins: %r0, %r2, %r3
-; CHECK-DAG: [[VREGP0LO:%[0-9]+]]:_(s32) = COPY %r2
-; CHECK-DAG: [[VREGP0HI:%[0-9]+]]:_(s32) = COPY %r3
+; CHECK: liveins: $r0, $r2, $r3
+; CHECK-DAG: [[VREGP0LO:%[0-9]+]]:_(s32) = COPY $r2
+; CHECK-DAG: [[VREGP0HI:%[0-9]+]]:_(s32) = COPY $r3
; LITTLE: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0LO]](s32), [[VREGP0HI]](s32)
; BIG: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0HI]](s32), [[VREGP0LO]](s32)
; CHECK: [[FIP1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P1]]
@@ -404,9 +404,9 @@ define arm_aapcscc double @test_double_g
; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP0]], [[VREGP1]]
; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
-; CHECK-DAG: %r0 = COPY [[VREGVLO]]
-; CHECK-DAG: %r1 = COPY [[VREGVHI]]
-; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
+; CHECK-DAG: $r0 = COPY [[VREGVLO]]
+; CHECK-DAG: $r1 = COPY [[VREGVHI]]
+; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1
entry:
%v = fadd double %p0, %p1
ret double %v
@@ -417,9 +417,9 @@ define arm_aapcscc double @test_double_g
; CHECK-LABEL: name: test_double_gap2_aapcscc
; CHECK: fixedStack:
; CHECK-DAG: id: [[P1:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
-; CHECK: liveins: %r0, %r1, %r2
-; CHECK-DAG: [[VREGP0LO:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK-DAG: [[VREGP0HI:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: liveins: $r0, $r1, $r2
+; CHECK-DAG: [[VREGP0LO:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK-DAG: [[VREGP0HI:%[0-9]+]]:_(s32) = COPY $r1
; LITTLE: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0LO]](s32), [[VREGP0HI]](s32)
; BIG: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0HI]](s32), [[VREGP0LO]](s32)
; CHECK: [[FIP1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P1]]
@@ -427,9 +427,9 @@ define arm_aapcscc double @test_double_g
; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP0]], [[VREGP1]]
; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
-; CHECK-DAG: %r0 = COPY [[VREGVLO]]
-; CHECK-DAG: %r1 = COPY [[VREGVHI]]
-; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
+; CHECK-DAG: $r0 = COPY [[VREGVLO]]
+; CHECK-DAG: $r1 = COPY [[VREGVHI]]
+; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1
entry:
%v = fadd double %p0, %p1
ret double %v
@@ -437,7 +437,7 @@ entry:
define i32 @test_shufflevector_s32_v2s32(i32 %arg) {
; CHECK-LABEL: name: test_shufflevector_s32_v2s32
-; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-DAG: [[MASK:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C0]](s32)
@@ -451,8 +451,8 @@ define i32 @test_shufflevector_s32_v2s32
define i32 @test_shufflevector_v2s32_v3s32(i32 %arg1, i32 %arg2) {
; CHECK-LABEL: name: test_shufflevector_v2s32_v3s32
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[ARG2:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[ARG2:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
@@ -471,8 +471,8 @@ define i32 @test_shufflevector_v2s32_v3s
define i32 @test_shufflevector_v2s32_v4s32(i32 %arg1, i32 %arg2) {
; CHECK-LABEL: name: test_shufflevector_v2s32_v4s32
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[ARG2:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[ARG2:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
@@ -490,10 +490,10 @@ define i32 @test_shufflevector_v2s32_v4s
define i32 @test_shufflevector_v4s32_v2s32(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4) {
; CHECK-LABEL: name: test_shufflevector_v4s32_v2s32
-; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[ARG2:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK: [[ARG3:%[0-9]+]]:_(s32) = COPY %r2
-; CHECK: [[ARG4:%[0-9]+]]:_(s32) = COPY %r3
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[ARG2:%[0-9]+]]:_(s32) = COPY $r1
+; CHECK: [[ARG3:%[0-9]+]]:_(s32) = COPY $r2
+; CHECK: [[ARG4:%[0-9]+]]:_(s32) = COPY $r3
; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir Wed Jan 31 14:04:26 2018
@@ -35,27 +35,27 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; HWDIV: [[R:%[0-9]+]]:_(s32) = G_SDIV [[X]], [[Y]]
; SOFT-NOT: G_SDIV
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r0
- ; SOFT-DEFAULT: BL &__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT-DEFAULT: BL &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SDIV
%2(s32) = G_SDIV %0, %1
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_udiv_i32
@@ -71,27 +71,27 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; HWDIV: [[R:%[0-9]+]]:_(s32) = G_UDIV [[X]], [[Y]]
; SOFT-NOT: G_UDIV
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r0
- ; SOFT-DEFAULT: BL &__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT-DEFAULT: BL &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UDIV
%2(s32) = G_UDIV %0, %1
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_sdiv_i16
@@ -110,10 +110,10 @@ registers:
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+ ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
@@ -124,28 +124,28 @@ body: |
; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]]
; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32)
- %2(s32) = COPY %r1
+ %2(s32) = COPY $r1
%3(s16) = G_TRUNC %2(s32)
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]]
; SOFT-NOT: G_SDIV
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X32]]
- ; SOFT-DAG: %r1 = COPY [[Y32]]
- ; SOFT-AEABI: BL &__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r0
- ; SOFT-DEFAULT: BL &__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X32]]
+ ; SOFT-DAG: $r1 = COPY [[Y32]]
+ ; SOFT-AEABI: BL &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT-DEFAULT: BL &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SDIV
; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR
; SOFT-NOT: G_SDIV
%4(s16) = G_SDIV %1, %3
- ; CHECK: %r0 = COPY [[R]]
+ ; CHECK: $r0 = COPY [[R]]
%5(s32) = G_SEXT %4(s16)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_udiv_i16
@@ -164,10 +164,10 @@ registers:
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+ ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
@@ -176,28 +176,28 @@ body: |
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]]
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32)
- %2(s32) = COPY %r1
+ %2(s32) = COPY $r1
%3(s16) = G_TRUNC %2(s32)
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]]
; SOFT-NOT: G_UDIV
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X32]]
- ; SOFT-DAG: %r1 = COPY [[Y32]]
- ; SOFT-AEABI: BL &__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r0
- ; SOFT-DEFAULT: BL &__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X32]]
+ ; SOFT-DAG: $r1 = COPY [[Y32]]
+ ; SOFT-AEABI: BL &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT-DEFAULT: BL &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UDIV
; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND
; SOFT-NOT: G_UDIV
%4(s16) = G_UDIV %1, %3
- ; CHECK: %r0 = COPY [[R]]
+ ; CHECK: $r0 = COPY [[R]]
%5(s32) = G_ZEXT %4(s16)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_sdiv_i8
@@ -216,10 +216,10 @@ registers:
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+ ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
@@ -230,28 +230,28 @@ body: |
; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]]
; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32)
- %2(s32) = COPY %r1
+ %2(s32) = COPY $r1
%3(s8) = G_TRUNC %2(s32)
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]]
; SOFT-NOT: G_SDIV
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X32]]
- ; SOFT-DAG: %r1 = COPY [[Y32]]
- ; SOFT-AEABI: BL &__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r0
- ; SOFT-DEFAULT: BL &__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X32]]
+ ; SOFT-DAG: $r1 = COPY [[Y32]]
+ ; SOFT-AEABI: BL &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT-DEFAULT: BL &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SDIV
; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR
; SOFT-NOT: G_SDIV
%4(s8) = G_SDIV %1, %3
- ; CHECK: %r0 = COPY [[R]]
+ ; CHECK: $r0 = COPY [[R]]
%5(s32) = G_SEXT %4(s8)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_udiv_i8
@@ -270,10 +270,10 @@ registers:
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -282,28 +282,28 @@ body: |
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]]
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32)
- %2(s32) = COPY %r1
+ %2(s32) = COPY $r1
%3(s8) = G_TRUNC %2(s32)
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]]
; SOFT-NOT: G_UDIV
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X32]]
- ; SOFT-DAG: %r1 = COPY [[Y32]]
- ; SOFT-AEABI: BL &__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r0
- ; SOFT-DEFAULT: BL &__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X32]]
+ ; SOFT-DAG: $r1 = COPY [[Y32]]
+ ; SOFT-AEABI: BL &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT-DEFAULT: BL &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UDIV
; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND
; SOFT-NOT: G_UDIV
%4(s8) = G_UDIV %1, %3
- ; CHECK: %r0 = COPY [[R]]
+ ; CHECK: $r0 = COPY [[R]]
%5(s32) = G_ZEXT %4(s8)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_srem_i32
@@ -319,29 +319,29 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; HWDIV: [[Q:%[0-9]+]]:_(s32) = G_SDIV [[X]], [[Y]]
; HWDIV: [[P:%[0-9]+]]:_(s32) = G_MUL [[Q]], [[Y]]
; HWDIV: [[R:%[0-9]+]]:_(s32) = G_SUB [[X]], [[P]]
; SOFT-NOT: G_SREM
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r1
- ; SOFT-DEFAULT: BL &__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY $r1
+ ; SOFT-DEFAULT: BL &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SREM
%2(s32) = G_SREM %0, %1
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_urem_i32
@@ -357,29 +357,29 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; HWDIV: [[Q:%[0-9]+]]:_(s32) = G_UDIV [[X]], [[Y]]
; HWDIV: [[P:%[0-9]+]]:_(s32) = G_MUL [[Q]], [[Y]]
; HWDIV: [[R:%[0-9]+]]:_(s32) = G_SUB [[X]], [[P]]
; SOFT-NOT: G_UREM
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r1
- ; SOFT-DEFAULT: BL &__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY $r1
+ ; SOFT-DEFAULT: BL &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UREM
%2(s32) = G_UREM %0, %1
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_srem_i16
@@ -398,10 +398,10 @@ registers:
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+ ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
@@ -412,30 +412,30 @@ body: |
; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]]
; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32)
- %2(s32) = COPY %r1
+ %2(s32) = COPY $r1
%3(s16) = G_TRUNC %2(s32)
; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]]
; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]]
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]]
; SOFT-NOT: G_SREM
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X32]]
- ; SOFT-DAG: %r1 = COPY [[Y32]]
- ; SOFT-AEABI: BL &__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r1
- ; SOFT-DEFAULT: BL &__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X32]]
+ ; SOFT-DAG: $r1 = COPY [[Y32]]
+ ; SOFT-AEABI: BL &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r1
+ ; SOFT-DEFAULT: BL &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SREM
; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR
; SOFT-NOT: G_SREM
%4(s16) = G_SREM %1, %3
- ; CHECK: %r0 = COPY [[R]]
+ ; CHECK: $r0 = COPY [[R]]
%5(s32) = G_SEXT %4(s16)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_urem_i16
@@ -454,10 +454,10 @@ registers:
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+ ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
@@ -466,30 +466,30 @@ body: |
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]]
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32)
- %2(s32) = COPY %r1
+ %2(s32) = COPY $r1
%3(s16) = G_TRUNC %2(s32)
; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]]
; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]]
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]]
; SOFT-NOT: G_UREM
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X32]]
- ; SOFT-DAG: %r1 = COPY [[Y32]]
- ; SOFT-AEABI: BL &__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r1
- ; SOFT-DEFAULT: BL &__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X32]]
+ ; SOFT-DAG: $r1 = COPY [[Y32]]
+ ; SOFT-AEABI: BL &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r1
+ ; SOFT-DEFAULT: BL &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UREM
; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND
; SOFT-NOT: G_UREM
%4(s16) = G_UREM %1, %3
- ; CHECK: %r0 = COPY [[R]]
+ ; CHECK: $r0 = COPY [[R]]
%5(s32) = G_ZEXT %4(s16)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_srem_i8
@@ -508,10 +508,10 @@ registers:
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+ ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
@@ -522,30 +522,30 @@ body: |
; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]]
; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32)
- %2(s32) = COPY %r1
+ %2(s32) = COPY $r1
%3(s8) = G_TRUNC %2(s32)
; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]]
; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]]
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]]
; SOFT-NOT: G_SREM
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X32]]
- ; SOFT-DAG: %r1 = COPY [[Y32]]
- ; SOFT-AEABI: BL &__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r1
- ; SOFT-DEFAULT: BL &__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X32]]
+ ; SOFT-DAG: $r1 = COPY [[Y32]]
+ ; SOFT-AEABI: BL &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r1
+ ; SOFT-DEFAULT: BL &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SREM
; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR
; SOFT-NOT: G_SREM
%4(s8) = G_SREM %1, %3
- ; CHECK: %r0 = COPY [[R]]
+ ; CHECK: $r0 = COPY [[R]]
%5(s32) = G_SEXT %4(s8)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_urem_i8
@@ -564,10 +564,10 @@ registers:
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+ ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
@@ -576,28 +576,28 @@ body: |
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]]
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32)
- %2(s32) = COPY %r1
+ %2(s32) = COPY $r1
%3(s8) = G_TRUNC %2(s32)
; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]]
; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]]
; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]]
; SOFT-NOT: G_UREM
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X32]]
- ; SOFT-DAG: %r1 = COPY [[Y32]]
- ; SOFT-AEABI: BL &__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r1
- ; SOFT-DEFAULT: BL &__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X32]]
+ ; SOFT-DAG: $r1 = COPY [[Y32]]
+ ; SOFT-AEABI: BL &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r1
+ ; SOFT-DEFAULT: BL &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UREM
; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND
; SOFT-NOT: G_UREM
%4(s8) = G_UREM %1, %3
- ; CHECK: %r0 = COPY [[R]]
+ ; CHECK: $r0 = COPY [[R]]
%5(s32) = G_ZEXT %4(s8)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir Wed Jan 31 14:04:26 2018
@@ -91,28 +91,28 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; CHECK-NOT: G_FREM
; CHECK: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; HARD-DAG: %s0 = COPY [[X]]
- ; HARD-DAG: %s1 = COPY [[Y]]
- ; SOFT: BL &fmodf, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; HARD: BL &fmodf, {{.*}}, implicit %s0, implicit %s1, implicit-def %s0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
- ; HARD: [[R:%[0-9]+]]:_(s32) = COPY %s0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; HARD-DAG: $s0 = COPY [[X]]
+ ; HARD-DAG: $s1 = COPY [[Y]]
+ ; SOFT: BL &fmodf, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; HARD: BL &fmodf, {{.*}}, implicit $s0, implicit $s1, implicit-def $s0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
+ ; HARD: [[R:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP
; CHECK-NOT: G_FREM
%2(s32) = G_FREM %0, %1
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_frem_double
@@ -134,7 +134,7 @@ registers:
- { id: 8, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
; The inputs may be in the wrong order (depending on the target's
; endianness), but that's orthogonal to what we're trying to test here.
@@ -142,35 +142,35 @@ body: |
; through R0-R1, ends up in R0-R1 or R1-R0, and the second value, received
; through R2-R3, ends up in R2-R3 or R3-R2, when passed to fmod.
; For hard float, the values need to end up in D0 and D1.
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
%4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
%5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
; CHECK-NOT: G_FREM
; CHECK: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]]
- ; HARD-DAG: %d0 = COPY [[X]]
- ; HARD-DAG: %d1 = COPY [[Y]]
- ; SOFT: BL &fmod, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
- ; HARD: BL &fmod, {{.*}}, implicit %d0, implicit %d1, implicit-def %d0
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y0]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y1]]
+ ; HARD-DAG: $d0 = COPY [[X]]
+ ; HARD-DAG: $d1 = COPY [[Y]]
+ ; SOFT: BL &fmod, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
+ ; HARD: BL &fmod, {{.*}}, implicit $d0, implicit $d1, implicit-def $d0
; CHECK: ADJCALLSTACKUP
; CHECK-NOT: G_FREM
%6(s64) = G_FREM %4, %5
%7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64)
- %r0 = COPY %7(s32)
- %r1 = COPY %8(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ $r0 = COPY %7(s32)
+ $r1 = COPY %8(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
name: test_fpow_float
@@ -186,28 +186,28 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; CHECK-NOT: G_FPOW
; CHECK: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; HARD-DAG: %s0 = COPY [[X]]
- ; HARD-DAG: %s1 = COPY [[Y]]
- ; SOFT: BL &powf, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; HARD: BL &powf, {{.*}}, implicit %s0, implicit %s1, implicit-def %s0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
- ; HARD: [[R:%[0-9]+]]:_(s32) = COPY %s0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; HARD-DAG: $s0 = COPY [[X]]
+ ; HARD-DAG: $s1 = COPY [[Y]]
+ ; SOFT: BL &powf, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; HARD: BL &powf, {{.*}}, implicit $s0, implicit $s1, implicit-def $s0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
+ ; HARD: [[R:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP
; CHECK-NOT: G_FPOW
%2(s32) = G_FPOW %0, %1
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fpow_double
@@ -229,7 +229,7 @@ registers:
- { id: 8, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
; The inputs may be in the wrong order (depending on the target's
; endianness), but that's orthogonal to what we're trying to test here.
@@ -237,35 +237,35 @@ body: |
; through R0-R1, ends up in R0-R1 or R1-R0, and the second value, received
; through R2-R3, ends up in R2-R3 or R3-R2, when passed to pow.
; For hard float, the values need to end up in D0 and D1.
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
%4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
%5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
; CHECK-NOT: G_FPOW
; CHECK: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]]
- ; HARD-DAG: %d0 = COPY [[X]]
- ; HARD-DAG: %d1 = COPY [[Y]]
- ; SOFT: BL &pow, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
- ; HARD: BL &pow, {{.*}}, implicit %d0, implicit %d1, implicit-def %d0
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y0]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y1]]
+ ; HARD-DAG: $d0 = COPY [[X]]
+ ; HARD-DAG: $d1 = COPY [[Y]]
+ ; SOFT: BL &pow, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
+ ; HARD: BL &pow, {{.*}}, implicit $d0, implicit $d1, implicit-def $d0
; CHECK: ADJCALLSTACKUP
; CHECK-NOT: G_FPOW
%6(s64) = G_FPOW %4, %5
%7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64)
- %r0 = COPY %7(s32)
- %r1 = COPY %8(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ $r0 = COPY %7(s32)
+ $r1 = COPY %8(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
name: test_fadd_float
@@ -281,26 +281,26 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; HARD: [[R:%[0-9]+]]:_(s32) = G_FADD [[X]], [[Y]]
; SOFT-NOT: G_FADD
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fadd, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__addsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fadd, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__addsf3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FADD
%2(s32) = G_FADD %0, %1
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fadd_double
@@ -322,16 +322,16 @@ registers:
- { id: 8, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
%4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
@@ -339,20 +339,20 @@ body: |
; HARD: [[R:%[0-9]+]]:_(s64) = G_FADD [[X]], [[Y]]
; SOFT-NOT: G_FADD
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dadd, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
- ; SOFT-DEFAULT: BL &__adddf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y0]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dadd, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
+ ; SOFT-DEFAULT: BL &__adddf3, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FADD
%6(s64) = G_FADD %4, %5
; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
%7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
- %r0 = COPY %7(s32)
- %r1 = COPY %8(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ $r0 = COPY %7(s32)
+ $r1 = COPY %8(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
name: test_fsub_float
@@ -368,26 +368,26 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; HARD: [[R:%[0-9]+]]:_(s32) = G_FSUB [[X]], [[Y]]
; SOFT-NOT: G_FSUB
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fsub, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__subsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fsub, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__subsf3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FSUB
%2(s32) = G_FSUB %0, %1
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fsub_double
@@ -409,16 +409,16 @@ registers:
- { id: 8, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
%4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
@@ -426,20 +426,20 @@ body: |
; HARD: [[R:%[0-9]+]]:_(s64) = G_FSUB [[X]], [[Y]]
; SOFT-NOT: G_FSUB
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dsub, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
- ; SOFT-DEFAULT: BL &__subdf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y0]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dsub, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
+ ; SOFT-DEFAULT: BL &__subdf3, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FSUB
%6(s64) = G_FSUB %4, %5
; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
%7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
- %r0 = COPY %7(s32)
- %r1 = COPY %8(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ $r0 = COPY %7(s32)
+ $r1 = COPY %8(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
name: test_fmul_float
@@ -455,26 +455,26 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; HARD: [[R:%[0-9]+]]:_(s32) = G_FMUL [[X]], [[Y]]
; SOFT-NOT: G_FMUL
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fmul, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__mulsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fmul, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__mulsf3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FMUL
%2(s32) = G_FMUL %0, %1
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fmul_double
@@ -496,16 +496,16 @@ registers:
- { id: 8, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
%4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
@@ -513,20 +513,20 @@ body: |
; HARD: [[R:%[0-9]+]]:_(s64) = G_FMUL [[X]], [[Y]]
; SOFT-NOT: G_FMUL
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dmul, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
- ; SOFT-DEFAULT: BL &__muldf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y0]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dmul, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
+ ; SOFT-DEFAULT: BL &__muldf3, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FMUL
%6(s64) = G_FMUL %4, %5
; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
%7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
- %r0 = COPY %7(s32)
- %r1 = COPY %8(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ $r0 = COPY %7(s32)
+ $r1 = COPY %8(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
name: test_fdiv_float
@@ -542,26 +542,26 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; HARD: [[R:%[0-9]+]]:_(s32) = G_FDIV [[X]], [[Y]]
; SOFT-NOT: G_FDIV
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fdiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__divsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fdiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__divsf3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FDIV
%2(s32) = G_FDIV %0, %1
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fdiv_double
@@ -583,16 +583,16 @@ registers:
- { id: 8, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
%4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
@@ -600,20 +600,20 @@ body: |
; HARD: [[R:%[0-9]+]]:_(s64) = G_FDIV [[X]], [[Y]]
; SOFT-NOT: G_FDIV
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_ddiv, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
- ; SOFT-DEFAULT: BL &__divdf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y0]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_ddiv, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
+ ; SOFT-DEFAULT: BL &__divdf3, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FDIV
%6(s64) = G_FDIV %4, %5
; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
%7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
- %r0 = COPY %7(s32)
- %r1 = COPY %8(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ $r0 = COPY %7(s32)
+ $r1 = COPY %8(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
name: test_fconstant_float
@@ -634,9 +634,9 @@ body: |
; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1080033280
; SOFT-NOT: G_FCONSTANT
%0(s32) = G_FCONSTANT float -1.25
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %0(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %0(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fconstant_double
@@ -661,12 +661,12 @@ body: |
; SOFT-NOT: G_FCONSTANT
%0(s64) = G_FCONSTANT double -2.4
; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
- ; SOFT-DAG: %r0 = COPY [[HI]]
- ; SOFT-DAG: %r1 = COPY [[LO]]
+ ; SOFT-DAG: $r0 = COPY [[HI]]
+ ; SOFT-DAG: $r1 = COPY [[LO]]
%1(s32),%2(s32) = G_UNMERGE_VALUES %0(s64)
- %r0 = COPY %2(s32)
- %r1 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ $r0 = COPY %2(s32)
+ $r1 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
name: test_fneg_float
@@ -681,25 +681,25 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- %0(s32) = COPY %r0
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ %0(s32) = COPY $r0
; HARD: [[R:%[0-9]+]]:_(s32) = G_FNEG [[X]]
; SOFT-NOT: G_FNEG
; SOFT-DAG: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[ZERO]]
- ; SOFT-DAG: %r1 = COPY [[X]]
- ; SOFT-AEABI: BL &__aeabi_fsub, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__subsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[ZERO]]
+ ; SOFT-DAG: $r1 = COPY [[X]]
+ ; SOFT-AEABI: BL &__aeabi_fsub, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__subsf3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FNEG
%1(s32) = G_FNEG %0
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fneg_double
@@ -718,12 +718,12 @@ registers:
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
%2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
; HARD: [[R:%[0-9]+]]:_(s64) = G_FNEG [[X]]
@@ -731,20 +731,20 @@ body: |
; SOFT-DAG: [[NEGATIVE_ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; SOFT-DAG: [[POSITIVE_ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[NEGATIVE_ZERO]]
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[POSITIVE_ZERO]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[X0]]
- ; SOFT-DAG: %r{{[2-3]}} = COPY [[X1]]
- ; SOFT-AEABI: BL &__aeabi_dsub, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
- ; SOFT-DEFAULT: BL &__subdf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[NEGATIVE_ZERO]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[POSITIVE_ZERO]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[X0]]
+ ; SOFT-DAG: $r{{[2-3]}} = COPY [[X1]]
+ ; SOFT-AEABI: BL &__aeabi_dsub, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
+ ; SOFT-DEFAULT: BL &__subdf3, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FNEG
%3(s64) = G_FNEG %2
; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
%4(s32),%5(s32) = G_UNMERGE_VALUES %3(s64)
- %r0 = COPY %4(s32)
- %r1 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ $r0 = COPY %4(s32)
+ $r1 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
name: test_fpext_float_to_double
@@ -761,28 +761,28 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- %0(s32) = COPY %r0
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ %0(s32) = COPY $r0
; HARD: [[R:%[0-9]+]]:_(s64) = G_FPEXT [[X]]
; SOFT-NOT: G_FPEXT
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-AEABI: BL &__aeabi_f2d, {{.*}}, implicit %r0, implicit-def %r0, implicit-def %r1
- ; SOFT-DEFAULT: BL &__extendsfdf2, {{.*}}, implicit %r0, implicit-def %r0, implicit-def %r1
- ; SOFT: [[R0:%[0-9]+]]:_(s32) = COPY %r0
- ; SOFT: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-AEABI: BL &__aeabi_f2d, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
+ ; SOFT-DEFAULT: BL &__extendsfdf2, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
+ ; SOFT: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FPEXT
%1(s64) = G_FPEXT %0(s32)
; HARD: G_UNMERGE_VALUES [[R]](s64)
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[R0]]
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[R1]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[R0]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[R1]]
%2(s32), %3(s32) = G_UNMERGE_VALUES %1(s64)
- %r0 = COPY %2(s32)
- %r1 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ $r0 = COPY %2(s32)
+ $r1 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
name: test_fptrunc_double_to_float
@@ -799,28 +799,28 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
; HARD: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
; HARD: [[R:%[0-9]+]]:_(s32) = G_FPTRUNC [[X]]
; SOFT-NOT: G_FPTRUNC
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-AEABI: BL &__aeabi_d2f, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__truncdfsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-AEABI: BL &__aeabi_d2f, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__truncdfsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FPTRUNC
%3(s32) = G_FPTRUNC %2(s64)
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
---
---
name: test_fptosi_float
@@ -835,23 +835,23 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- %0(s32) = COPY %r0
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ %0(s32) = COPY $r0
; HARD: [[R:%[0-9]+]]:_(s32) = G_FPTOSI [[X]]
; SOFT-NOT: G_FPTOSI
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-AEABI: BL &__aeabi_f2iz, {{.*}}, implicit %r0, implicit-def %r0
- ; SOFT-DEFAULT: BL &__fixsfsi, {{.*}}, implicit %r0, implicit-def %r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-AEABI: BL &__aeabi_f2iz, {{.*}}, implicit $r0, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__fixsfsi, {{.*}}, implicit $r0, implicit-def $r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FPTOSI
%1(s32) = G_FPTOSI %0(s32)
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fptosi_double
@@ -868,28 +868,28 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; HARD: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
%2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
; HARD: [[R:%[0-9]+]]:_(s32) = G_FPTOSI [[X]]
; SOFT-NOT: G_FPTOSI
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
- ; SOFT-AEABI: BL &__aeabi_d2iz, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__fixdfsi, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
+ ; SOFT-AEABI: BL &__aeabi_d2iz, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__fixdfsi, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FPTOSI
%3(s32) = G_FPTOSI %2(s64)
- ; CHECK: %r0 = COPY [[R]](s32)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]](s32)
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fptoui_float
@@ -904,23 +904,23 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- %0(s32) = COPY %r0
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ %0(s32) = COPY $r0
; HARD: [[R:%[0-9]+]]:_(s32) = G_FPTOUI [[X]]
; SOFT-NOT: G_FPTOUI
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-AEABI: BL &__aeabi_f2uiz, {{.*}}, implicit %r0, implicit-def %r0
- ; SOFT-DEFAULT: BL &__fixunssfsi, {{.*}}, implicit %r0, implicit-def %r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-AEABI: BL &__aeabi_f2uiz, {{.*}}, implicit $r0, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__fixunssfsi, {{.*}}, implicit $r0, implicit-def $r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FPTOUI
%1(s32) = G_FPTOUI %0(s32)
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fptoui_double
@@ -937,28 +937,28 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
; HARD: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
%2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
; HARD: [[R:%[0-9]+]]:_(s32) = G_FPTOUI [[X]]
; SOFT-NOT: G_FPTOUI
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
- ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
- ; SOFT-AEABI: BL &__aeabi_d2uiz, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__fixunsdfsi, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X0]]
+ ; SOFT-DAG: $r{{[0-1]}} = COPY [[X1]]
+ ; SOFT-AEABI: BL &__aeabi_d2uiz, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__fixunsdfsi, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FPTOUI
%3(s32) = G_FPTOUI %2(s64)
- ; CHECK: %r0 = COPY [[R]](s32)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]](s32)
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_sitofp_float
@@ -973,23 +973,23 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- %0(s32) = COPY %r0
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ %0(s32) = COPY $r0
; HARD: [[R:%[0-9]+]]:_(s32) = G_SITOFP [[X]]
; SOFT-NOT: G_SITOFP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-AEABI: BL &__aeabi_i2f, {{.*}}, implicit %r0, implicit-def %r0
- ; SOFT-DEFAULT: BL &__floatsisf, {{.*}}, implicit %r0, implicit-def %r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-AEABI: BL &__aeabi_i2f, {{.*}}, implicit $r0, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__floatsisf, {{.*}}, implicit $r0, implicit-def $r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SITOFP
%1(s32) = G_SITOFP %0(s32)
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_sitofp_double
@@ -1006,28 +1006,28 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY %r0
- %0(s32) = COPY %r0
+ ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ %0(s32) = COPY $r0
; HARD: [[R:%[0-9]+]]:_(s64) = G_SITOFP [[X]]
; SOFT-NOT: G_SITOFP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT: %r0 = COPY [[X]]
- ; SOFT-AEABI: BL &__aeabi_i2d, {{.*}}, implicit %r0, implicit-def %r0, implicit-def %r1
- ; SOFT-DEFAULT: BL &__floatsidf, {{.*}}, implicit %r0, implicit-def %r0, implicit-def %r1
- ; SOFT-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
- ; SOFT-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+ ; SOFT: $r0 = COPY [[X]]
+ ; SOFT-AEABI: BL &__aeabi_i2d, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
+ ; SOFT-DEFAULT: BL &__floatsidf, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
+ ; SOFT-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SITOFP
%1(s64) = G_SITOFP %0(s32)
; HARD: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R]]
%2(s32), %3(s32) = G_UNMERGE_VALUES %1(s64)
- ; CHECK-DAG: %r0 = COPY [[R0]](s32)
- ; CHECK-DAG: %r1 = COPY [[R1]](s32)
- %r0 = COPY %2(s32)
- %r1 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ ; CHECK-DAG: $r0 = COPY [[R0]](s32)
+ ; CHECK-DAG: $r1 = COPY [[R1]](s32)
+ $r0 = COPY %2(s32)
+ $r1 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
---
name: test_uitofp_float
@@ -1042,23 +1042,23 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- %0(s32) = COPY %r0
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ %0(s32) = COPY $r0
; HARD: [[R:%[0-9]+]]:_(s32) = G_UITOFP [[X]]
; SOFT-NOT: G_UITOFP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-AEABI: BL &__aeabi_ui2f, {{.*}}, implicit %r0, implicit-def %r0
- ; SOFT-DEFAULT: BL &__floatunsisf, {{.*}}, implicit %r0, implicit-def %r0
- ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-AEABI: BL &__aeabi_ui2f, {{.*}}, implicit $r0, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__floatunsisf, {{.*}}, implicit $r0, implicit-def $r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UITOFP
%1(s32) = G_UITOFP %0(s32)
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_uitofp_double
@@ -1075,28 +1075,28 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY %r0
- %0(s32) = COPY %r0
+ ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ %0(s32) = COPY $r0
; HARD: [[R:%[0-9]+]]:_(s64) = G_UITOFP [[X]]
; SOFT-NOT: G_UITOFP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT: %r0 = COPY [[X]]
- ; SOFT-AEABI: BL &__aeabi_ui2d, {{.*}}, implicit %r0, implicit-def %r0, implicit-def %r1
- ; SOFT-DEFAULT: BL &__floatunsidf, {{.*}}, implicit %r0, implicit-def %r0, implicit-def %r1
- ; SOFT-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
- ; SOFT-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+ ; SOFT: $r0 = COPY [[X]]
+ ; SOFT-AEABI: BL &__aeabi_ui2d, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
+ ; SOFT-DEFAULT: BL &__floatunsidf, {{.*}}, implicit $r0, implicit-def $r0, implicit-def $r1
+ ; SOFT-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UITOFP
%1(s64) = G_UITOFP %0(s32)
; HARD: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R]]
%2(s32), %3(s32) = G_UNMERGE_VALUES %1(s64)
- ; CHECK-DAG: %r0 = COPY [[R0]](s32)
- ; CHECK-DAG: %r1 = COPY [[R1]](s32)
- %r0 = COPY %2(s32)
- %r1 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ ; CHECK-DAG: $r0 = COPY [[R0]](s32)
+ ; CHECK-DAG: $r1 = COPY [[R1]](s32)
+ $r0 = COPY %2(s32)
+ $r1 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
...
name: test_fcmp_true_s32
@@ -1113,16 +1113,16 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(true), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
- ; HARD-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
+ ; HARD-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(true), [[X]](s32), [[Y]]
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
@@ -1133,7 +1133,7 @@ body: |
; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]](s32)
; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP
- ; CHECK: %r0 = COPY [[REXT]]
+ ; CHECK: $r0 = COPY [[REXT]]
...
---
name: test_fcmp_false_s32
@@ -1150,16 +1150,16 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(false), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
- ; HARD-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; HARD-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
+ ; HARD-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(false), [[X]](s32), [[Y]]
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
@@ -1170,7 +1170,7 @@ body: |
; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]](s32)
; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP
- ; CHECK: %r0 = COPY [[REXT]]
+ ; CHECK: $r0 = COPY [[REXT]]
...
---
name: test_fcmp_oeq_s32
@@ -1187,22 +1187,22 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(oeq), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[X]](s32), [[Y]]
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__eqsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__eqsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
@@ -1214,9 +1214,9 @@ body: |
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ogt_s32
@@ -1233,22 +1233,22 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(ogt), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[X]](s32), [[Y]]
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__gtsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
@@ -1260,9 +1260,9 @@ body: |
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_oge_s32
@@ -1279,22 +1279,22 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(oge), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[X]](s32), [[Y]]
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmpge, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__gesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmpge, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__gesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
@@ -1306,9 +1306,9 @@ body: |
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_olt_s32
@@ -1325,22 +1325,22 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(olt), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[X]](s32), [[Y]]
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmplt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__ltsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
@@ -1352,9 +1352,9 @@ body: |
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ole_s32
@@ -1371,22 +1371,22 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(ole), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ole), [[X]](s32), [[Y]]
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmple, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__lesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmple, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__lesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
@@ -1398,9 +1398,9 @@ body: |
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ord_s32
@@ -1417,30 +1417,30 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(ord), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[X]](s32), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmpun, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__unordsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ugt_s32
@@ -1457,21 +1457,21 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(ugt), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ugt), [[X]](s32), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmple, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__lesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmple, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__lesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
@@ -1479,9 +1479,9 @@ body: |
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_uge_s32
@@ -1498,21 +1498,21 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(uge), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uge), [[X]](s32), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmplt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__ltsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
@@ -1520,9 +1520,9 @@ body: |
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ult_s32
@@ -1539,21 +1539,21 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(ult), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ult), [[X]](s32), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmpge, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__gesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmpge, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__gesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
@@ -1561,9 +1561,9 @@ body: |
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ule_s32
@@ -1580,21 +1580,21 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(ule), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[X]](s32), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__gtsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
@@ -1602,9 +1602,9 @@ body: |
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_une_s32
@@ -1621,21 +1621,21 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(une), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(une), [[X]](s32), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__nesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__nesf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
@@ -1643,9 +1643,9 @@ body: |
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_uno_s32
@@ -1662,22 +1662,22 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(uno), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uno), [[X]](s32), [[Y]]
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmpun, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__unordsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
@@ -1689,9 +1689,9 @@ body: |
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_one_s32
@@ -1708,32 +1708,32 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(one), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[X]](s32), [[Y]]
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__gtsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET1]](s32), [[ZERO]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmplt, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__ltsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]]
@@ -1749,9 +1749,9 @@ body: |
; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ueq_s32
@@ -1768,32 +1768,32 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
%2(s1) = G_FCMP floatpred(ueq), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ueq), [[X]](s32), [[Y]]
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__eqsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__eqsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET1]](s32), [[ZERO]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X]]
- ; SOFT-DAG: %r1 = COPY [[Y]]
- ; SOFT-AEABI: BL &__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT-DEFAULT: BL &__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
- ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X]]
+ ; SOFT-DAG: $r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL &__aeabi_fcmpun, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__unordsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
+ ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]]
@@ -1809,9 +1809,9 @@ body: |
; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_true_s64
@@ -1832,16 +1832,16 @@ registers:
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -1858,9 +1858,9 @@ body: |
; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_false_s64
@@ -1881,16 +1881,16 @@ registers:
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -1908,9 +1908,9 @@ body: |
; SOFT-NOT: G_FCMP
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_oeq_s64
@@ -1931,16 +1931,16 @@ registers:
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -1950,13 +1950,13 @@ body: |
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__eqdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__eqdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
@@ -1968,9 +1968,9 @@ body: |
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ogt_s64
@@ -1991,16 +1991,16 @@ registers:
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2010,13 +2010,13 @@ body: |
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__gtdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
@@ -2028,9 +2028,9 @@ body: |
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_oge_s64
@@ -2051,16 +2051,16 @@ registers:
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2070,13 +2070,13 @@ body: |
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmpge, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__gedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmpge, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__gedf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
@@ -2088,9 +2088,9 @@ body: |
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_olt_s64
@@ -2111,16 +2111,16 @@ registers:
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2130,13 +2130,13 @@ body: |
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmplt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__ltdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
@@ -2148,9 +2148,9 @@ body: |
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ole_s64
@@ -2171,16 +2171,16 @@ registers:
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2190,13 +2190,13 @@ body: |
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmple, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__ledf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmple, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__ledf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
@@ -2208,9 +2208,9 @@ body: |
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ord_s64
@@ -2231,16 +2231,16 @@ registers:
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2249,22 +2249,22 @@ body: |
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[X]](s64), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmpun, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__unorddf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ugt_s64
@@ -2285,16 +2285,16 @@ registers:
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2303,13 +2303,13 @@ body: |
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ugt), [[X]](s64), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmple, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__ledf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmple, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__ledf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
@@ -2317,9 +2317,9 @@ body: |
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_uge_s64
@@ -2340,16 +2340,16 @@ registers:
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2358,13 +2358,13 @@ body: |
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uge), [[X]](s64), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmplt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__ltdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
@@ -2372,9 +2372,9 @@ body: |
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ult_s64
@@ -2395,16 +2395,16 @@ registers:
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2413,13 +2413,13 @@ body: |
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ult), [[X]](s64), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmpge, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__gedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmpge, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__gedf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
@@ -2427,9 +2427,9 @@ body: |
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ule_s64
@@ -2450,16 +2450,16 @@ registers:
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2468,13 +2468,13 @@ body: |
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[X]](s64), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__gtdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
@@ -2482,9 +2482,9 @@ body: |
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_une_s64
@@ -2505,16 +2505,16 @@ registers:
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2523,13 +2523,13 @@ body: |
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(une), [[X]](s64), [[Y]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__nedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__nedf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
@@ -2537,9 +2537,9 @@ body: |
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_uno_s64
@@ -2560,16 +2560,16 @@ registers:
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2579,13 +2579,13 @@ body: |
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmpun, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__unorddf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
@@ -2597,9 +2597,9 @@ body: |
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_one_s64
@@ -2620,16 +2620,16 @@ registers:
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2639,25 +2639,25 @@ body: |
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmpgt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__gtdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET1]](s32), [[ZERO]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmplt, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__ltdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]]
@@ -2673,9 +2673,9 @@ body: |
; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fcmp_ueq_s64
@@ -2696,16 +2696,16 @@ registers:
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
%4(s64) = G_MERGE_VALUES %0(s32), %1
%5(s64) = G_MERGE_VALUES %2(s32), %3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
@@ -2715,25 +2715,25 @@ body: |
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__eqdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmpeq, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__eqdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET1]](s32), [[ZERO]]
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-DAG: %r0 = COPY [[X0]]
- ; SOFT-DAG: %r1 = COPY [[X1]]
- ; SOFT-DAG: %r2 = COPY [[Y0]]
- ; SOFT-DAG: %r3 = COPY [[Y1]]
- ; SOFT-AEABI: BL &__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT-DEFAULT: BL &__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
- ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT-DAG: $r0 = COPY [[X0]]
+ ; SOFT-DAG: $r1 = COPY [[X1]]
+ ; SOFT-DAG: $r2 = COPY [[Y0]]
+ ; SOFT-DAG: $r3 = COPY [[Y1]]
+ ; SOFT-AEABI: BL &__aeabi_dcmpun, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT-DEFAULT: BL &__unorddf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+ ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]]
@@ -2749,7 +2749,7 @@ body: |
; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- %r0 = COPY %7(s32)
- ; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %7(s32)
+ ; CHECK: $r0 = COPY [[REXT]]
+ BX_RET 14, $noreg, implicit $r0
...
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir Wed Jan 31 14:04:26 2018
@@ -21,33 +21,33 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Z:%[0-9]+]]:_(s32) = COPY %r2
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Z:%[0-9]+]]:_(s32) = COPY $r2
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
; HARD: [[R:%[0-9]+]]:_(s32) = G_FMA [[X]], [[Y]], [[Z]]
; SOFT-NOT: G_FMA
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-ABI-DAG: %r0 = COPY [[X]]
- ; SOFT-ABI-DAG: %r1 = COPY [[Y]]
- ; SOFT-ABI-DAG: %r2 = COPY [[Z]]
- ; SOFT-ABI: BL &fmaf, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit-def %r0
- ; SOFT-ABI: [[R:%[0-9]+]]:_(s32) = COPY %r0
- ; HARD-ABI-DAG: %s0 = COPY [[X]]
- ; HARD-ABI-DAG: %s1 = COPY [[Y]]
- ; HARD-ABI-DAG: %s2 = COPY [[Z]]
- ; HARD-ABI: BL &fmaf, {{.*}}, implicit %s0, implicit %s1, implicit %s2, implicit-def %s0
- ; HARD-ABI: [[R:%[0-9]+]]:_(s32) = COPY %s0
+ ; SOFT-ABI-DAG: $r0 = COPY [[X]]
+ ; SOFT-ABI-DAG: $r1 = COPY [[Y]]
+ ; SOFT-ABI-DAG: $r2 = COPY [[Z]]
+ ; SOFT-ABI: BL &fmaf, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit-def $r0
+ ; SOFT-ABI: [[R:%[0-9]+]]:_(s32) = COPY $r0
+ ; HARD-ABI-DAG: $s0 = COPY [[X]]
+ ; HARD-ABI-DAG: $s1 = COPY [[Y]]
+ ; HARD-ABI-DAG: $s2 = COPY [[Z]]
+ ; HARD-ABI: BL &fmaf, {{.*}}, implicit $s0, implicit $s1, implicit $s2, implicit-def $s0
+ ; HARD-ABI: [[R:%[0-9]+]]:_(s32) = COPY $s0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FMA
%3(s32) = G_FMA %0, %1, %2
- ; CHECK: %r0 = COPY [[R]]
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]]
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fma_double
@@ -69,16 +69,16 @@ registers:
- { id: 8, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
- ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
- ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
- ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
- %3(s32) = COPY %r3
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY $r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY $r3
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
+ %3(s32) = COPY $r3
; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
; HARD-ABI-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
@@ -88,34 +88,34 @@ body: |
; HARD: [[R:%[0-9]+]]:_(s64) = G_FMA [[X]], [[X]], [[Y]]
; SOFT-NOT: G_FMA
; SOFT: ADJCALLSTACKDOWN
- ; SOFT-ABI-DAG: %r{{[0-1]}} = COPY [[X0]]
- ; SOFT-ABI-DAG: %r{{[0-1]}} = COPY [[X1]]
- ; SOFT-ABI-DAG: %r{{[2-3]}} = COPY [[X0]]
- ; SOFT-ABI-DAG: %r{{[2-3]}} = COPY [[X1]]
- ; SOFT-ABI: [[SP1:%[0-9]+]]:_(p0) = COPY %sp
+ ; SOFT-ABI-DAG: $r{{[0-1]}} = COPY [[X0]]
+ ; SOFT-ABI-DAG: $r{{[0-1]}} = COPY [[X1]]
+ ; SOFT-ABI-DAG: $r{{[2-3]}} = COPY [[X0]]
+ ; SOFT-ABI-DAG: $r{{[2-3]}} = COPY [[X1]]
+ ; SOFT-ABI: [[SP1:%[0-9]+]]:_(p0) = COPY $sp
; SOFT-ABI: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-ABI: [[FI1:%[0-9]+]]:_(p0) = G_GEP [[SP1]], [[OFF1]](s32)
; SOFT-ABI: G_STORE [[Y0]](s32), [[FI1]](p0){{.*}}store 8 into stack
; SOFT-ABI: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; SOFT-ABI: [[FI2:%[0-9]+]]:_(p0) = G_GEP [[FI1]], [[OFF2]](s32)
; SOFT-ABI: G_STORE [[Y1]](s32), [[FI2]](p0){{.*}}store 8 into stack
- ; SOFT-ABI: BL &fma, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
- ; SOFT-ABI-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
- ; SOFT-ABI-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
- ; HARD-ABI-DAG: %d0 = COPY [[X]]
- ; HARD-ABI-DAG: %d1 = COPY [[X]]
- ; HARD-ABI-DAG: %d2 = COPY [[Y]]
- ; HARD-ABI: BL &fma, {{.*}}, implicit %d0, implicit %d1, implicit %d2, implicit-def %d0
- ; HARD-ABI: [[R:%[0-9]+]]:_(s64) = COPY %d0
+ ; SOFT-ABI: BL &fma, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
+ ; SOFT-ABI-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+ ; SOFT-ABI-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
+ ; HARD-ABI-DAG: $d0 = COPY [[X]]
+ ; HARD-ABI-DAG: $d1 = COPY [[X]]
+ ; HARD-ABI-DAG: $d2 = COPY [[Y]]
+ ; HARD-ABI: BL &fma, {{.*}}, implicit $d0, implicit $d1, implicit $d2, implicit-def $d0
+ ; HARD-ABI: [[R:%[0-9]+]]:_(s64) = COPY $d0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FMA
%6(s64) = G_FMA %4, %4, %5
; HARD: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R]](s64)
; HARD-ABI: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R]](s64)
%7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
- ; CHECK-DAG: %r0 = COPY [[R0]]
- ; CHECK-DAG: %r1 = COPY [[R1]]
- %r0 = COPY %7(s32)
- %r1 = COPY %8(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ ; CHECK-DAG: $r0 = COPY [[R0]]
+ ; CHECK-DAG: $r1 = COPY [[R1]]
+ $r0 = COPY %7(s32)
+ $r1 = COPY %8(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir Wed Jan 31 14:04:26 2018
@@ -74,15 +74,15 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s8) = G_LOAD %0(p0) :: (load 1)
%2(s32) = G_SEXT %1
; G_SEXT with s8 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_SEXT {{%[0-9]+}}
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_zext_s16
@@ -98,15 +98,15 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s16) = G_LOAD %0 :: (load 2)
%2(s32) = G_ZEXT %1
; G_ZEXT with s16 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_ZEXT {{%[0-9]+}}
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_inttoptr_s32
@@ -121,14 +121,14 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(p0) = G_INTTOPTR %0(s32)
; G_INTTOPTR with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(p0) = G_INTTOPTR {{%[0-9]+}}
- %r0 = COPY %1(p0)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %1(p0)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_ptrtoint_s32
@@ -143,14 +143,14 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s32) = G_PTRTOINT %0(p0)
; G_PTRTOINT with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_PTRTOINT {{%[0-9]+}}
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_add_s8
@@ -169,11 +169,11 @@ registers:
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s8) = G_LOAD %0 :: (load 1)
- %2(p0) = COPY %r0
+ %2(p0) = COPY $r0
%3(s8) = G_LOAD %2 :: (load 1)
%4(s8) = G_ADD %1, %3
; G_ADD with s8 should widen
@@ -181,8 +181,8 @@ body: |
; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_ADD {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s8)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_add_s16
@@ -201,11 +201,11 @@ registers:
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s16) = G_LOAD %0 :: (load 2)
- %2(p0) = COPY %r0
+ %2(p0) = COPY $r0
%3(s16) = G_LOAD %2 :: (load 2)
%4(s16) = G_ADD %1, %3
; G_ADD with s16 should widen
@@ -213,8 +213,8 @@ body: |
; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_ADD {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s16)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_add_s32
@@ -230,15 +230,15 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_ADD %0, %1
; G_ADD with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -258,11 +258,11 @@ registers:
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s8) = G_LOAD %0 :: (load 1)
- %2(p0) = COPY %r0
+ %2(p0) = COPY $r0
%3(s8) = G_LOAD %2 :: (load 1)
%4(s8) = G_SUB %1, %3
; G_SUB with s8 should widen
@@ -270,8 +270,8 @@ body: |
; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_SUB {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s8)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_sub_s16
@@ -290,11 +290,11 @@ registers:
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s16) = G_LOAD %0 :: (load 2)
- %2(p0) = COPY %r0
+ %2(p0) = COPY $r0
%3(s16) = G_LOAD %2 :: (load 2)
%4(s16) = G_SUB %1, %3
; G_SUB with s16 should widen
@@ -302,8 +302,8 @@ body: |
; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_SUB {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s16)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_sub_s32
@@ -319,15 +319,15 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_SUB %0, %1
; G_SUB with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -347,11 +347,11 @@ registers:
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s8) = G_LOAD %0 :: (load 1)
- %2(p0) = COPY %r0
+ %2(p0) = COPY $r0
%3(s8) = G_LOAD %2 :: (load 1)
%4(s8) = G_MUL %1, %3
; G_MUL with s8 should widen
@@ -359,8 +359,8 @@ body: |
; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_MUL {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s8)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_mul_s16
@@ -379,11 +379,11 @@ registers:
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s16) = G_LOAD %0 :: (load 2)
- %2(p0) = COPY %r0
+ %2(p0) = COPY $r0
%3(s16) = G_LOAD %2 :: (load 2)
%4(s16) = G_MUL %1, %3
; G_MUL with s16 should widen
@@ -391,8 +391,8 @@ body: |
; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_MUL {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s16)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_mul_s32
@@ -408,15 +408,15 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_MUL %0, %1
; G_MUL with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -436,11 +436,11 @@ registers:
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s8) = G_LOAD %0 :: (load 1)
- %2(p0) = COPY %r0
+ %2(p0) = COPY $r0
%3(s8) = G_LOAD %2 :: (load 1)
%4(s8) = G_AND %1, %3
; G_AND with s8 should widen
@@ -448,8 +448,8 @@ body: |
; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_AND {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s8)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_and_s16
@@ -468,11 +468,11 @@ registers:
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s16) = G_LOAD %0 :: (load 2)
- %2(p0) = COPY %r0
+ %2(p0) = COPY $r0
%3(s16) = G_LOAD %2 :: (load 2)
%4(s16) = G_AND %1, %3
; G_AND with s16 should widen
@@ -480,8 +480,8 @@ body: |
; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_AND {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s16)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_and_s32
@@ -497,15 +497,15 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_AND %0, %1
; G_AND with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -525,11 +525,11 @@ registers:
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s8) = G_LOAD %0 :: (load 1)
- %2(p0) = COPY %r0
+ %2(p0) = COPY $r0
%3(s8) = G_LOAD %2 :: (load 1)
%4(s8) = G_OR %1, %3
; G_OR with s8 should widen
@@ -537,8 +537,8 @@ body: |
; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_OR {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s8)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_or_s16
@@ -557,11 +557,11 @@ registers:
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s16) = G_LOAD %0 :: (load 2)
- %2(p0) = COPY %r0
+ %2(p0) = COPY $r0
%3(s16) = G_LOAD %2 :: (load 2)
%4(s16) = G_OR %1, %3
; G_OR with s16 should widen
@@ -569,8 +569,8 @@ body: |
; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_OR {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s16)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_or_s32
@@ -586,15 +586,15 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_OR %0, %1
; G_OR with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -614,11 +614,11 @@ registers:
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s8) = G_LOAD %0 :: (load 1)
- %2(p0) = COPY %r0
+ %2(p0) = COPY $r0
%3(s8) = G_LOAD %2 :: (load 1)
%4(s8) = G_XOR %1, %3
; G_XOR with s8 should widen
@@ -626,8 +626,8 @@ body: |
; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_XOR {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s8)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_xor_s16
@@ -646,11 +646,11 @@ registers:
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s16) = G_LOAD %0 :: (load 2)
- %2(p0) = COPY %r0
+ %2(p0) = COPY $r0
%3(s16) = G_LOAD %2 :: (load 2)
%4(s16) = G_XOR %1, %3
; G_XOR with s16 should widen
@@ -658,8 +658,8 @@ body: |
; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_XOR {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s16)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_xor_s32
@@ -675,15 +675,15 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_XOR %0, %1
; G_XOR with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -700,15 +700,15 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_LSHR %0, %1
; G_LSHR with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_LSHR {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -725,15 +725,15 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_ASHR %0, %1
; G_ASHR with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_ASHR {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -750,15 +750,15 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_SHL %0, %1
; G_SHL with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}}
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -781,15 +781,15 @@ fixedStack:
# CHECK: id: [[FRAME_INDEX:[0-9]+]], type: default, offset: 8
body: |
bb.0:
- liveins: %r0, %r1, %r2, %r3
+ liveins: $r0, $r1, $r2, $r3
; This is legal, so we should find it unchanged in the output
; CHECK: [[FIVREG:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FRAME_INDEX]]
; CHECK: {{%[0-9]+}}:_(s32) = G_LOAD [[FIVREG]](p0) :: (load 4)
%0(p0) = G_FRAME_INDEX %fixed-stack.2
%1(s32) = G_LOAD %0(p0) :: (load 4)
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_legal_loads_stores
@@ -809,7 +809,7 @@ registers:
- { id: 6, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
; These are all legal, so we should find them unchanged in the output
; CHECK-DAG: G_STORE {{%[0-9]+}}(s64), %0(p0)
@@ -824,7 +824,7 @@ body: |
; CHECK-DAG: {{%[0-9]+}}:_(s8) = G_LOAD %0(p0)
; CHECK-DAG: {{%[0-9]+}}:_(s1) = G_LOAD %0(p0)
; CHECK-DAG: {{%[0-9]+}}:_(p0) = G_LOAD %0(p0)
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s64) = G_LOAD %0(p0) :: (load 8)
G_STORE %1(s64), %0(p0) :: (store 8)
%2(s32) = G_LOAD %0(p0) :: (load 4)
@@ -837,7 +837,7 @@ body: |
G_STORE %5(s1), %0(p0) :: (store 1)
%6(p0) = G_LOAD %0(p0) :: (load 4)
G_STORE %6(p0), %0(p0) :: (store 4)
- BX_RET 14, %noreg
+ BX_RET 14, $noreg
...
---
name: test_gep
@@ -853,16 +853,16 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
- %1(s32) = COPY %r1
+ %0(p0) = COPY $r0
+ %1(s32) = COPY $r1
; CHECK: {{%[0-9]+}}:_(p0) = G_GEP {{%[0-9]+}}, {{%[0-9]+}}(s32)
%2(p0) = G_GEP %0, %1(s32)
- %r0 = COPY %2(p0)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(p0)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_constants
@@ -884,9 +884,9 @@ registers:
- { id: 8, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %4(p0) = COPY %r0
+ %4(p0) = COPY $r0
%0(s32) = G_CONSTANT 42
; CHECK: {{%[0-9]+}}:_(s32) = G_CONSTANT 42
@@ -924,8 +924,8 @@ body: |
; CHECK-DAG: {{%[0-9]+}}:_(s32) = G_CONSTANT i32 16
; CHECK-NOT: G_CONSTANT i64
- %r0 = COPY %0(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %0(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_s8
@@ -944,19 +944,19 @@ registers:
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s8) = G_LOAD %0 :: (load 1)
- %2(p0) = COPY %r1
+ %2(p0) = COPY $r1
%3(s8) = G_LOAD %2 :: (load 1)
%4(s1) = G_ICMP intpred(ne), %1(s8), %3
; G_ICMP with s8 should widen
; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s32), {{%[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s8), {{%[0-9]+}}
%5(s32) = G_ZEXT %4(s1)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_s16
@@ -975,19 +975,19 @@ registers:
- { id: 5, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s16) = G_LOAD %0 :: (load 2)
- %2(p0) = COPY %r1
+ %2(p0) = COPY $r1
%3(s16) = G_LOAD %2 :: (load 2)
%4(s1) = G_ICMP intpred(slt), %1(s16), %3
; G_ICMP with s16 should widen
; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s32), {{%[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s16), {{%[0-9]+}}
%5(s32) = G_ZEXT %4(s1)
- %r0 = COPY %5(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_icmp_s32
@@ -1004,16 +1004,16 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(eq), %0(s32), %1
; G_ICMP with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(eq), {{%[0-9]+}}(s32), {{%[0-9]+}}
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_select_s32
@@ -1030,16 +1030,16 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_CONSTANT i1 1
%3(s32) = G_SELECT %2(s1), %0, %1
; G_SELECT with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_SELECT {{%[0-9]+}}(s1), {{%[0-9]+}}, {{%[0-9]+}}
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_select_ptr
@@ -1056,16 +1056,16 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(p0) = COPY %r0
- %1(p0) = COPY %r1
+ %0(p0) = COPY $r0
+ %1(p0) = COPY $r1
%2(s1) = G_CONSTANT i1 0
%3(p0) = G_SELECT %2(s1), %0, %1
; G_SELECT with p0 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(p0) = G_SELECT {{%[0-9]+}}(s1), {{%[0-9]+}}, {{%[0-9]+}}
- %r0 = COPY %3(p0)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(p0)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_brcond
@@ -1082,10 +1082,10 @@ registers:
body: |
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(sgt), %0(s32), %1
G_BRCOND %2(s1), %bb.1
; G_BRCOND with s1 is legal, so we should find it unchanged in the output
@@ -1093,12 +1093,12 @@ body: |
G_BR %bb.2
bb.1:
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
bb.2:
- %r0 = COPY %0(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %0(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -1117,13 +1117,13 @@ registers:
- { id: 4, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
- %2(s32) = COPY %r1
- %3(s32) = COPY %r2
+ %2(s32) = COPY $r1
+ %3(s32) = COPY $r2
G_BRCOND %1(s1), %bb.1
G_BR %bb.2
@@ -1135,8 +1135,8 @@ body: |
%4(s32) = G_PHI %2(s32), %bb.0, %3(s32), %bb.1
; G_PHI with s32 is legal, so we should find it unchanged in the output
; CHECK: G_PHI {{%[0-9]+}}(s32), %bb.0, {{%[0-9]+}}(s32), %bb.1
- %r0 = COPY %4(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %4(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_phi_p0
@@ -1154,13 +1154,13 @@ registers:
- { id: 4, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
- %2(p0) = COPY %r1
- %3(p0) = COPY %r2
+ %2(p0) = COPY $r1
+ %3(p0) = COPY $r2
G_BRCOND %1(s1), %bb.1
G_BR %bb.2
@@ -1172,8 +1172,8 @@ body: |
%4(p0) = G_PHI %2(p0), %bb.0, %3(p0), %bb.1
; G_PHI with p0 is legal, so we should find it unchanged in the output
; CHECK: G_PHI {{%[0-9]+}}(p0), %bb.0, {{%[0-9]+}}(p0), %bb.1
- %r0 = COPY %4(p0)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %4(p0)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_phi_s64
@@ -1191,13 +1191,13 @@ registers:
- { id: 4, class: _ }
body: |
bb.0:
- liveins: %r0, %d0, %d1
+ liveins: $r0, $d0, $d1
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
- %2(s64) = COPY %d0
- %3(s64) = COPY %d1
+ %2(s64) = COPY $d0
+ %3(s64) = COPY $d1
G_BRCOND %1(s1), %bb.1
G_BR %bb.2
@@ -1210,8 +1210,8 @@ body: |
; G_PHI with s64 is legal when we have floating point support, so we should
; find it unchanged in the output
; CHECK: G_PHI {{%[0-9]+}}(s64), %bb.0, {{%[0-9]+}}(s64), %bb.1
- %d0 = COPY %4(s64)
- BX_RET 14, %noreg, implicit %d0
+ $d0 = COPY %4(s64)
+ BX_RET 14, $noreg, implicit $d0
...
---
name: test_phi_s8
@@ -1232,18 +1232,18 @@ registers:
- { id: 7, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
- %2(s32) = COPY %r1
+ %2(s32) = COPY $r1
%3(s8) = G_TRUNC %2(s32)
- ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+ ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
- %4(s32) = COPY %r2
+ %4(s32) = COPY $r2
%5(s8) = G_TRUNC %4(s32)
- ; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %r2
+ ; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $r2
; CHECK: [[V1:%[0-9]+]]:_(s32) = COPY [[R1]]
@@ -1261,10 +1261,10 @@ body: |
; CHECK: [[V:%[0-9]+]]:_(s32) = G_PHI [[V1]](s32), %bb.0, [[V2]](s32), %bb.1
%7(s32) = G_ANYEXT %6(s8)
- %r0 = COPY %7(s32)
+ $r0 = COPY %7(s32)
; CHECK: [[R:%[0-9]+]]:_(s32) = COPY [[V]]
- ; CHECK: %r0 = COPY [[R]](s32)
- BX_RET 14, %noreg, implicit %r0
+ ; CHECK: $r0 = COPY [[R]](s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_global_variable
@@ -1279,13 +1279,13 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(p0) = G_GLOBAL_VALUE @a_global
; G_GLOBAL_VALUE is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(p0) = G_GLOBAL_VALUE @a_global
- %r0 = COPY %1(p0)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %1(p0)
+ BX_RET 14, $noreg, implicit $r0
...
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll Wed Jan 31 14:04:26 2018
@@ -6,16 +6,16 @@ declare arm_aapcscc i32* @simple_reg_par
define arm_aapcscc i32* @test_call_simple_reg_params(i32 *%a, i32 %b) {
; CHECK-LABEL: name: test_call_simple_reg_params
-; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY %r0
-; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK-DAG: %r0 = COPY [[BVREG]]
-; CHECK-DAG: %r1 = COPY [[AVREG]]
-; CHECK: BL @simple_reg_params_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0
-; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY %r0
-; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: %r0 = COPY [[RVREG]]
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY $r0
+; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r1
+; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK-DAG: $r0 = COPY [[BVREG]]
+; CHECK-DAG: $r1 = COPY [[AVREG]]
+; CHECK: BL @simple_reg_params_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0
+; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY $r0
+; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK: $r0 = COPY [[RVREG]]
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%r = notail call arm_aapcscc i32 *@simple_reg_params_target(i32 %b, i32 *%a)
ret i32 *%r
@@ -25,26 +25,26 @@ declare arm_aapcscc i32* @simple_stack_p
define arm_aapcscc i32* @test_call_simple_stack_params(i32 *%a, i32 %b) {
; CHECK-LABEL: name: test_call_simple_stack_params
-; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY %r0
-; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK: ADJCALLSTACKDOWN 8, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK-DAG: %r0 = COPY [[BVREG]]
-; CHECK-DAG: %r1 = COPY [[AVREG]]
-; CHECK-DAG: %r2 = COPY [[BVREG]]
-; CHECK-DAG: %r3 = COPY [[AVREG]]
-; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY $r0
+; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r1
+; CHECK: ADJCALLSTACKDOWN 8, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK-DAG: $r0 = COPY [[BVREG]]
+; CHECK-DAG: $r1 = COPY [[AVREG]]
+; CHECK-DAG: $r2 = COPY [[BVREG]]
+; CHECK-DAG: $r3 = COPY [[AVREG]]
+; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_GEP [[SP1]], [[OFF1]](s32)
; CHECK: G_STORE [[BVREG]](s32), [[FI1]](p0){{.*}}store 4
-; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_GEP [[SP2]], [[OFF2]](s32)
; CHECK: G_STORE [[AVREG]](p0), [[FI2]](p0){{.*}}store 4
-; CHECK: BL @simple_stack_params_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
-; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY %r0
-; CHECK: ADJCALLSTACKUP 8, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: %r0 = COPY [[RVREG]]
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: BL @simple_stack_params_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY $r0
+; CHECK: ADJCALLSTACKUP 8, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK: $r0 = COPY [[RVREG]]
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%r = notail call arm_aapcscc i32 *@simple_stack_params_target(i32 %b, i32 *%a, i32 %b, i32 *%a, i32 %b, i32 *%a)
ret i32 *%r
@@ -54,53 +54,53 @@ declare arm_aapcscc signext i16 @ext_tar
define arm_aapcscc signext i16 @test_call_ext_params(i8 %a, i16 %b, i1 %c) {
; CHECK-LABEL: name: test_call_ext_params
-; CHECK-DAG: [[R0VREG:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK-DAG: [[R0VREG:%[0-9]+]]:_(s32) = COPY $r0
; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s8) = G_TRUNC [[R0VREG]]
-; CHECK-DAG: [[R1VREG:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: [[R1VREG:%[0-9]+]]:_(s32) = COPY $r1
; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R1VREG]]
-; CHECK-DAG: [[R2VREG:%[0-9]+]]:_(s32) = COPY %r2
+; CHECK-DAG: [[R2VREG:%[0-9]+]]:_(s32) = COPY $r2
; CHECK-DAG: [[CVREG:%[0-9]+]]:_(s1) = G_TRUNC [[R2VREG]]
-; CHECK: ADJCALLSTACKDOWN 20, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 20, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[SEXTA:%[0-9]+]]:_(s32) = G_SEXT [[AVREG]](s8)
-; CHECK: %r0 = COPY [[SEXTA]]
+; CHECK: $r0 = COPY [[SEXTA]]
; CHECK: [[ZEXTA:%[0-9]+]]:_(s32) = G_ZEXT [[AVREG]](s8)
-; CHECK: %r1 = COPY [[ZEXTA]]
+; CHECK: $r1 = COPY [[ZEXTA]]
; CHECK: [[SEXTB:%[0-9]+]]:_(s32) = G_SEXT [[BVREG]](s16)
-; CHECK: %r2 = COPY [[SEXTB]]
+; CHECK: $r2 = COPY [[SEXTB]]
; CHECK: [[ZEXTB:%[0-9]+]]:_(s32) = G_ZEXT [[BVREG]](s16)
-; CHECK: %r3 = COPY [[ZEXTB]]
-; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: $r3 = COPY [[ZEXTB]]
+; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_GEP [[SP1]], [[OFF1]](s32)
; CHECK: [[SEXTA2:%[0-9]+]]:_(s32) = G_SEXT [[AVREG]]
; CHECK: G_STORE [[SEXTA2]](s32), [[FI1]](p0){{.*}}store 4
-; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_GEP [[SP2]], [[OFF2]](s32)
; CHECK: [[ZEXTA2:%[0-9]+]]:_(s32) = G_ZEXT [[AVREG]]
; CHECK: G_STORE [[ZEXTA2]](s32), [[FI2]](p0){{.*}}store 4
-; CHECK: [[SP3:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[SP3:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[FI3:%[0-9]+]]:_(p0) = G_GEP [[SP3]], [[OFF3]](s32)
; CHECK: [[SEXTB2:%[0-9]+]]:_(s32) = G_SEXT [[BVREG]]
; CHECK: G_STORE [[SEXTB2]](s32), [[FI3]](p0){{.*}}store 4
-; CHECK: [[SP4:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[SP4:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF4:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[FI4:%[0-9]+]]:_(p0) = G_GEP [[SP4]], [[OFF4]](s32)
; CHECK: [[ZEXTB2:%[0-9]+]]:_(s32) = G_ZEXT [[BVREG]]
; CHECK: G_STORE [[ZEXTB2]](s32), [[FI4]](p0){{.*}}store 4
-; CHECK: [[SP5:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[SP5:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[FI5:%[0-9]+]]:_(p0) = G_GEP [[SP5]], [[OFF5]](s32)
; CHECK: [[ZEXTC:%[0-9]+]]:_(s32) = G_ZEXT [[CVREG]]
; CHECK: G_STORE [[ZEXTC]](s32), [[FI5]](p0){{.*}}store 4
-; CHECK: BL @ext_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
-; CHECK: [[R0VREG:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: BL @ext_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
+; CHECK: [[R0VREG:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: [[RVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R0VREG]]
-; CHECK: ADJCALLSTACKUP 20, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 20, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[RExtVREG:%[0-9]+]]:_(s32) = G_SEXT [[RVREG]]
-; CHECK: %r0 = COPY [[RExtVREG]]
-; CHECK: BX_RET 14, %noreg, implicit %r0
+; CHECK: $r0 = COPY [[RExtVREG]]
+; CHECK: BX_RET 14, $noreg, implicit $r0
entry:
%r = notail call arm_aapcscc signext i16 @ext_target(i8 signext %a, i8 zeroext %a, i16 signext %b, i16 zeroext %b, i8 signext %a, i8 zeroext %a, i16 signext %b, i16 zeroext %b, i1 zeroext %c)
ret i16 %r
@@ -110,16 +110,16 @@ declare arm_aapcs_vfpcc double @vfpcc_fp
define arm_aapcs_vfpcc double @test_call_vfpcc_fp_params(double %a, float %b) {
; CHECK-LABEL: name: test_call_vfpcc_fp_params
-; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s64) = COPY %d0
-; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %s2
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK-DAG: %s0 = COPY [[BVREG]]
-; CHECK-DAG: %d1 = COPY [[AVREG]]
-; CHECK: BL @vfpcc_fp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %d1, implicit-def %d0
-; CHECK: [[RVREG:%[0-9]+]]:_(s64) = COPY %d0
-; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: %d0 = COPY [[RVREG]]
-; CHECK: BX_RET 14, %noreg, implicit %d0
+; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s64) = COPY $d0
+; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $s2
+; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK-DAG: $s0 = COPY [[BVREG]]
+; CHECK-DAG: $d1 = COPY [[AVREG]]
+; CHECK: BL @vfpcc_fp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $d1, implicit-def $d0
+; CHECK: [[RVREG:%[0-9]+]]:_(s64) = COPY $d0
+; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK: $d0 = COPY [[RVREG]]
+; CHECK: BX_RET 14, $noreg, implicit $d0
entry:
%r = notail call arm_aapcs_vfpcc double @vfpcc_fp_target(float %b, double %a)
ret double %r
@@ -129,38 +129,38 @@ declare arm_aapcscc double @aapcscc_fp_t
define arm_aapcscc double @test_call_aapcs_fp_params(double %a, float %b) {
; CHECK-LABEL: name: test_call_aapcs_fp_params
-; CHECK-DAG: [[A1:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK-DAG: [[A2:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: [[A1:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK-DAG: [[A2:%[0-9]+]]:_(s32) = COPY $r1
; LITTLE-DAG: [[AVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A1]](s32), [[A2]](s32)
; BIG-DAG: [[AVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A2]](s32), [[A1]](s32)
-; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %r2
-; CHECK: ADJCALLSTACKDOWN 16, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK-DAG: %r0 = COPY [[BVREG]]
+; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r2
+; CHECK: ADJCALLSTACKDOWN 16, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK-DAG: $r0 = COPY [[BVREG]]
; CHECK-DAG: [[A1:%[0-9]+]]:_(s32), [[A2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AVREG]](s64)
-; LITTLE-DAG: %r2 = COPY [[A1]]
-; LITTLE-DAG: %r3 = COPY [[A2]]
-; BIG-DAG: %r2 = COPY [[A2]]
-; BIG-DAG: %r3 = COPY [[A1]]
-; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY %sp
+; LITTLE-DAG: $r2 = COPY [[A1]]
+; LITTLE-DAG: $r3 = COPY [[A2]]
+; BIG-DAG: $r2 = COPY [[A2]]
+; BIG-DAG: $r3 = COPY [[A1]]
+; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_GEP [[SP1]], [[OFF1]](s32)
; CHECK: G_STORE [[BVREG]](s32), [[FI1]](p0){{.*}}store 4
-; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_GEP [[SP2]], [[OFF2]](s32)
; CHECK: G_STORE [[AVREG]](s64), [[FI2]](p0){{.*}}store 8
-; CHECK: BL @aapcscc_fp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
-; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: BL @aapcscc_fp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
+; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY $r1
; LITTLE: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R1]](s32), [[R2]](s32)
; BIG: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R2]](s32), [[R1]](s32)
-; CHECK: ADJCALLSTACKUP 16, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 16, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RVREG]](s64)
-; LITTLE-DAG: %r0 = COPY [[R1]]
-; LITTLE-DAG: %r1 = COPY [[R2]]
-; BIG-DAG: %r0 = COPY [[R2]]
-; BIG-DAG: %r1 = COPY [[R1]]
-; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
+; LITTLE-DAG: $r0 = COPY [[R1]]
+; LITTLE-DAG: $r1 = COPY [[R2]]
+; BIG-DAG: $r0 = COPY [[R2]]
+; BIG-DAG: $r1 = COPY [[R1]]
+; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1
entry:
%r = notail call arm_aapcscc double @aapcscc_fp_target(float %b, double %a, float %b, double %a)
ret double %r
@@ -170,14 +170,14 @@ declare arm_aapcscc float @different_cal
define arm_aapcs_vfpcc float @test_call_different_call_conv(float %x) {
; CHECK-LABEL: name: test_call_different_call_conv
-; CHECK: [[X:%[0-9]+]]:_(s32) = COPY %s0
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: %r0 = COPY [[X]]
-; CHECK: BL @different_call_conv_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit-def %r0
-; CHECK: [[R:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: %s0 = COPY [[R]]
-; CHECK: BX_RET 14, %noreg, implicit %s0
+; CHECK: [[X:%[0-9]+]]:_(s32) = COPY $s0
+; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK: $r0 = COPY [[X]]
+; CHECK: BL @different_call_conv_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit-def $r0
+; CHECK: [[R:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK: $s0 = COPY [[R]]
+; CHECK: BX_RET 14, $noreg, implicit $s0
entry:
%r = notail call arm_aapcscc float @different_call_conv_target(float %x)
ret float %r
@@ -187,28 +187,28 @@ declare arm_aapcscc [3 x i32] @tiny_int_
define arm_aapcscc [3 x i32] @test_tiny_int_arrays([2 x i32] %arr) {
; CHECK-LABEL: name: test_tiny_int_arrays
-; CHECK: liveins: %r0, %r1
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: liveins: $r0, $r1
+; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[ARG_ARR:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s64)
-; CHECK: %r0 = COPY [[R0]]
-; CHECK: %r1 = COPY [[R1]]
-; CHECK: BL @tiny_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %r2
+; CHECK: $r0 = COPY [[R0]]
+; CHECK: $r1 = COPY [[R1]]
+; CHECK: BL @tiny_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
+; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
+; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $r2
; CHECK: [[RES_ARR:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32)
-; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RES_ARR]](s96)
; FIXME: This doesn't seem correct with regard to the AAPCS docs (which say
; that composite types larger than 4 bytes should be passed through memory),
; but it's what DAGISel does. We should fix it in the common code for both.
-; CHECK: %r0 = COPY [[R0]]
-; CHECK: %r1 = COPY [[R1]]
-; CHECK: %r2 = COPY [[R2]]
-; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1, implicit %r2
+; CHECK: $r0 = COPY [[R0]]
+; CHECK: $r1 = COPY [[R1]]
+; CHECK: $r2 = COPY [[R2]]
+; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1, implicit $r2
entry:
%r = notail call arm_aapcscc [3 x i32] @tiny_int_arrays_target([2 x i32] %arr)
ret [3 x i32] %r
@@ -218,23 +218,23 @@ declare arm_aapcscc void @multiple_int_a
define arm_aapcscc void @test_multiple_int_arrays([2 x i32] %arr0, [2 x i32] %arr1) {
; CHECK-LABEL: name: test_multiple_int_arrays
-; CHECK: liveins: %r0, %r1
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %r2
-; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY %r3
+; CHECK: liveins: $r0, $r1
+; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
+; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $r2
+; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY $r3
; CHECK: [[ARG_ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
; CHECK: [[ARG_ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R2]](s32), [[R3]](s32)
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR0]](s64)
; CHECK: [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR1]](s64)
-; CHECK: %r0 = COPY [[R0]]
-; CHECK: %r1 = COPY [[R1]]
-; CHECK: %r2 = COPY [[R2]]
-; CHECK: %r3 = COPY [[R3]]
-; CHECK: BL @multiple_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3
-; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: BX_RET 14, %noreg
+; CHECK: $r0 = COPY [[R0]]
+; CHECK: $r1 = COPY [[R1]]
+; CHECK: $r2 = COPY [[R2]]
+; CHECK: $r3 = COPY [[R3]]
+; CHECK: BL @multiple_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3
+; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK: BX_RET 14, $noreg
entry:
notail call arm_aapcscc void @multiple_int_arrays_target([2 x i32] %arr0, [2 x i32] %arr1)
ret void
@@ -249,35 +249,35 @@ define arm_aapcscc void @test_large_int_
; doesn't fit in the registers.
; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], type: default, offset: 0, size: 4,
; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], type: default, offset: 60, size: 4
-; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY %r2
-; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY %r3
+; CHECK: liveins: $r0, $r1, $r2, $r3
+; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
+; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY $r2
+; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY $r3
; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]]
; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]]
; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]]
; CHECK: [[ARG_ARR:%[0-9]+]]:_(s640) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32), [[FIRST_STACK_ELEMENT]](s32), {{.*}}, [[LAST_STACK_ELEMENT]](s32)
-; CHECK: ADJCALLSTACKDOWN 64, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 64, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32), [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s640)
-; CHECK: %r0 = COPY [[R0]]
-; CHECK: %r1 = COPY [[R1]]
-; CHECK: %r2 = COPY [[R2]]
-; CHECK: %r3 = COPY [[R3]]
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: $r0 = COPY [[R0]]
+; CHECK: $r1 = COPY [[R1]]
+; CHECK: $r2 = COPY [[R2]]
+; CHECK: $r3 = COPY [[R3]]
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_FIRST_ELEMENT]](s32)
; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](s32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store 4
; Match the second-to-last offset, so we can get the correct SP for the last element
; CHECK: G_CONSTANT i32 56
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 60
; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_LAST_ELEMENT]](s32)
; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4
-; CHECK: BL @large_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3
-; CHECK: ADJCALLSTACKUP 64, 0, 14, %noreg, implicit-def %sp, implicit %sp
-; CHECK: BX_RET 14, %noreg
+; CHECK: BL @large_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3
+; CHECK: ADJCALLSTACKUP 64, 0, 14, $noreg, implicit-def $sp, implicit $sp
+; CHECK: BX_RET 14, $noreg
entry:
notail call arm_aapcscc void @large_int_arrays_target([20 x i32] %arr)
ret void
@@ -289,43 +289,43 @@ define arm_aapcscc [2 x float] @test_fp_
; CHECK-LABEL: name: test_fp_arrays_aapcs
; CHECK: fixedStack:
; CHECK: id: [[ARR2_ID:[0-9]+]], type: default, offset: 0, size: 8,
-; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK: [[ARR0_0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[ARR0_1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: liveins: $r0, $r1, $r2, $r3
+; CHECK: [[ARR0_0:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[ARR0_1:%[0-9]+]]:_(s32) = COPY $r1
; LITTLE: [[ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR0_0]](s32), [[ARR0_1]](s32)
; BIG: [[ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR0_1]](s32), [[ARR0_0]](s32)
-; CHECK: [[ARR1_0:%[0-9]+]]:_(s32) = COPY %r2
-; CHECK: [[ARR1_1:%[0-9]+]]:_(s32) = COPY %r3
+; CHECK: [[ARR1_0:%[0-9]+]]:_(s32) = COPY $r2
+; CHECK: [[ARR1_1:%[0-9]+]]:_(s32) = COPY $r3
; LITTLE: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_0]](s32), [[ARR1_1]](s32)
; BIG: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_1]](s32), [[ARR1_0]](s32)
; CHECK: [[ARR2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[ARR2_ID]]
; CHECK: [[ARR2:%[0-9]+]]:_(s64) = G_LOAD [[ARR2_FI]]{{.*}}load 8 from %fixed-stack.[[ARR2_ID]]
; CHECK: [[ARR_MERGED:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[ARR0]](s64), [[ARR1]](s64), [[ARR2]](s64)
-; CHECK: ADJCALLSTACKDOWN 8, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 8, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[ARR0:%[0-9]+]]:_(s64), [[ARR1:%[0-9]+]]:_(s64), [[ARR2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ARR_MERGED]](s192)
; CHECK: [[ARR0_0:%[0-9]+]]:_(s32), [[ARR0_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR0]](s64)
-; LITTLE: %r0 = COPY [[ARR0_0]](s32)
-; LITTLE: %r1 = COPY [[ARR0_1]](s32)
-; BIG: %r0 = COPY [[ARR0_1]](s32)
-; BIG: %r1 = COPY [[ARR0_0]](s32)
+; LITTLE: $r0 = COPY [[ARR0_0]](s32)
+; LITTLE: $r1 = COPY [[ARR0_1]](s32)
+; BIG: $r0 = COPY [[ARR0_1]](s32)
+; BIG: $r1 = COPY [[ARR0_0]](s32)
; CHECK: [[ARR1_0:%[0-9]+]]:_(s32), [[ARR1_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR1]](s64)
-; LITTLE: %r2 = COPY [[ARR1_0]](s32)
-; LITTLE: %r3 = COPY [[ARR1_1]](s32)
-; BIG: %r2 = COPY [[ARR1_1]](s32)
-; BIG: %r3 = COPY [[ARR1_0]](s32)
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; LITTLE: $r2 = COPY [[ARR1_0]](s32)
+; LITTLE: $r3 = COPY [[ARR1_1]](s32)
+; BIG: $r2 = COPY [[ARR1_1]](s32)
+; BIG: $r3 = COPY [[ARR1_0]](s32)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[ARR2_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ARR2_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[ARR2_OFFSET]](s32)
; CHECK: G_STORE [[ARR2]](s64), [[ARR2_ADDR]](p0){{.*}}store 8
-; CHECK: BL @fp_arrays_aapcs_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: BL @fp_arrays_aapcs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
+; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[R_MERGED:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
-; CHECK: ADJCALLSTACKUP 8, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 8, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R_MERGED]](s64)
-; CHECK: %r0 = COPY [[R0]]
-; CHECK: %r1 = COPY [[R1]]
-; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
+; CHECK: $r0 = COPY [[R0]]
+; CHECK: $r1 = COPY [[R1]]
+; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1
entry:
%r = notail call arm_aapcscc [2 x float] @fp_arrays_aapcs_target([3 x double] %arr)
ret [2 x float] %r
@@ -340,13 +340,13 @@ define arm_aapcs_vfpcc [4 x float] @test
; CHECK-DAG: id: [[Z1_ID:[0-9]+]], type: default, offset: 8, size: 8,
; CHECK-DAG: id: [[Z2_ID:[0-9]+]], type: default, offset: 16, size: 8,
; CHECK-DAG: id: [[Z3_ID:[0-9]+]], type: default, offset: 24, size: 8,
-; CHECK: liveins: %d0, %d1, %d2, %s6, %s7, %s8
-; CHECK: [[X0:%[0-9]+]]:_(s64) = COPY %d0
-; CHECK: [[X1:%[0-9]+]]:_(s64) = COPY %d1
-; CHECK: [[X2:%[0-9]+]]:_(s64) = COPY %d2
-; CHECK: [[Y0:%[0-9]+]]:_(s32) = COPY %s6
-; CHECK: [[Y1:%[0-9]+]]:_(s32) = COPY %s7
-; CHECK: [[Y2:%[0-9]+]]:_(s32) = COPY %s8
+; CHECK: liveins: $d0, $d1, $d2, $s6, $s7, $s8
+; CHECK: [[X0:%[0-9]+]]:_(s64) = COPY $d0
+; CHECK: [[X1:%[0-9]+]]:_(s64) = COPY $d1
+; CHECK: [[X2:%[0-9]+]]:_(s64) = COPY $d2
+; CHECK: [[Y0:%[0-9]+]]:_(s32) = COPY $s6
+; CHECK: [[Y1:%[0-9]+]]:_(s32) = COPY $s7
+; CHECK: [[Y2:%[0-9]+]]:_(s32) = COPY $s8
; CHECK: [[Z0_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z0_ID]]
; CHECK: [[Z0:%[0-9]+]]:_(s64) = G_LOAD [[Z0_FI]]{{.*}}load 8
; CHECK: [[Z1_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z1_ID]]
@@ -358,45 +358,45 @@ define arm_aapcs_vfpcc [4 x float] @test
; CHECK: [[X_ARR:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[X0]](s64), [[X1]](s64), [[X2]](s64)
; CHECK: [[Y_ARR:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32), [[Y2]](s32)
; CHECK: [[Z_ARR:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[Z0]](s64), [[Z1]](s64), [[Z2]](s64), [[Z3]](s64)
-; CHECK: ADJCALLSTACKDOWN 32, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 32, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[X0:%[0-9]+]]:_(s64), [[X1:%[0-9]+]]:_(s64), [[X2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[X_ARR]](s192)
; CHECK: [[Y0:%[0-9]+]]:_(s32), [[Y1:%[0-9]+]]:_(s32), [[Y2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[Y_ARR]](s96)
; CHECK: [[Z0:%[0-9]+]]:_(s64), [[Z1:%[0-9]+]]:_(s64), [[Z2:%[0-9]+]]:_(s64), [[Z3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[Z_ARR]](s256)
-; CHECK: %d0 = COPY [[X0]](s64)
-; CHECK: %d1 = COPY [[X1]](s64)
-; CHECK: %d2 = COPY [[X2]](s64)
-; CHECK: %s6 = COPY [[Y0]](s32)
-; CHECK: %s7 = COPY [[Y1]](s32)
-; CHECK: %s8 = COPY [[Y2]](s32)
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: $d0 = COPY [[X0]](s64)
+; CHECK: $d1 = COPY [[X1]](s64)
+; CHECK: $d2 = COPY [[X2]](s64)
+; CHECK: $s6 = COPY [[Y0]](s32)
+; CHECK: $s7 = COPY [[Y1]](s32)
+; CHECK: $s8 = COPY [[Y2]](s32)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[Z0_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[Z0_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[Z0_OFFSET]](s32)
; CHECK: G_STORE [[Z0]](s64), [[Z0_ADDR]](p0){{.*}}store 8
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[Z1_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[Z1_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[Z1_OFFSET]](s32)
; CHECK: G_STORE [[Z1]](s64), [[Z1_ADDR]](p0){{.*}}store 8
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[Z2_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[Z2_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[Z2_OFFSET]](s32)
; CHECK: G_STORE [[Z2]](s64), [[Z2_ADDR]](p0){{.*}}store 8
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[Z3_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[Z3_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[Z3_OFFSET]](s32)
; CHECK: G_STORE [[Z3]](s64), [[Z3_ADDR]](p0){{.*}}store 8
-; CHECK: BL @fp_arrays_aapcs_vfp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit %d2, implicit %s6, implicit %s7, implicit %s8, implicit-def %s0, implicit-def %s1, implicit-def %s2, implicit-def %s3
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %s0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %s1
-; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %s2
-; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY %s3
+; CHECK: BL @fp_arrays_aapcs_vfp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit $d2, implicit $s6, implicit $s7, implicit $s8, implicit-def $s0, implicit-def $s1, implicit-def $s2, implicit-def $s3
+; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $s0
+; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $s1
+; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $s2
+; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY $s3
; CHECK: [[R_MERGED:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32)
-; CHECK: ADJCALLSTACKUP 32, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 32, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R_MERGED]](s128)
-; CHECK: %s0 = COPY [[R0]]
-; CHECK: %s1 = COPY [[R1]]
-; CHECK: %s2 = COPY [[R2]]
-; CHECK: %s3 = COPY [[R3]]
-; CHECK: BX_RET 14, %noreg, implicit %s0, implicit %s1, implicit %s2, implicit %s3
+; CHECK: $s0 = COPY [[R0]]
+; CHECK: $s1 = COPY [[R1]]
+; CHECK: $s2 = COPY [[R2]]
+; CHECK: $s3 = COPY [[R3]]
+; CHECK: BX_RET 14, $noreg, implicit $s0, implicit $s1, implicit $s2, implicit $s3
entry:
%r = notail call arm_aapcs_vfpcc [4 x float] @fp_arrays_aapcs_vfp_target([3 x double] %x, [3 x float] %y, [4 x double] %z)
ret [4 x float] %r
@@ -411,41 +411,41 @@ define arm_aapcscc [2 x i32*] @test_toug
; doesn't fit in the registers.
; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], type: default, offset: 0, size: 4,
; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], type: default, offset: 76, size: 4
-; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
-; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY %r2
-; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY %r3
+; CHECK: liveins: $r0, $r1, $r2, $r3
+; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r1
+; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY $r2
+; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY $r3
; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]]
; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]]
; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]]
; CHECK: [[ARG_ARR:%[0-9]+]]:_(s768) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32), [[FIRST_STACK_ELEMENT]](s32), {{.*}}, [[LAST_STACK_ELEMENT]](s32)
-; CHECK: ADJCALLSTACKDOWN 80, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 80, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32), [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s768)
-; CHECK: %r0 = COPY [[R0]]
-; CHECK: %r1 = COPY [[R1]]
-; CHECK: %r2 = COPY [[R2]]
-; CHECK: %r3 = COPY [[R3]]
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: $r0 = COPY [[R0]]
+; CHECK: $r1 = COPY [[R1]]
+; CHECK: $r2 = COPY [[R2]]
+; CHECK: $r3 = COPY [[R3]]
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_FIRST_ELEMENT]](s32)
; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](s32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store 4
; Match the second-to-last offset, so we can get the correct SP for the last element
; CHECK: G_CONSTANT i32 72
-; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 76
; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_LAST_ELEMENT]](s32)
; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4
-; CHECK: BL @tough_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: BL @tough_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1
+; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[RES_ARR:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
-; CHECK: ADJCALLSTACKUP 80, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 80, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RES_ARR]](s64)
-; CHECK: %r0 = COPY [[R0]]
-; CHECK: %r1 = COPY [[R1]]
-; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
+; CHECK: $r0 = COPY [[R0]]
+; CHECK: $r1 = COPY [[R1]]
+; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1
entry:
%r = notail call arm_aapcscc [2 x i32*] @tough_arrays_target([6 x [4 x i32]] %arr)
ret [2 x i32*] %r
@@ -455,23 +455,23 @@ declare arm_aapcscc {i32, i32} @structs_
define arm_aapcscc {i32, i32} @test_structs({i32, i32} %x) {
; CHECK-LABEL: test_structs
-; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: liveins: $r0, $r1
+; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
-; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[X0:%[0-9]+]]:_(s32), [[X1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[X]](s64)
-; CHECK-DAG: %r0 = COPY [[X0]](s32)
-; CHECK-DAG: %r1 = COPY [[X1]](s32)
-; CHECK: BL @structs_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1
-; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
-; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: $r0 = COPY [[X0]](s32)
+; CHECK-DAG: $r1 = COPY [[X1]](s32)
+; CHECK: BL @structs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1
+; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0
+; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1
; CHECK: [[R:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
-; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
+; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R]](s64)
-; CHECK: %r0 = COPY [[R0]](s32)
-; CHECK: %r1 = COPY [[R1]](s32)
-; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
+; CHECK: $r0 = COPY [[R0]](s32)
+; CHECK: $r1 = COPY [[R1]](s32)
+; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1
%r = notail call arm_aapcscc {i32, i32} @structs_target({i32, i32} %x)
ret {i32, i32} %r
}
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir Wed Jan 31 14:04:26 2018
@@ -101,13 +101,13 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_ADD %0, %1
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -127,13 +127,13 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_SUB %0, %1
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -153,13 +153,13 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_MUL %0, %1
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -179,13 +179,13 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_SDIV %0, %1
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -205,13 +205,13 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_UDIV %0, %1
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -231,13 +231,13 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_AND %0, %1
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -257,13 +257,13 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_OR %0, %1
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -283,13 +283,13 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_XOR %0, %1
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -309,13 +309,13 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_LSHR %0, %1
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -335,13 +335,13 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_ASHR %0, %1
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -361,13 +361,13 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s32) = G_SHL %0, %1
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -395,15 +395,15 @@ registers:
- { id: 6, class: _ }
body: |
bb.0:
- liveins: %r0
- %0(p0) = COPY %r0
+ liveins: $r0
+ %0(p0) = COPY $r0
%6(s64) = G_LOAD %0 :: (load 8)
%1(s32) = G_LOAD %0 :: (load 4)
%2(s16) = G_LOAD %0 :: (load 2)
%3(s8) = G_LOAD %0 :: (load 1)
%4(s1) = G_LOAD %0 :: (load 1)
%5(p0) = G_LOAD %0 :: (load 4)
- BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -431,9 +431,9 @@ registers:
- { id: 6, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r5, %d6
- %0(p0) = COPY %r0
- %1(s32) = COPY %r1
+ liveins: $r0, $r1, $r5, $d6
+ %0(p0) = COPY $r0
+ %1(s32) = COPY $r1
G_STORE %1(s32), %0 :: (store 4)
%2(s16) = G_TRUNC %1(s32)
G_STORE %2(s16), %0 :: (store 2)
@@ -441,11 +441,11 @@ body: |
G_STORE %3(s8), %0 :: (store 1)
%4(s1) = G_TRUNC %1(s32)
G_STORE %4(s1), %0 :: (store 1)
- %5(p0) = COPY %r5
+ %5(p0) = COPY $r5
G_STORE %5(p0), %0 :: (store 4)
- %6(s64) = COPY %d6
+ %6(s64) = COPY $d6
G_STORE %6(s64), %0 :: (store 8)
- BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -473,12 +473,12 @@ body: |
%0(p0) = G_FRAME_INDEX %fixed-stack.0
%1(s32) = G_LOAD %0(p0) :: (load 4 from %fixed-stack.0, align 0)
- %2(p0) = COPY %sp
+ %2(p0) = COPY $sp
%3(s32) = G_CONSTANT i32 8
%4(p0) = G_GEP %2, %3(s32)
G_STORE %1(s32), %4(p0) :: (store 4)
- BX_RET 14, %noreg
+ BX_RET 14, $noreg
...
---
@@ -498,13 +498,13 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(p0) = COPY %r0
- %1(s32) = COPY %r1
+ %0(p0) = COPY $r0
+ %1(s32) = COPY $r1
%2(p0) = G_GEP %0, %1(s32)
- %r0 = COPY %2(p0)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(p0)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_constants
@@ -519,8 +519,8 @@ registers:
body: |
bb.0:
%0(s32) = G_CONSTANT 42
- %r0 = COPY %0(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %0(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_inttoptr_s32
@@ -536,10 +536,10 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(p0) = G_INTTOPTR %0(s32)
- %r0 = COPY %1(p0)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %1(p0)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_ptrtoint_s32
@@ -555,10 +555,10 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
- %0(p0) = COPY %r0
+ %0(p0) = COPY $r0
%1(s32) = G_PTRTOINT %0(p0)
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_globals
@@ -573,8 +573,8 @@ registers:
body: |
bb.0:
%0(p0) = G_GLOBAL_VALUE @a_global
- %r0 = COPY %0(p0)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %0(p0)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_anyext_s8_32
@@ -592,13 +592,13 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32)
%2(s32) = G_ANYEXT %1(s8)
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_anyext_s16_32
@@ -616,13 +616,13 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32)
%2(s32) = G_ANYEXT %1(s16)
- %r0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_trunc_s32_16
@@ -640,13 +640,13 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %2(p0) = COPY %r1
+ %0(s32) = COPY $r0
+ %2(p0) = COPY $r1
%1(s16) = G_TRUNC %0(s32)
G_STORE %1(s16), %2 :: (store 2)
- BX_RET 14, %noreg
+ BX_RET 14, $noreg
...
---
name: test_trunc_s64_32
@@ -664,13 +664,13 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %r0, %d0
+ liveins: $r0, $d0
- %0(s64) = COPY %d0
- %2(p0) = COPY %r0
+ %0(s64) = COPY $d0
+ %2(p0) = COPY $r0
%1(s32) = G_TRUNC %0(s64)
G_STORE %1(s32), %2 :: (store 4)
- BX_RET 14, %noreg
+ BX_RET 14, $noreg
...
---
name: test_icmp_eq_s32
@@ -691,14 +691,14 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s1) = G_ICMP intpred(eq), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -720,14 +720,14 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s1) = G_FCMP floatpred(one), %0(s32), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -749,14 +749,14 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s1) = G_FCMP floatpred(ugt), %0(s64), %1
%3(s32) = G_ZEXT %2(s1)
- %r0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -780,15 +780,15 @@ registers:
- { id: 4, class: _ }
body: |
bb.0:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
- %2(s32) = COPY %r2
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s32) = COPY $r2
%3(s1) = G_TRUNC %2(s32)
%4(s32) = G_SELECT %3(s1), %0, %1
- %r0 = COPY %4(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %4(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -808,18 +808,18 @@ registers:
body: |
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
G_BRCOND %1(s1), %bb.1
G_BR %bb.2
bb.1:
- BX_RET 14, %noreg
+ BX_RET 14, $noreg
bb.2:
- BX_RET 14, %noreg
+ BX_RET 14, $noreg
...
---
@@ -844,13 +844,13 @@ registers:
body: |
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
- %2(s32) = COPY %r1
- %3(s32) = COPY %r2
+ %2(s32) = COPY $r1
+ %3(s32) = COPY $r2
G_BRCOND %1(s1), %bb.1
G_BR %bb.2
@@ -860,8 +860,8 @@ body: |
bb.2:
%4(s32) = G_PHI %2(s32), %bb.0, %3(s32), %bb.1
- %r0 = COPY %4(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %4(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_phi_s64
@@ -885,13 +885,13 @@ registers:
body: |
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: %r0, %d0, %d1
+ liveins: $r0, $d0, $d1
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
- %2(s64) = COPY %d0
- %3(s64) = COPY %d1
+ %2(s64) = COPY $d0
+ %3(s64) = COPY $d1
G_BRCOND %1(s1), %bb.1
G_BR %bb.2
@@ -901,8 +901,8 @@ body: |
bb.2:
%4(s64) = G_PHI %2(s64), %bb.0, %3(s64), %bb.1
- %d0 = COPY %4(s64)
- BX_RET 14, %noreg, implicit %d0
+ $d0 = COPY %4(s64)
+ BX_RET 14, $noreg, implicit $d0
...
---
name: test_fadd_s32
@@ -921,13 +921,13 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s32) = G_FADD %0, %1
- %s0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %s0
+ $s0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $s0
...
---
@@ -947,13 +947,13 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s64) = G_FADD %0, %1
- %d0 = COPY %2(s64)
- BX_RET 14, %noreg, implicit %d0
+ $d0 = COPY %2(s64)
+ BX_RET 14, $noreg, implicit $d0
...
---
@@ -973,13 +973,13 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s32) = G_FSUB %0, %1
- %s0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %s0
+ $s0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $s0
...
---
@@ -999,13 +999,13 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s64) = G_FSUB %0, %1
- %d0 = COPY %2(s64)
- BX_RET 14, %noreg, implicit %d0
+ $d0 = COPY %2(s64)
+ BX_RET 14, $noreg, implicit $d0
...
---
@@ -1025,13 +1025,13 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s32) = G_FMUL %0, %1
- %s0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %s0
+ $s0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $s0
...
---
@@ -1051,13 +1051,13 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s64) = G_FMUL %0, %1
- %d0 = COPY %2(s64)
- BX_RET 14, %noreg, implicit %d0
+ $d0 = COPY %2(s64)
+ BX_RET 14, $noreg, implicit $d0
...
---
@@ -1077,13 +1077,13 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %s0, %s1
+ liveins: $s0, $s1
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
%2(s32) = G_FDIV %0, %1
- %s0 = COPY %2(s32)
- BX_RET 14, %noreg, implicit %s0
+ $s0 = COPY %2(s32)
+ BX_RET 14, $noreg, implicit $s0
...
---
@@ -1103,13 +1103,13 @@ registers:
- { id: 2, class: _ }
body: |
bb.0:
- liveins: %d0, %d1
+ liveins: $d0, $d1
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
%2(s64) = G_FDIV %0, %1
- %d0 = COPY %2(s64)
- BX_RET 14, %noreg, implicit %d0
+ $d0 = COPY %2(s64)
+ BX_RET 14, $noreg, implicit $d0
...
---
@@ -1126,12 +1126,12 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %s0
+ liveins: $s0
- %0(s32) = COPY %s0
+ %0(s32) = COPY $s0
%1(s32) = G_FNEG %0
- %s0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %s0
+ $s0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $s0
...
---
@@ -1148,12 +1148,12 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %d0
+ liveins: $d0
- %0(s64) = COPY %d0
+ %0(s64) = COPY $d0
%1(s64) = G_FNEG %0
- %d0 = COPY %1(s64)
- BX_RET 14, %noreg, implicit %d0
+ $d0 = COPY %1(s64)
+ BX_RET 14, $noreg, implicit $d0
...
---
@@ -1174,14 +1174,14 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %s0, %s1, %s2
+ liveins: $s0, $s1, $s2
- %0(s32) = COPY %s0
- %1(s32) = COPY %s1
- %2(s32) = COPY %s2
+ %0(s32) = COPY $s0
+ %1(s32) = COPY $s1
+ %2(s32) = COPY $s2
%3(s32) = G_FMA %0, %1, %2
- %s0 = COPY %3(s32)
- BX_RET 14, %noreg, implicit %s0
+ $s0 = COPY %3(s32)
+ BX_RET 14, $noreg, implicit $s0
...
---
name: test_fma_s64
@@ -1201,14 +1201,14 @@ registers:
- { id: 3, class: _ }
body: |
bb.0:
- liveins: %d0, %d1, %d2
+ liveins: $d0, $d1, $d2
- %0(s64) = COPY %d0
- %1(s64) = COPY %d1
- %2(s64) = COPY %d2
+ %0(s64) = COPY $d0
+ %1(s64) = COPY $d1
+ %2(s64) = COPY $d2
%3(s64) = G_FMA %0, %1, %2
- %d0 = COPY %3(s64)
- BX_RET 14, %noreg, implicit %d0
+ $d0 = COPY %3(s64)
+ BX_RET 14, $noreg, implicit $d0
...
---
name: test_fpext_s32_to_s64
@@ -1224,12 +1224,12 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %s0
+ liveins: $s0
- %0(s32) = COPY %s0
+ %0(s32) = COPY $s0
%1(s64) = G_FPEXT %0
- %d0 = COPY %1(s64)
- BX_RET 14, %noreg, implicit %d0
+ $d0 = COPY %1(s64)
+ BX_RET 14, $noreg, implicit $d0
...
---
name: test_fptrunc_s64_to_s32
@@ -1245,12 +1245,12 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %d0
+ liveins: $d0
- %0(s64) = COPY %d0
+ %0(s64) = COPY $d0
%1(s32) = G_FPTRUNC %0
- %s0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %s0
+ $s0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $s0
...
---
name: test_fptosi_s32
@@ -1266,12 +1266,12 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %s0
+ liveins: $s0
- %0(s32) = COPY %s0
+ %0(s32) = COPY $s0
%1(s32) = G_FPTOSI %0
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -1288,12 +1288,12 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %d0
+ liveins: $d0
- %0(s64) = COPY %d0
+ %0(s64) = COPY $d0
%1(s32) = G_FPTOSI %0
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_fptoui_s32
@@ -1309,12 +1309,12 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %s0
+ liveins: $s0
- %0(s32) = COPY %s0
+ %0(s32) = COPY $s0
%1(s32) = G_FPTOUI %0
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -1331,12 +1331,12 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %d0
+ liveins: $d0
- %0(s64) = COPY %d0
+ %0(s64) = COPY $d0
%1(s32) = G_FPTOUI %0
- %r0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
...
---
name: test_sitofp_s32
@@ -1352,12 +1352,12 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s32) = G_SITOFP %0
- %s0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %s0
+ $s0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $s0
...
---
@@ -1374,12 +1374,12 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s64) = G_SITOFP %0
- %d0 = COPY %1(s64)
- BX_RET 14, %noreg, implicit %d0
+ $d0 = COPY %1(s64)
+ BX_RET 14, $noreg, implicit $d0
...
---
name: test_uitofp_s32
@@ -1395,12 +1395,12 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s32) = G_UITOFP %0
- %s0 = COPY %1(s32)
- BX_RET 14, %noreg, implicit %s0
+ $s0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $s0
...
---
@@ -1417,12 +1417,12 @@ registers:
- { id: 1, class: _ }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0(s32) = COPY %r0
+ %0(s32) = COPY $r0
%1(s64) = G_UITOFP %0
- %d0 = COPY %1(s64)
- BX_RET 14, %noreg, implicit %d0
+ $d0 = COPY %1(s64)
+ BX_RET 14, $noreg, implicit $d0
...
---
name: test_soft_fp_s64
@@ -1445,14 +1445,14 @@ registers:
- { id: 4, class: _ }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %0(s32) = COPY %r0
- %1(s32) = COPY %r1
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
%2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
%3(s32), %4(s32) = G_UNMERGE_VALUES %2(s64)
- %r0 = COPY %3(s32)
- %r1 = COPY %4(s32)
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ $r0 = COPY %3(s32)
+ $r1 = COPY %4(s32)
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir Wed Jan 31 14:04:26 2018
@@ -18,13 +18,13 @@ regBankSelected: true
body: |
bb.1:
; CHECK-LABEL: name: test_fptosi
- ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
- ; CHECK: [[VTOSIZS:%[0-9]+]]:spr = VTOSIZS [[COPY]], 14, %noreg
+ ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
+ ; CHECK: [[VTOSIZS:%[0-9]+]]:spr = VTOSIZS [[COPY]], 14, $noreg
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOSIZS]]
- ; CHECK: %r0 = COPY [[COPY1]]
- ; CHECK: MOVPCLR 14, %noreg, implicit %r0
- %0:fprb(s32) = COPY %s0
+ ; CHECK: $r0 = COPY [[COPY1]]
+ ; CHECK: MOVPCLR 14, $noreg, implicit $r0
+ %0:fprb(s32) = COPY $s0
%1:gprb(s32) = G_FPTOSI %0(s32)
- %r0 = COPY %1(s32)
- MOVPCLR 14, %noreg, implicit %r0
+ $r0 = COPY %1(s32)
+ MOVPCLR 14, $noreg, implicit $r0
...
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir Wed Jan 31 14:04:26 2018
@@ -33,13 +33,13 @@ body: |
; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel {{.*}}@internal_global
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global)
- ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @internal_global)
+ ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_global)
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[V]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[V]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_external_global
@@ -59,13 +59,13 @@ body: |
; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr target-flags(arm-got) @external_global :: (load 4 from got)
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global)
- ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @external_global)
+ ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_global)
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[V]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[V]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_internal_constant
@@ -85,13 +85,13 @@ body: |
; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel {{.*}}@internal_constant
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant)
- ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @internal_constant)
+ ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_constant)
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[V]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[V]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_external_constant
@@ -111,11 +111,11 @@ body: |
; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr target-flags(arm-got) @external_constant :: (load 4 from got)
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant)
- ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @external_constant)
+ ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_constant)
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[V]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[V]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir Wed Jan 31 14:04:26 2018
@@ -37,19 +37,19 @@ body: |
bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_global
; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global
- ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
+ ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool)
; RWPI-MOVT: [[OFF:%[0-9]+]]:gpr = MOVi32imm {{.*}} @internal_global
- ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
- ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr %r9, [[OFF]], 14, %noreg, %noreg
+ ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool)
+ ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr $r9, [[OFF]], 14, $noreg, $noreg
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global)
- ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @internal_global)
+ ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_global)
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[V]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[V]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_external_global
@@ -71,19 +71,19 @@ body: |
bb.0:
%0(p0) = G_GLOBAL_VALUE @external_global
; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global
- ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
+ ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool)
; RWPI-MOVT: [[OFF:%[0-9]+]]:gpr = MOVi32imm {{.*}} @external_global
- ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
- ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr %r9, [[OFF]], 14, %noreg, %noreg
+ ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool)
+ ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr $r9, [[OFF]], 14, $noreg, $noreg
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global)
- ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @external_global)
+ ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_global)
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[V]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[V]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_internal_constant
@@ -104,16 +104,16 @@ body: |
; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @internal_constant
; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @internal_constant
; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_constant
- ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
+ ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool)
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant)
- ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @internal_constant)
+ ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_constant)
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[V]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[V]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_external_constant
@@ -134,14 +134,14 @@ body: |
; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @external_constant
; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @external_constant
; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_constant
- ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
+ ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool)
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant)
- ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @external_constant)
+ ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_constant)
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[V]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[V]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir Wed Jan 31 14:04:26 2018
@@ -26,18 +26,18 @@ body: |
bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_global
; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global
- ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
+ ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool)
; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global
; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @internal_global
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global)
- ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg
+ ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[V]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[V]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
---
name: test_external_global
@@ -56,16 +56,16 @@ body: |
bb.0:
%0(p0) = G_GLOBAL_VALUE @external_global
; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global
- ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
+ ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool)
; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global
; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @external_global
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global)
- ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg
+ ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg
- %r0 = COPY %1(s32)
- ; CHECK: %r0 = COPY [[V]]
+ $r0 = COPY %1(s32)
+ ; CHECK: $r0 = COPY [[V]]
- BX_RET 14, %noreg, implicit %r0
- ; CHECK: BX_RET 14, %noreg, implicit %r0
+ BX_RET 14, $noreg, implicit $r0
+ ; CHECK: BX_RET 14, $noreg, implicit $r0
...
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/select-pr35926.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/select-pr35926.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/select-pr35926.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/select-pr35926.mir Wed Jan 31 14:04:26 2018
@@ -24,17 +24,17 @@ regBankSelected: true
selected: false
body: |
bb.1 (%ir-block.0):
- liveins: %d0, %d1, %d2
+ liveins: $d0, $d1, $d2
- %0:fprb(s64) = COPY %d0
- %1:fprb(s64) = COPY %d1
- %2:fprb(s64) = COPY %d2
+ %0:fprb(s64) = COPY $d0
+ %1:fprb(s64) = COPY $d1
+ %2:fprb(s64) = COPY $d2
%3:fprb(s64) = G_FNEG %1
%4:fprb(s64) = G_FMA %0, %3, %2
%5:fprb(s64) = G_FNEG %4
- %d0 = COPY %5(s64)
- MOVPCLR 14, %noreg, implicit %d0
+ $d0 = COPY %5(s64)
+ MOVPCLR 14, $noreg, implicit $d0
-# CHECK: %{{[0-9]+}}:dpr = VFNMSD %{{[0-9]+}}, %{{[0-9]+}}, %{{[0-9]+}}, 14, %noreg
+# CHECK: %{{[0-9]+}}:dpr = VFNMSD %{{[0-9]+}}, %{{[0-9]+}}, %{{[0-9]+}}, 14, $noreg
...
Modified: llvm/trunk/test/CodeGen/ARM/PR32721_ifcvt_triangle_unanalyzable.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/PR32721_ifcvt_triangle_unanalyzable.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/PR32721_ifcvt_triangle_unanalyzable.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/PR32721_ifcvt_triangle_unanalyzable.mir Wed Jan 31 14:04:26 2018
@@ -9,7 +9,7 @@ body: |
BX_RET 14, 0
bb.2:
- Bcc %bb.1, 1, %cpsr
+ Bcc %bb.1, 1, $cpsr
bb.3:
B %bb.1
Modified: llvm/trunk/test/CodeGen/ARM/Windows/vla-cpsr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/Windows/vla-cpsr.ll?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/Windows/vla-cpsr.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/Windows/vla-cpsr.ll Wed Jan 31 14:04:26 2018
@@ -9,5 +9,5 @@ entry:
ret void
}
-; CHECK: tBL 14, %noreg, &__chkstk, implicit-def %lr, implicit %sp, implicit killed %r4, implicit-def %r4, implicit-def dead %r12, implicit-def dead %cpsr
+; CHECK: tBL 14, $noreg, &__chkstk, implicit-def $lr, implicit $sp, implicit killed $r4, implicit-def $r4, implicit-def dead $r12, implicit-def dead $cpsr
Modified: llvm/trunk/test/CodeGen/ARM/cmp1-peephole-thumb.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/cmp1-peephole-thumb.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/cmp1-peephole-thumb.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/cmp1-peephole-thumb.mir Wed Jan 31 14:04:26 2018
@@ -32,8 +32,8 @@ registers:
- { id: 4, class: tgpr }
- { id: 5, class: tgpr }
liveins:
- - { reg: '%r0', virtual-reg: '%0' }
- - { reg: '%r1', virtual-reg: '%1' }
+ - { reg: '$r0', virtual-reg: '%0' }
+ - { reg: '$r1', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -49,27 +49,27 @@ frameInfo:
hasVAStart: false
hasMustTailInVarArgFunc: false
-# CHECK: tMOVi8 1, 14, %noreg
-# CHECK: tMOVi8 0, 14, %noreg
-# CHECK: tMUL %1, %0, 14, %noreg
+# CHECK: tMOVi8 1, 14, $noreg
+# CHECK: tMOVi8 0, 14, $noreg
+# CHECK: tMUL %1, %0, 14, $noreg
# CHECK-NOT: tCMPi8
body: |
bb.0.entry:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %1 = COPY %r1
- %0 = COPY %r0
- %2, %cpsr = tMUL %1, %0, 14, %noreg
- %3, %cpsr = tMOVi8 1, 14, %noreg
- %4, %cpsr = tMOVi8 0, 14, %noreg
- tCMPi8 killed %2, 0, 14, %noreg, implicit-def %cpsr
- tBcc %bb.2.entry, 0, %cpsr
+ %1 = COPY $r1
+ %0 = COPY $r0
+ %2, $cpsr = tMUL %1, %0, 14, $noreg
+ %3, $cpsr = tMOVi8 1, 14, $noreg
+ %4, $cpsr = tMOVi8 0, 14, $noreg
+ tCMPi8 killed %2, 0, 14, $noreg, implicit-def $cpsr
+ tBcc %bb.2.entry, 0, $cpsr
bb.1.entry:
bb.2.entry:
%5 = PHI %4, %bb.1.entry, %3, %bb.0.entry
- %r0 = COPY %5
- tBX_RET 14, %noreg, implicit %r0
+ $r0 = COPY %5
+ tBX_RET 14, $noreg, implicit $r0
...
Modified: llvm/trunk/test/CodeGen/ARM/cmp2-peephole-thumb.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/cmp2-peephole-thumb.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/cmp2-peephole-thumb.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/cmp2-peephole-thumb.mir Wed Jan 31 14:04:26 2018
@@ -51,8 +51,8 @@ registers:
- { id: 4, class: tgpr }
- { id: 5, class: tgpr }
liveins:
- - { reg: '%r0', virtual-reg: '%0' }
- - { reg: '%r1', virtual-reg: '%1' }
+ - { reg: '$r0', virtual-reg: '%0' }
+ - { reg: '$r1', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -76,28 +76,28 @@ stack:
# CHECK-NEXT: tCMPi8
body: |
bb.0.entry:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %1 = COPY %r1
- %0 = COPY %r0
- %2, %cpsr = tMUL %0, %1, 14, %noreg
- tSTRspi %2, %stack.1.mul, 0, 14, %noreg :: (store 4 into %ir.mul)
- tCMPi8 %2, 0, 14, %noreg, implicit-def %cpsr
- tBcc %bb.2.if.end, 12, %cpsr
- tB %bb.1.if.then, 14, %noreg
+ %1 = COPY $r1
+ %0 = COPY $r0
+ %2, $cpsr = tMUL %0, %1, 14, $noreg
+ tSTRspi %2, %stack.1.mul, 0, 14, $noreg :: (store 4 into %ir.mul)
+ tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
+ tBcc %bb.2.if.end, 12, $cpsr
+ tB %bb.1.if.then, 14, $noreg
bb.1.if.then:
- %4, %cpsr = tMOVi8 42, 14, %noreg
- tSTRspi killed %4, %stack.0.retval, 0, 14, %noreg :: (store 4 into %ir.retval)
- tB %bb.3.return, 14, %noreg
+ %4, $cpsr = tMOVi8 42, 14, $noreg
+ tSTRspi killed %4, %stack.0.retval, 0, 14, $noreg :: (store 4 into %ir.retval)
+ tB %bb.3.return, 14, $noreg
bb.2.if.end:
- %3, %cpsr = tMOVi8 1, 14, %noreg
- tSTRspi killed %3, %stack.0.retval, 0, 14, %noreg :: (store 4 into %ir.retval)
+ %3, $cpsr = tMOVi8 1, 14, $noreg
+ tSTRspi killed %3, %stack.0.retval, 0, 14, $noreg :: (store 4 into %ir.retval)
bb.3.return:
- %5 = tLDRspi %stack.0.retval, 0, 14, %noreg :: (dereferenceable load 4 from %ir.retval)
- %r0 = COPY %5
- tBX_RET 14, %noreg, implicit %r0
+ %5 = tLDRspi %stack.0.retval, 0, 14, $noreg :: (dereferenceable load 4 from %ir.retval)
+ $r0 = COPY %5
+ tBX_RET 14, $noreg, implicit $r0
...
Modified: llvm/trunk/test/CodeGen/ARM/constant-islands-cfg.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/constant-islands-cfg.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/constant-islands-cfg.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/constant-islands-cfg.mir Wed Jan 31 14:04:26 2018
@@ -15,7 +15,7 @@ selected: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '%r0', virtual-reg: '' }
+ - { reg: '$r0', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -37,7 +37,7 @@ fixedStack:
# CHECK-LABEL: name: test_split_cfg
# CHECK: bb.0:
# CHECK: successors: %[[LONG_BR_BB:bb.[0-9]+]](0x{{[0-9a-f]+}}), %[[DEST1:bb.[0-9]+]](0x{{[0-9a-f]+}}){{$}}
-# CHECK: tBcc %[[LONG_BR_BB]], 0, %cpsr
+# CHECK: tBcc %[[LONG_BR_BB]], 0, $cpsr
# CHECK: tB %[[DEST1]]
# CHECK: [[LONG_BR_BB]]:
# CHECK: successors: %[[DEST2:bb.[0-9]+]](0x{{[0-9a-f]+}}){{$}}
@@ -47,18 +47,18 @@ fixedStack:
body: |
bb.0:
- liveins: %r0
- tCMPi8 killed %r0, 0, 14, %noreg, implicit-def %cpsr
- tBcc %bb.2, 1, killed %cpsr
- tB %bb.3, 14, %noreg
+ liveins: $r0
+ tCMPi8 killed $r0, 0, 14, $noreg, implicit-def $cpsr
+ tBcc %bb.2, 1, killed $cpsr
+ tB %bb.3, 14, $noreg
bb.1:
- dead %r0 = SPACE 256, undef %r0
+ dead $r0 = SPACE 256, undef $r0
bb.2:
- tPOP_RET 14, %noreg, def %pc
+ tPOP_RET 14, $noreg, def $pc
bb.3:
- tPOP_RET 14, %noreg, def %pc
+ tPOP_RET 14, $noreg, def $pc
...
Modified: llvm/trunk/test/CodeGen/ARM/dbg-range-extension.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/dbg-range-extension.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/dbg-range-extension.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/dbg-range-extension.mir Wed Jan 31 14:04:26 2018
@@ -23,37 +23,37 @@
# CHECK: [[VAR_I:![0-9]+]] = !DILocalVariable(name: "i",
# CHECK: bb.0.entry
-# CHECK: DBG_VALUE debug-use %r0, debug-use %noreg, [[VAR_A]]
-# CHECK: DBG_VALUE debug-use [[REG_A:%r[0-9]+]], debug-use %noreg, [[VAR_A]]
-# CHECK: DBG_VALUE debug-use [[REG_B:%r[0-9]+]], debug-use %noreg, [[VAR_B]]
+# CHECK: DBG_VALUE debug-use $r0, debug-use $noreg, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_A:\$r[0-9]+]], debug-use $noreg, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_B:\$r[0-9]+]], debug-use $noreg, [[VAR_B]]
# CHECK: bb.1.if.then
-# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]]
-# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]]
-# CHECK: DBG_VALUE debug-use [[REG_C:%r[0-9]+]], debug-use %noreg, [[VAR_C]]
+# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use $noreg, [[VAR_B]]
+# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use $noreg, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_C:\$r[0-9]+]], debug-use $noreg, [[VAR_C]]
# CHECK: DBG_VALUE 1, 0, [[VAR_I]]
# CHECK: bb.2.for.body
-# CHECK: DBG_VALUE debug-use [[REG_I:%r[0-9]+]], debug-use %noreg, [[VAR_I]]
-# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use %noreg, [[VAR_C]]
-# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]]
-# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]]
-# CHECK: DBG_VALUE debug-use [[REG_I]], debug-use %noreg, [[VAR_I]]
+# CHECK: DBG_VALUE debug-use [[REG_I:\$r[0-9]+]], debug-use $noreg, [[VAR_I]]
+# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use $noreg, [[VAR_C]]
+# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use $noreg, [[VAR_B]]
+# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use $noreg, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_I]], debug-use $noreg, [[VAR_I]]
# CHECK: bb.3.for.cond
-# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use %noreg, [[VAR_C]]
-# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]]
-# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]]
-# CHECK: DBG_VALUE debug-use [[REG_I]], debug-use %noreg, [[VAR_I]]
+# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use $noreg, [[VAR_C]]
+# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use $noreg, [[VAR_B]]
+# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use $noreg, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_I]], debug-use $noreg, [[VAR_I]]
# CHECK: bb.4.for.cond.cleanup
-# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use %noreg, [[VAR_C]]
-# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]]
-# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use $noreg, [[VAR_C]]
+# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use $noreg, [[VAR_B]]
+# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use $noreg, [[VAR_A]]
# CHECK: bb.5.if.end
-# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]]
-# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]]
+# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use $noreg, [[VAR_B]]
+# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use $noreg, [[VAR_A]]
--- |
; ModuleID = '/data/kwalker/work/OpenSource-llvm/llvm/test/CodeGen/ARM/dbg-range-extension.ll'
source_filename = "/data/kwalker/work/OpenSource-llvm/llvm/test/CodeGen/ARM/dbg-range-extension.ll"
@@ -171,21 +171,21 @@ regBankSelected: false
selected: false
tracksRegLiveness: false
liveins:
- - { reg: '%r0' }
-calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13',
- '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4',
- '%r5', '%r6', '%r7', '%r8', '%r9', '%r10', '%r11',
- '%s16', '%s17', '%s18', '%s19', '%s20', '%s21',
- '%s22', '%s23', '%s24', '%s25', '%s26', '%s27',
- '%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11',
- '%d10_d12', '%d11_d13', '%d12_d14', '%d13_d15',
- '%q4_q5', '%q5_q6', '%q6_q7', '%q4_q5_q6_q7', '%r4_r5',
- '%r6_r7', '%r8_r9', '%r10_r11', '%d8_d9_d10', '%d9_d10_d11',
- '%d10_d11_d12', '%d11_d12_d13', '%d12_d13_d14',
- '%d13_d14_d15', '%d8_d10_d12', '%d9_d11_d13', '%d10_d12_d14',
- '%d11_d13_d15', '%d8_d10_d12_d14', '%d9_d11_d13_d15',
- '%d9_d10', '%d11_d12', '%d13_d14', '%d9_d10_d11_d12',
- '%d11_d12_d13_d14' ]
+ - { reg: '$r0' }
+calleeSavedRegisters: [ '$lr', '$d8', '$d9', '$d10', '$d11', '$d12', '$d13',
+ '$d14', '$d15', '$q4', '$q5', '$q6', '$q7', '$r4',
+ '$r5', '$r6', '$r7', '$r8', '$r9', '$r10', '$r11',
+ '$s16', '$s17', '$s18', '$s19', '$s20', '$s21',
+ '$s22', '$s23', '$s24', '$s25', '$s26', '$s27',
+ '$s28', '$s29', '$s30', '$s31', '$d8_d10', '$d9_d11',
+ '$d10_d12', '$d11_d13', '$d12_d14', '$d13_d15',
+ '$q4_q5', '$q5_q6', '$q6_q7', '$q4_q5_q6_q7', '$r4_r5',
+ '$r6_r7', '$r8_r9', '$r10_r11', '$d8_d9_d10', '$d9_d10_d11',
+ '$d10_d11_d12', '$d11_d12_d13', '$d12_d13_d14',
+ '$d13_d14_d15', '$d8_d10_d12', '$d9_d11_d13', '$d10_d12_d14',
+ '$d11_d13_d15', '$d8_d10_d12_d14', '$d9_d11_d13_d15',
+ '$d9_d10', '$d11_d12', '$d13_d14', '$d9_d10_d11_d12',
+ '$d11_d12_d13_d14' ]
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -201,76 +201,76 @@ frameInfo:
hasVAStart: false
hasMustTailInVarArgFunc: false
stack:
- - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr' }
- - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r11' }
- - { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4, callee-saved-register: '%r7' }
- - { id: 3, type: spill-slot, offset: -16, size: 4, alignment: 4, callee-saved-register: '%r6' }
- - { id: 4, type: spill-slot, offset: -20, size: 4, alignment: 4, callee-saved-register: '%r5' }
- - { id: 5, type: spill-slot, offset: -24, size: 4, alignment: 4, callee-saved-register: '%r4' }
+ - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '$lr' }
+ - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '$r11' }
+ - { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4, callee-saved-register: '$r7' }
+ - { id: 3, type: spill-slot, offset: -16, size: 4, alignment: 4, callee-saved-register: '$r6' }
+ - { id: 4, type: spill-slot, offset: -20, size: 4, alignment: 4, callee-saved-register: '$r5' }
+ - { id: 5, type: spill-slot, offset: -24, size: 4, alignment: 4, callee-saved-register: '$r4' }
body: |
bb.0.entry:
- liveins: %r0, %r4, %r5, %r6, %r7, %r11, %lr
+ liveins: $r0, $r4, $r5, $r6, $r7, $r11, $lr
- %sp = frame-setup STMDB_UPD %sp, 14, %noreg, killed %r4, killed %r5, killed %r6, killed %r7, killed %r11, killed %lr
+ $sp = frame-setup STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r11, killed $lr
frame-setup CFI_INSTRUCTION def_cfa_offset 24
- frame-setup CFI_INSTRUCTION offset %lr, -4
- frame-setup CFI_INSTRUCTION offset %r11, -8
- frame-setup CFI_INSTRUCTION offset %r7, -12
- frame-setup CFI_INSTRUCTION offset %r6, -16
- frame-setup CFI_INSTRUCTION offset %r5, -20
- frame-setup CFI_INSTRUCTION offset %r4, -24
- DBG_VALUE debug-use %r0, debug-use %noreg, !13, !20, debug-location !21
- %r4 = MOVr killed %r0, 14, %noreg, %noreg
- DBG_VALUE debug-use %r4, debug-use %noreg, !13, !20, debug-location !21
- %r0 = MOVi 10, 14, %noreg, _, debug-location !22
- %r1 = MOVi 11, 14, %noreg, _, debug-location !22
- BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def %r0, debug-location !22
- %r5 = MOVr killed %r0, 14, %noreg, _, debug-location !22
- DBG_VALUE debug-use %r5, debug-use %noreg, !14, !20, debug-location !23
- CMPri %r4, 0, 14, %noreg, implicit-def %cpsr, debug-location !25
- Bcc %bb.5.if.end, 0, killed %cpsr
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r11, -8
+ frame-setup CFI_INSTRUCTION offset $r7, -12
+ frame-setup CFI_INSTRUCTION offset $r6, -16
+ frame-setup CFI_INSTRUCTION offset $r5, -20
+ frame-setup CFI_INSTRUCTION offset $r4, -24
+ DBG_VALUE debug-use $r0, debug-use $noreg, !13, !20, debug-location !21
+ $r4 = MOVr killed $r0, 14, $noreg, $noreg
+ DBG_VALUE debug-use $r4, debug-use $noreg, !13, !20, debug-location !21
+ $r0 = MOVi 10, 14, $noreg, _, debug-location !22
+ $r1 = MOVi 11, 14, $noreg, _, debug-location !22
+ BL @func2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit-def $sp, implicit-def $r0, debug-location !22
+ $r5 = MOVr killed $r0, 14, $noreg, _, debug-location !22
+ DBG_VALUE debug-use $r5, debug-use $noreg, !14, !20, debug-location !23
+ CMPri $r4, 0, 14, $noreg, implicit-def $cpsr, debug-location !25
+ Bcc %bb.5.if.end, 0, killed $cpsr
bb.1.if.then:
- liveins: %r4, %r5
+ liveins: $r4, $r5
- %r0 = MOVi 12, 14, %noreg, _, debug-location !26
- %r1 = MOVi 13, 14, %noreg, _, debug-location !26
- BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def %r0, debug-location !26
- %r6 = MOVr killed %r0, 14, %noreg, _, debug-location !26
- DBG_VALUE debug-use %r6, debug-use %noreg, !15, !20, debug-location !27
- %r7 = MOVi 1, 14, %noreg, %noreg
+ $r0 = MOVi 12, 14, $noreg, _, debug-location !26
+ $r1 = MOVi 13, 14, $noreg, _, debug-location !26
+ BL @func2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit-def $sp, implicit-def $r0, debug-location !26
+ $r6 = MOVr killed $r0, 14, $noreg, _, debug-location !26
+ DBG_VALUE debug-use $r6, debug-use $noreg, !15, !20, debug-location !27
+ $r7 = MOVi 1, 14, $noreg, $noreg
DBG_VALUE 1, 0, !18, !20, debug-location !28
B %bb.3.for.cond
bb.2.for.body:
- liveins: %r4, %r5, %r6, %r7
+ liveins: $r4, $r5, $r6, $r7
- %r1 = ADDrr %r5, %r7, 14, %noreg, _, debug-location !36
- %r0 = MOVr %r7, 14, %noreg, _, debug-location !36
- BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def dead %r0, debug-location !36
- %r7 = ADDri killed %r7, 1, 14, %noreg, _, debug-location !38
- DBG_VALUE debug-use %r7, debug-use %noreg, !18, !20, debug-location !28
+ $r1 = ADDrr $r5, $r7, 14, $noreg, _, debug-location !36
+ $r0 = MOVr $r7, 14, $noreg, _, debug-location !36
+ BL @func2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit-def $sp, implicit-def dead $r0, debug-location !36
+ $r7 = ADDri killed $r7, 1, 14, $noreg, _, debug-location !38
+ DBG_VALUE debug-use $r7, debug-use $noreg, !18, !20, debug-location !28
bb.3.for.cond:
- liveins: %r4, %r5, %r6, %r7
+ liveins: $r4, $r5, $r6, $r7
- DBG_VALUE debug-use %r7, debug-use %noreg, !18, !20, debug-location !28
- CMPrr %r7, %r4, 14, %noreg, implicit-def %cpsr, debug-location !33
- Bcc %bb.2.for.body, 11, killed %cpsr, debug-location !33
+ DBG_VALUE debug-use $r7, debug-use $noreg, !18, !20, debug-location !28
+ CMPrr $r7, $r4, 14, $noreg, implicit-def $cpsr, debug-location !33
+ Bcc %bb.2.for.body, 11, killed $cpsr, debug-location !33
bb.4.for.cond.cleanup:
- liveins: %r4, %r5, %r6
+ liveins: $r4, $r5, $r6
- %r0 = MOVr %r5, 14, %noreg, _, debug-location !34
- %r1 = MOVr killed %r6, 14, %noreg, _, debug-location !34
- BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def dead %r0, debug-location !34
+ $r0 = MOVr $r5, 14, $noreg, _, debug-location !34
+ $r1 = MOVr killed $r6, 14, $noreg, _, debug-location !34
+ BL @func2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit-def $sp, implicit-def dead $r0, debug-location !34
bb.5.if.end:
- liveins: %r4, %r5
+ liveins: $r4, $r5
- %r0 = MOVr killed %r5, 14, %noreg, _, debug-location !43
- %r1 = MOVr killed %r4, 14, %noreg, _, debug-location !43
- %sp = LDMIA_UPD %sp, 14, %noreg, def %r4, def %r5, def %r6, def %r7, def %r11, def %lr, debug-location !43
- TAILJMPd @func2, implicit %sp, implicit %sp, implicit killed %r0, implicit killed %r1, debug-location !43
+ $r0 = MOVr killed $r5, 14, $noreg, _, debug-location !43
+ $r1 = MOVr killed $r4, 14, $noreg, _, debug-location !43
+ $sp = LDMIA_UPD $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r11, def $lr, debug-location !43
+ TAILJMPd @func2, implicit $sp, implicit $sp, implicit killed $r0, implicit killed $r1, debug-location !43
...
Modified: llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/debug-info-arg.ll Wed Jan 31 14:04:26 2018
@@ -11,7 +11,7 @@ define void @foo(%struct.tag_s* nocaptur
tail call void @llvm.dbg.value(metadata %struct.tag_s* %c, metadata !13, metadata !DIExpression()), !dbg !21
tail call void @llvm.dbg.value(metadata i64 %x, metadata !14, metadata !DIExpression()), !dbg !22
tail call void @llvm.dbg.value(metadata i64 %y, metadata !17, metadata !DIExpression()), !dbg !23
-;CHECK: @DEBUG_VALUE: foo:y <- [DW_OP_plus_uconst 8] [%r7+0]
+;CHECK: @DEBUG_VALUE: foo:y <- [DW_OP_plus_uconst 8] [$r7+0]
tail call void @llvm.dbg.value(metadata %struct.tag_s* %ptr1, metadata !18, metadata !DIExpression()), !dbg !24
tail call void @llvm.dbg.value(metadata %struct.tag_s* %ptr2, metadata !19, metadata !DIExpression()), !dbg !25
%1 = icmp eq %struct.tag_s* %c, null, !dbg !26
Modified: llvm/trunk/test/CodeGen/ARM/debug-info-branch-folding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/debug-info-branch-folding.ll?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/debug-info-branch-folding.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/debug-info-branch-folding.ll Wed Jan 31 14:04:26 2018
@@ -5,8 +5,8 @@ target triple = "thumbv7-apple-macosx10.
;CHECK: vadd.f32 q4, q8, q8
;CHECK-NEXT: LBB0_1
-;CHECK: @DEBUG_VALUE: x <- %q4{{$}}
-;CHECK-NEXT: @DEBUG_VALUE: y <- %q4{{$}}
+;CHECK: @DEBUG_VALUE: x <- $q4{{$}}
+;CHECK-NEXT: @DEBUG_VALUE: y <- $q4{{$}}
;CHECK: beq LBB0_1
Modified: llvm/trunk/test/CodeGen/ARM/expand-pseudos.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/expand-pseudos.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/expand-pseudos.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/expand-pseudos.mir Wed Jan 31 14:04:26 2018
@@ -20,16 +20,16 @@ name: test1
alignment: 2
tracksRegLiveness: true
liveins:
- - { reg: '%r0', virtual-reg: '' }
+ - { reg: '$r0', virtual-reg: '' }
body: |
bb.0.entry:
- liveins: %r0
+ liveins: $r0
- %r1 = MOVi 2, 14, %noreg, %noreg
- CMPri killed %r0, 0, 14, %noreg, implicit-def %cpsr
- %r1 = MOVCCi16 killed %r1, 500, 0, killed %cpsr
- %r0 = MOVr killed %r1, 14, %noreg, %noreg
- BX_RET 14, %noreg, implicit %r0
+ $r1 = MOVi 2, 14, $noreg, $noreg
+ CMPri killed $r0, 0, 14, $noreg, implicit-def $cpsr
+ $r1 = MOVCCi16 killed $r1, 500, 0, killed $cpsr
+ $r0 = MOVr killed $r1, 14, $noreg, $noreg
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -37,16 +37,16 @@ name: test2
alignment: 2
tracksRegLiveness: true
liveins:
- - { reg: '%r0', virtual-reg: '' }
+ - { reg: '$r0', virtual-reg: '' }
body: |
bb.0.entry:
- liveins: %r0
+ liveins: $r0
- %r1 = MOVi 2, 14, %noreg, %noreg
- CMPri killed %r0, 0, 14, %noreg, implicit-def %cpsr
- %r1 = MOVCCi32imm killed %r1, 500500500, 0, killed %cpsr
- %r0 = MOVr killed %r1, 14, %noreg, %noreg
- BX_RET 14, %noreg, implicit %r0
+ $r1 = MOVi 2, 14, $noreg, $noreg
+ CMPri killed $r0, 0, 14, $noreg, implicit-def $cpsr
+ $r1 = MOVCCi32imm killed $r1, 500500500, 0, killed $cpsr
+ $r0 = MOVr killed $r1, 14, $noreg, $noreg
+ BX_RET 14, $noreg, implicit $r0
...
---
@@ -54,22 +54,22 @@ name: test3
alignment: 2
tracksRegLiveness: true
liveins:
- - { reg: '%r0', virtual-reg: '' }
- - { reg: '%r1', virtual-reg: '' }
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
body: |
bb.0.entry:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- CMPri %r1, 500, 14, %noreg, implicit-def %cpsr
- %r0 = MOVCCr killed %r0, killed %r1, 12, killed %cpsr
- BX_RET 14, %noreg, implicit %r0
+ CMPri $r1, 500, 14, $noreg, implicit-def $cpsr
+ $r0 = MOVCCr killed $r0, killed $r1, 12, killed $cpsr
+ BX_RET 14, $noreg, implicit $r0
...
# CHECK-LABEL: name: test1
-# CHECK: %r1 = MOVi16 500, 0, killed %cpsr, implicit killed %r1
+# CHECK: $r1 = MOVi16 500, 0, killed $cpsr, implicit killed $r1
# CHECK-LABEL: name: test2
-# CHECK: %r1 = MOVi16 2068, 0, %cpsr, implicit killed %r1
-# CHECK: %r1 = MOVTi16 %r1, 7637, 0, %cpsr
+# CHECK: $r1 = MOVi16 2068, 0, $cpsr, implicit killed $r1
+# CHECK: $r1 = MOVTi16 $r1, 7637, 0, $cpsr
# CHECK-LABEL: name: test3
-# CHECK: %r0 = MOVr killed %r1, 12, killed %cpsr, %noreg, implicit killed %r0
+# CHECK: $r0 = MOVr killed $r1, 12, killed $cpsr, $noreg, implicit killed $r0
Modified: llvm/trunk/test/CodeGen/ARM/fpoffset_overflow.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fpoffset_overflow.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fpoffset_overflow.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/fpoffset_overflow.mir Wed Jan 31 14:04:26 2018
@@ -3,10 +3,10 @@
# This should trigger an emergency spill in the register scavenger because the
# frame offset into the large argument is too large.
# CHECK-LABEL: name: func0
-# CHECK: t2STRi12 killed [[SPILLED:%r[0-9]+]], %sp, 0, 14, %noreg :: (store 4 into %stack.0)
-# CHECK: [[SPILLED]] = t2ADDri killed %sp, 4096, 14, %noreg, %noreg
-# CHECK: %sp = t2LDRi12 killed [[SPILLED]], 40, 14, %noreg :: (load 4)
-# CHECK: [[SPILLED]] = t2LDRi12 %sp, 0, 14, %noreg :: (load 4 from %stack.0)
+# CHECK: t2STRi12 killed [[SPILLED:\$r[0-9]+]], $sp, 0, 14, $noreg :: (store 4 into %stack.0)
+# CHECK: [[SPILLED]] = t2ADDri killed $sp, 4096, 14, $noreg, $noreg
+# CHECK: $sp = t2LDRi12 killed [[SPILLED]], 40, 14, $noreg :: (load 4)
+# CHECK: [[SPILLED]] = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.0)
name: func0
tracksRegLiveness: true
fixedStack:
@@ -16,44 +16,44 @@ fixedStack:
isAliased: false }
body: |
bb.0:
- %r0 = IMPLICIT_DEF
- %r1 = IMPLICIT_DEF
- %r2 = IMPLICIT_DEF
- %r3 = IMPLICIT_DEF
- %r4 = IMPLICIT_DEF
- %r5 = IMPLICIT_DEF
- %r6 = IMPLICIT_DEF
- %r7 = IMPLICIT_DEF
- %r8 = IMPLICIT_DEF
- %r9 = IMPLICIT_DEF
- %r10 = IMPLICIT_DEF
- %r11 = IMPLICIT_DEF
- %r12 = IMPLICIT_DEF
- %lr = IMPLICIT_DEF
+ $r0 = IMPLICIT_DEF
+ $r1 = IMPLICIT_DEF
+ $r2 = IMPLICIT_DEF
+ $r3 = IMPLICIT_DEF
+ $r4 = IMPLICIT_DEF
+ $r5 = IMPLICIT_DEF
+ $r6 = IMPLICIT_DEF
+ $r7 = IMPLICIT_DEF
+ $r8 = IMPLICIT_DEF
+ $r9 = IMPLICIT_DEF
+ $r10 = IMPLICIT_DEF
+ $r11 = IMPLICIT_DEF
+ $r12 = IMPLICIT_DEF
+ $lr = IMPLICIT_DEF
- %sp = t2LDRi12 %fixed-stack.0, 0, 14, %noreg :: (load 4)
+ $sp = t2LDRi12 %fixed-stack.0, 0, 14, $noreg :: (load 4)
- KILL %r0
- KILL %r1
- KILL %r2
- KILL %r3
- KILL %r4
- KILL %r5
- KILL %r6
- KILL %r7
- KILL %r8
- KILL %r9
- KILL %r10
- KILL %r11
- KILL %r12
- KILL %lr
+ KILL $r0
+ KILL $r1
+ KILL $r2
+ KILL $r3
+ KILL $r4
+ KILL $r5
+ KILL $r6
+ KILL $r7
+ KILL $r8
+ KILL $r9
+ KILL $r10
+ KILL $r11
+ KILL $r12
+ KILL $lr
...
---
# This should not trigger an emergency spill yet.
# CHECK-LABEL: name: func1
# CHECK-NOT: t2STRi12
# CHECK-NOT: t2ADDri
-# CHECK: %r11 = t2LDRi12 %sp, 4092, 14, %noreg :: (load 4)
+# CHECK: $r11 = t2LDRi12 $sp, 4092, 14, $noreg :: (load 4)
# CHECK-NOT: t2LDRi12
name: func1
tracksRegLiveness: true
@@ -64,33 +64,33 @@ fixedStack:
isAliased: false }
body: |
bb.0:
- %r0 = IMPLICIT_DEF
- %r1 = IMPLICIT_DEF
- %r2 = IMPLICIT_DEF
- %r3 = IMPLICIT_DEF
- %r4 = IMPLICIT_DEF
- %r5 = IMPLICIT_DEF
- %r6 = IMPLICIT_DEF
- %r8 = IMPLICIT_DEF
- %r9 = IMPLICIT_DEF
- %r10 = IMPLICIT_DEF
- %r11 = IMPLICIT_DEF
- %r12 = IMPLICIT_DEF
- %lr = IMPLICIT_DEF
+ $r0 = IMPLICIT_DEF
+ $r1 = IMPLICIT_DEF
+ $r2 = IMPLICIT_DEF
+ $r3 = IMPLICIT_DEF
+ $r4 = IMPLICIT_DEF
+ $r5 = IMPLICIT_DEF
+ $r6 = IMPLICIT_DEF
+ $r8 = IMPLICIT_DEF
+ $r9 = IMPLICIT_DEF
+ $r10 = IMPLICIT_DEF
+ $r11 = IMPLICIT_DEF
+ $r12 = IMPLICIT_DEF
+ $lr = IMPLICIT_DEF
- %r11 = t2LDRi12 %fixed-stack.0, 0, 14, %noreg :: (load 4)
+ $r11 = t2LDRi12 %fixed-stack.0, 0, 14, $noreg :: (load 4)
- KILL %r0
- KILL %r1
- KILL %r2
- KILL %r3
- KILL %r4
- KILL %r5
- KILL %r6
- KILL %r8
- KILL %r9
- KILL %r10
- KILL %r11
- KILL %r12
- KILL %lr
+ KILL $r0
+ KILL $r1
+ KILL $r2
+ KILL $r3
+ KILL $r4
+ KILL $r5
+ KILL $r6
+ KILL $r8
+ KILL $r9
+ KILL $r10
+ KILL $r11
+ KILL $r12
+ KILL $lr
...
Modified: llvm/trunk/test/CodeGen/ARM/ifcvt_canFallThroughTo.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt_canFallThroughTo.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ifcvt_canFallThroughTo.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/ifcvt_canFallThroughTo.mir Wed Jan 31 14:04:26 2018
@@ -10,12 +10,12 @@ body: |
bb.1:
successors: %bb.2, %bb.4
- Bcc %bb.4, 1, %cpsr
+ Bcc %bb.4, 1, $cpsr
bb.2:
successors: %bb.3, %bb.5
- Bcc %bb.5, 1, %cpsr
+ Bcc %bb.5, 1, $cpsr
bb.3:
successors: %bb.5
@@ -28,7 +28,7 @@ body: |
bb.5:
successors: %bb.1, %bb.6
- Bcc %bb.1, 1, %cpsr
+ Bcc %bb.1, 1, $cpsr
bb.6:
BX_RET 14, _
Modified: llvm/trunk/test/CodeGen/ARM/ifcvt_diamond_unanalyzable.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt_diamond_unanalyzable.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ifcvt_diamond_unanalyzable.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/ifcvt_diamond_unanalyzable.mir Wed Jan 31 14:04:26 2018
@@ -3,19 +3,19 @@
name: foo
body: |
bb.0:
- Bcc %bb.2, 1, %cpsr
+ Bcc %bb.2, 1, $cpsr
bb.1:
- %sp = tADDspi %sp, 1, 14, _
+ $sp = tADDspi $sp, 1, 14, _
B %bb.3
bb.2:
- %sp = tADDspi %sp, 2, 14, _
+ $sp = tADDspi $sp, 2, 14, _
B %bb.3
bb.3:
successors:
- %sp = tADDspi %sp, 3, 14, _
+ $sp = tADDspi $sp, 3, 14, _
BX_RET 14, _
...
@@ -24,7 +24,7 @@ body: |
# CHECK: body: |
# CHECK: bb.0:
-# CHECK: %sp = tADDspi %sp, 2, 1, %cpsr
-# CHECK: %sp = tADDspi %sp, 1, 0, %cpsr, implicit %sp
-# CHECK: %sp = tADDspi %sp, 3, 14, %noreg
-# CHECK: BX_RET 14, %noreg
+# CHECK: $sp = tADDspi $sp, 2, 1, $cpsr
+# CHECK: $sp = tADDspi $sp, 1, 0, $cpsr, implicit $sp
+# CHECK: $sp = tADDspi $sp, 3, 14, $noreg
+# CHECK: BX_RET 14, $noreg
Modified: llvm/trunk/test/CodeGen/ARM/ifcvt_forked_diamond_unanalyzable.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt_forked_diamond_unanalyzable.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ifcvt_forked_diamond_unanalyzable.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/ifcvt_forked_diamond_unanalyzable.mir Wed Jan 31 14:04:26 2018
@@ -3,28 +3,28 @@
name: foo
body: |
bb.0:
- Bcc %bb.2, 1, %cpsr
+ Bcc %bb.2, 1, $cpsr
bb.1:
successors: %bb.3(0x20000000), %bb.4(0x60000000)
- %sp = tADDspi %sp, 1, 14, _
- Bcc %bb.3, 1, %cpsr
+ $sp = tADDspi $sp, 1, 14, _
+ Bcc %bb.3, 1, $cpsr
B %bb.4
bb.2:
successors: %bb.3(0x20000000), %bb.4(0x60000000)
- %sp = tADDspi %sp, 2, 14, _
- Bcc %bb.3, 1, %cpsr
+ $sp = tADDspi $sp, 2, 14, _
+ Bcc %bb.3, 1, $cpsr
B %bb.4
bb.3:
successors:
- %sp = tADDspi %sp, 3, 14, _
+ $sp = tADDspi $sp, 3, 14, _
BX_RET 14, _
bb.4:
successors:
- %sp = tADDspi %sp, 4, 14, _
+ $sp = tADDspi $sp, 4, 14, _
BX_RET 14, _
...
@@ -35,14 +35,14 @@ body: |
# CHECK: bb.0:
# CHECK: successors: %bb.2(0x20000000), %bb.1(0x60000000)
-# CHECK: %sp = tADDspi %sp, 2, 1, %cpsr
-# CHECK: %sp = tADDspi %sp, 1, 0, %cpsr, implicit %sp
-# CHECK: Bcc %bb.2, 1, %cpsr
+# CHECK: $sp = tADDspi $sp, 2, 1, $cpsr
+# CHECK: $sp = tADDspi $sp, 1, 0, $cpsr, implicit $sp
+# CHECK: Bcc %bb.2, 1, $cpsr
# CHECK: bb.1:
-# CHECK: %sp = tADDspi %sp, 4, 14, %noreg
-# CHECK: BX_RET 14, %noreg
+# CHECK: $sp = tADDspi $sp, 4, 14, $noreg
+# CHECK: BX_RET 14, $noreg
# CHECK: bb.2:
-# CHECK: %sp = tADDspi %sp, 3, 14, %noreg
-# CHECK: BX_RET 14, %noreg
+# CHECK: $sp = tADDspi $sp, 3, 14, $noreg
+# CHECK: BX_RET 14, $noreg
Modified: llvm/trunk/test/CodeGen/ARM/ifcvt_simple_bad_zero_prob_succ.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt_simple_bad_zero_prob_succ.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ifcvt_simple_bad_zero_prob_succ.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/ifcvt_simple_bad_zero_prob_succ.mir Wed Jan 31 14:04:26 2018
@@ -5,16 +5,16 @@ body: |
bb.0:
bb.1:
- Bcc %bb.3, 0, %cpsr
+ Bcc %bb.3, 0, $cpsr
bb.2:
bb.3:
- Bcc %bb.1, 0, %cpsr
+ Bcc %bb.1, 0, $cpsr
bb.4:
successors: %bb.1
- tBRIND %r1, 14, _
+ tBRIND $r1, 14, _
...
# We should only get bb.1 as successor to bb.1. No zero percent probability
@@ -27,7 +27,7 @@ body: |
# CHECK: bb.1:
# CHECK: successors: %bb.1(0x80000000)
# CHECK-NOT: %bb.2(0x00000000)
-# CHECK: tBRIND %r1, 1, %cpsr
+# CHECK: tBRIND $r1, 1, $cpsr
# CHECK: B %bb.1
#CHECK-NOT: bb.2:
Modified: llvm/trunk/test/CodeGen/ARM/ifcvt_simple_unanalyzable.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt_simple_unanalyzable.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ifcvt_simple_unanalyzable.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/ifcvt_simple_unanalyzable.mir Wed Jan 31 14:04:26 2018
@@ -3,7 +3,7 @@
name: foo
body: |
bb.0:
- Bcc %bb.2, 0, %cpsr
+ Bcc %bb.2, 0, $cpsr
bb.1:
successors:
@@ -11,7 +11,7 @@ body: |
bb.2:
successors:
- %sp = tADDspi %sp, 2, 14, _
+ $sp = tADDspi $sp, 2, 14, _
BX_RET 14, _
...
@@ -19,7 +19,7 @@ body: |
# CHECK: body: |
# CHECK: bb.0:
-# CHECK: %sp = tADDspi %sp, 2, 0, %cpsr
-# CHECK: BX_RET 0, %cpsr
-# CHECK: BX_RET 14, %noreg
+# CHECK: $sp = tADDspi $sp, 2, 0, $cpsr
+# CHECK: BX_RET 0, $cpsr
+# CHECK: BX_RET 14, $noreg
Modified: llvm/trunk/test/CodeGen/ARM/ifcvt_triangleWoCvtToNextEdge.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt_triangleWoCvtToNextEdge.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ifcvt_triangleWoCvtToNextEdge.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/ifcvt_triangleWoCvtToNextEdge.mir Wed Jan 31 14:04:26 2018
@@ -12,21 +12,21 @@ name: foo
body: |
bb.0:
- Bcc %bb.1, 1, %cpsr
+ Bcc %bb.1, 1, $cpsr
B %bb.2
bb.1:
- Bcc %bb.3, 0, %cpsr
+ Bcc %bb.3, 0, $cpsr
bb.2:
successors:
- tBL 14, %cpsr, @__stack_chk_fail
+ tBL 14, $cpsr, @__stack_chk_fail
bb.3:
successors:
- %sp = tADDspi %sp, 2, 14, _
- %sp = tADDspi %sp, 2, 14, _
- tTAILJMPdND @bar, 14, %cpsr
+ $sp = tADDspi $sp, 2, 14, _
+ $sp = tADDspi $sp, 2, 14, _
+ tTAILJMPdND @bar, 14, $cpsr
...
# bb.2 has no successors, presumably because __stack_chk_fail doesn't return,
@@ -38,15 +38,15 @@ body: |
# CHECK: bb.0:
# CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
-# CHECK: Bcc %bb.2, 1, %cpsr
+# CHECK: Bcc %bb.2, 1, $cpsr
# CHECK: bb.1:
# CHECK-NOT: successors: %bb
-# CHECK: tBL 14, %cpsr, @__stack_chk_fail
+# CHECK: tBL 14, $cpsr, @__stack_chk_fail
# CHECK: bb.2:
# CHECK-NOT: successors: %bb
-# CHECK: tBL 1, %cpsr, @__stack_chk_fail
-# CHECK: %sp = tADDspi %sp, 2, 14, %noreg
-# CHECK: %sp = tADDspi %sp, 2, 14, %noreg
-# CHECK: tTAILJMPdND @bar, 14, %cpsr
+# CHECK: tBL 1, $cpsr, @__stack_chk_fail
+# CHECK: $sp = tADDspi $sp, 2, 14, $noreg
+# CHECK: $sp = tADDspi $sp, 2, 14, $noreg
+# CHECK: tTAILJMPdND @bar, 14, $cpsr
Modified: llvm/trunk/test/CodeGen/ARM/imm-peephole-arm.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/imm-peephole-arm.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/imm-peephole-arm.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/imm-peephole-arm.mir Wed Jan 31 14:04:26 2018
@@ -1,6 +1,6 @@
# RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s
-# CHECK: [[IN:%.*]]:gprnopc = COPY %r0
+# CHECK: [[IN:%.*]]:gprnopc = COPY $r0
# CHECK: [[SUM1TMP:%.*]]:rgpr = ADDri [[IN]], 133
# CHECK: [[SUM1:%.*]]:rgpr = ADDri killed [[SUM1TMP]], 25600
@@ -35,25 +35,25 @@ registers:
- { id: 7, class: rgpr }
- { id: 8, class: rgpr }
liveins:
- - { reg: '%r0', virtual-reg: '%0' }
+ - { reg: '$r0', virtual-reg: '%0' }
body: |
bb.0 (%ir-block.0):
- liveins: %r0
+ liveins: $r0
- %0 = COPY %r0
+ %0 = COPY $r0
%1 = MOVi32imm -25733
- %2 = SUBrr %0, killed %1, 14, %noreg, %noreg
+ %2 = SUBrr %0, killed %1, 14, $noreg, $noreg
%3 = MOVi32imm 25733
- %4 = SUBrr %0, killed %3, 14, %noreg, %noreg
+ %4 = SUBrr %0, killed %3, 14, $noreg, $noreg
%5 = MOVi32imm -25733
- %6 = ADDrr %0, killed %5, 14, %noreg, %noreg
+ %6 = ADDrr %0, killed %5, 14, $noreg, $noreg
%7 = MOVi32imm 25733
- %8 = ADDrr killed %0, killed %7, 14, %noreg, %noreg
+ %8 = ADDrr killed %0, killed %7, 14, $noreg, $noreg
- %r0 = COPY killed %8
- BX_RET 14, %noreg, implicit %r0
+ $r0 = COPY killed %8
+ BX_RET 14, $noreg, implicit $r0
...
Modified: llvm/trunk/test/CodeGen/ARM/imm-peephole-thumb.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/imm-peephole-thumb.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/imm-peephole-thumb.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/imm-peephole-thumb.mir Wed Jan 31 14:04:26 2018
@@ -1,6 +1,6 @@
# RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s
-# CHECK: [[IN:%.*]]:gprnopc = COPY %r0
+# CHECK: [[IN:%.*]]:gprnopc = COPY $r0
# CHECK: [[SUM1TMP:%.*]]:rgpr = t2ADDri [[IN]], 25600
# CHECK: [[SUM1:%.*]]:rgpr = t2ADDri killed [[SUM1TMP]], 133
@@ -35,24 +35,24 @@ registers:
- { id: 7, class: rgpr }
- { id: 8, class: rgpr }
liveins:
- - { reg: '%r0', virtual-reg: '%0' }
+ - { reg: '$r0', virtual-reg: '%0' }
body: |
bb.0 (%ir-block.0):
- liveins: %r0
- %0 = COPY %r0
+ liveins: $r0
+ %0 = COPY $r0
%1 = t2MOVi32imm -25733
- %2 = t2SUBrr %0, killed %1, 14, %noreg, %noreg
+ %2 = t2SUBrr %0, killed %1, 14, $noreg, $noreg
%3 = t2MOVi32imm 25733
- %4 = t2SUBrr %0, killed %3, 14, %noreg, %noreg
+ %4 = t2SUBrr %0, killed %3, 14, $noreg, $noreg
%5 = t2MOVi32imm -25733
- %6= t2ADDrr %0, killed %5, 14, %noreg, %noreg
+ %6= t2ADDrr %0, killed %5, 14, $noreg, $noreg
%7 = t2MOVi32imm 25733
- %8 = t2ADDrr killed %0, killed %7, 14, %noreg, %noreg
+ %8 = t2ADDrr killed %0, killed %7, 14, $noreg, $noreg
- %r0 = COPY killed %8
- tBX_RET 14, %noreg, implicit %r0
+ $r0 = COPY killed %8
+ tBX_RET 14, $noreg, implicit $r0
...
Modified: llvm/trunk/test/CodeGen/ARM/load_store_opt_kill.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/load_store_opt_kill.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/load_store_opt_kill.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/load_store_opt_kill.mir Wed Jan 31 14:04:26 2018
@@ -2,11 +2,11 @@
---
# CHECK-LABEL: name: f
name: f
-# Make sure the load into %r0 doesn't clobber the base register before the second load uses it.
-# CHECK: %r3 = LDRi12 %r0, 12, 14, %noreg
-# CHECK-NEXT: %r0 = LDRi12 %r0, 8, 14, %noreg
+# Make sure the load into $r0 doesn't clobber the base register before the second load uses it.
+# CHECK: $r3 = LDRi12 $r0, 12, 14, $noreg
+# CHECK-NEXT: $r0 = LDRi12 $r0, 8, 14, $noreg
body: |
bb.0:
- liveins: %r0, %r3
- %r0, %r3 = LDRD %r0, %noreg, 8, 14, %noreg
+ liveins: $r0, $r3
+ $r0, $r3 = LDRD $r0, $noreg, 8, 14, $noreg
...
Modified: llvm/trunk/test/CodeGen/ARM/machine-copyprop.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/machine-copyprop.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/machine-copyprop.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/machine-copyprop.mir Wed Jan 31 14:04:26 2018
@@ -3,20 +3,20 @@
# Test that machine copy prop recognizes the implicit-def operands on a COPY
# as clobbering the register.
# CHECK-LABEL: name: func
-# CHECK: %d2 = VMOVv2i32 2, 14, %noreg
-# CHECK: %s5 = COPY %s0, implicit %q1, implicit-def %q1
-# CHECK: VST1q32 %r0, 0, %q1, 14, %noreg
+# CHECK: $d2 = VMOVv2i32 2, 14, $noreg
+# CHECK: $s5 = COPY $s0, implicit $q1, implicit-def $q1
+# CHECK: VST1q32 $r0, 0, $q1, 14, $noreg
# The following two COPYs must not be removed
-# CHECK: %s4 = COPY %s20, implicit-def %q1
-# CHECK: %s5 = COPY %s0, implicit killed %d0, implicit %q1, implicit-def %q1
-# CHECK: VST1q32 %r2, 0, %q1, 14, %noreg
+# CHECK: $s4 = COPY $s20, implicit-def $q1
+# CHECK: $s5 = COPY $s0, implicit killed $d0, implicit $q1, implicit-def $q1
+# CHECK: VST1q32 $r2, 0, $q1, 14, $noreg
name: func
body: |
bb.0:
- %d2 = VMOVv2i32 2, 14, %noreg
- %s5 = COPY %s0, implicit %q1, implicit-def %q1
- VST1q32 %r0, 0, %q1, 14, %noreg
- %s4 = COPY %s20, implicit-def %q1
- %s5 = COPY %s0, implicit killed %d0, implicit %q1, implicit-def %q1
- VST1q32 %r2, 0, %q1, 14, %noreg
+ $d2 = VMOVv2i32 2, 14, $noreg
+ $s5 = COPY $s0, implicit $q1, implicit-def $q1
+ VST1q32 $r0, 0, $q1, 14, $noreg
+ $s4 = COPY $s20, implicit-def $q1
+ $s5 = COPY $s0, implicit killed $d0, implicit $q1, implicit-def $q1
+ VST1q32 $r2, 0, $q1, 14, $noreg
...
Modified: llvm/trunk/test/CodeGen/ARM/misched-int-basic-thumb2.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/misched-int-basic-thumb2.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/misched-int-basic-thumb2.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/misched-int-basic-thumb2.mir Wed Jan 31 14:04:26 2018
@@ -42,57 +42,57 @@
# CHECK_SWIFT: Latency : 2
# CHECK_R52: Latency : 2
#
-# CHECK: SU(3): %3:rgpr = t2LDRi12 %2:rgpr, 0, 14, %noreg; mem:LD4[@g1](dereferenceable)
+# CHECK: SU(3): %3:rgpr = t2LDRi12 %2:rgpr, 0, 14, $noreg; mem:LD4[@g1](dereferenceable)
# CHECK_A9: Latency : 1
# CHECK_SWIFT: Latency : 3
# CHECK_R52: Latency : 4
#
-# CHECK : SU(6): %6 = t2ADDrr %3:rgpr, %3:rgpr, 14, %noreg, %noreg
+# CHECK : SU(6): %6 = t2ADDrr %3:rgpr, %3:rgpr, 14, $noreg, $noreg
# CHECK_A9: Latency : 1
# CHECK_SWIFT: Latency : 1
# CHECK_R52: Latency : 3
-# CHECK: SU(7): %7:rgpr = t2SDIV %6:rgpr, %5:rgpr, 14, %noreg
+# CHECK: SU(7): %7:rgpr = t2SDIV %6:rgpr, %5:rgpr, 14, $noreg
# CHECK_A9: Latency : 0
# CHECK_SWIFT: Latency : 14
# CHECK_R52: Latency : 8
-# CHECK: SU(8): t2STRi12 %7:rgpr, %2:rgpr, 0, 14, %noreg; mem:ST4[@g1]
+# CHECK: SU(8): t2STRi12 %7:rgpr, %2:rgpr, 0, 14, $noreg; mem:ST4[@g1]
# CHECK_A9: Latency : 1
# CHECK_SWIFT: Latency : 0
# CHECK_R52: Latency : 4
#
-# CHECK: SU(9): %8:rgpr = t2SMULBB %1:rgpr, %1:rgpr, 14, %noreg
+# CHECK: SU(9): %8:rgpr = t2SMULBB %1:rgpr, %1:rgpr, 14, $noreg
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 4
# CHECK_R52: Latency : 4
#
-# CHECK: SU(10): %9:rgpr = t2SMLABB %0:rgpr, %0:rgpr, %8:rgpr, 14, %noreg
+# CHECK: SU(10): %9:rgpr = t2SMLABB %0:rgpr, %0:rgpr, %8:rgpr, 14, $noreg
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 4
# CHECK_R52: Latency : 4
#
-# CHECK: SU(11): %10:rgpr = t2UXTH %9:rgpr, 0, 14, %noreg
+# CHECK: SU(11): %10:rgpr = t2UXTH %9:rgpr, 0, 14, $noreg
# CHECK_A9: Latency : 1
# CHECK_SWIFT: Latency : 1
# CHECK_R52: Latency : 3
#
-# CHECK: SU(12): %11:rgpr = t2MUL %10:rgpr, %7:rgpr, 14, %noreg
+# CHECK: SU(12): %11:rgpr = t2MUL %10:rgpr, %7:rgpr, 14, $noreg
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 4
# CHECK_R52: Latency : 4
#
-# CHECK: SU(13): %12:rgpr = t2MLA %11:rgpr, %11:rgpr, %11:rgpr, 14, %noreg
+# CHECK: SU(13): %12:rgpr = t2MLA %11:rgpr, %11:rgpr, %11:rgpr, 14, $noreg
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 4
# CHECK_R52: Latency : 4
#
-# CHECK: SU(14): %13:rgpr, %14:rgpr = t2UMULL %12:rgpr, %12:rgpr, 14, %noreg
+# CHECK: SU(14): %13:rgpr, %14:rgpr = t2UMULL %12:rgpr, %12:rgpr, 14, $noreg
# CHECK_A9: Latency : 3
# CHECK_SWIFT: Latency : 5
# CHECK_R52: Latency : 4
#
-# CHECK: SU(18): %19:rgpr, %20:rgpr = t2UMLAL %12:rgpr, %12:rgpr, %19:rgpr, %20:rgpr, 14, %noreg
+# CHECK: SU(18): %19:rgpr, %20:rgpr = t2UMLAL %12:rgpr, %12:rgpr, %19:rgpr, %20:rgpr, 14, $noreg
# CHECK_A9: Latency : 3
# CHECK_SWIFT: Latency : 7
# CHECK_R52: Latency : 4
@@ -129,8 +129,8 @@ registers:
- { id: 19, class: rgpr }
- { id: 20, class: rgpr }
liveins:
- - { reg: '%r0', virtual-reg: '%0' }
- - { reg: '%r1', virtual-reg: '%1' }
+ - { reg: '$r0', virtual-reg: '%0' }
+ - { reg: '$r1', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -147,29 +147,29 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %1 = COPY %r1
- %0 = COPY %r0
+ %1 = COPY $r1
+ %0 = COPY $r0
%2 = t2MOVi32imm @g1
- %3 = t2LDRi12 %2, 0, 14, %noreg :: (dereferenceable load 4 from @g1)
+ %3 = t2LDRi12 %2, 0, 14, $noreg :: (dereferenceable load 4 from @g1)
%4 = t2MOVi32imm @g2
- %5 = t2LDRi12 %4, 0, 14, %noreg :: (dereferenceable load 4 from @g2)
- %6 = t2ADDrr %3, %3, 14, %noreg, %noreg
- %7 = t2SDIV %6, %5, 14, %noreg
- t2STRi12 %7, %2, 0, 14, %noreg :: (store 4 into @g1)
- %8 = t2SMULBB %1, %1, 14, %noreg
- %9 = t2SMLABB %0, %0, %8, 14, %noreg
- %10 = t2UXTH %9, 0, 14, %noreg
- %11 = t2MUL %10, %7, 14, %noreg
- %12 = t2MLA %11, %11, %11, 14, %noreg
- %13, %14 = t2UMULL %12, %12, 14, %noreg
- %19, %16 = t2UMULL %13, %13, 14, %noreg
- %17 = t2MLA %13, %14, %16, 14, %noreg
- %20 = t2MLA %13, %14, %17, 14, %noreg
- %19, %20 = t2UMLAL %12, %12, %19, %20, 14, %noreg
- %r0 = COPY %19
- %r1 = COPY %20
- tBX_RET 14, %noreg, implicit %r0, implicit %r1
+ %5 = t2LDRi12 %4, 0, 14, $noreg :: (dereferenceable load 4 from @g2)
+ %6 = t2ADDrr %3, %3, 14, $noreg, $noreg
+ %7 = t2SDIV %6, %5, 14, $noreg
+ t2STRi12 %7, %2, 0, 14, $noreg :: (store 4 into @g1)
+ %8 = t2SMULBB %1, %1, 14, $noreg
+ %9 = t2SMLABB %0, %0, %8, 14, $noreg
+ %10 = t2UXTH %9, 0, 14, $noreg
+ %11 = t2MUL %10, %7, 14, $noreg
+ %12 = t2MLA %11, %11, %11, 14, $noreg
+ %13, %14 = t2UMULL %12, %12, 14, $noreg
+ %19, %16 = t2UMULL %13, %13, 14, $noreg
+ %17 = t2MLA %13, %14, %16, 14, $noreg
+ %20 = t2MLA %13, %14, %17, 14, $noreg
+ %19, %20 = t2UMLAL %12, %12, %19, %20, 14, $noreg
+ $r0 = COPY %19
+ $r1 = COPY %20
+ tBX_RET 14, $noreg, implicit $r0, implicit $r1
...
Modified: llvm/trunk/test/CodeGen/ARM/misched-int-basic.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/misched-int-basic.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/misched-int-basic.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/misched-int-basic.mir Wed Jan 31 14:04:26 2018
@@ -28,37 +28,37 @@
}
# CHECK: ********** MI Scheduling **********
-# CHECK: SU(2): %2:gpr = SMULBB %1:gpr, %1:gpr, 14, %noreg
+# CHECK: SU(2): %2:gpr = SMULBB %1:gpr, %1:gpr, 14, $noreg
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 4
# CHECK_R52: Latency : 4
#
-# CHECK: SU(3): %3:gprnopc = SMLABB %0:gprnopc, %0:gprnopc, %2:gpr, 14, %noreg
+# CHECK: SU(3): %3:gprnopc = SMLABB %0:gprnopc, %0:gprnopc, %2:gpr, 14, $noreg
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 4
# CHECK_R52: Latency : 4
#
-# CHECK: SU(4): %4:gprnopc = UXTH %3:gprnopc, 0, 14, %noreg
+# CHECK: SU(4): %4:gprnopc = UXTH %3:gprnopc, 0, 14, $noreg
# CHECK_A9: Latency : 1
# CHECK_SWIFT: Latency : 1
# CHECK_R52: Latency : 3
#
-# CHECK: SU(5): %5:gprnopc = MUL %4:gprnopc, %4:gprnopc, 14, %noreg, %noreg
+# CHECK: SU(5): %5:gprnopc = MUL %4:gprnopc, %4:gprnopc, 14, $noreg, $noreg
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 4
# CHECK_R52: Latency : 4
#
-# CHECK: SU(6): %6:gprnopc = MLA %5:gprnopc, %5:gprnopc, %5:gprnopc, 14, %noreg, %noreg
+# CHECK: SU(6): %6:gprnopc = MLA %5:gprnopc, %5:gprnopc, %5:gprnopc, 14, $noreg, $noreg
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 4
# CHECK_R52: Latency : 4
#
-# CHECK: SU(7): %7:gprnopc, %8:gprnopc = UMULL %6:gprnopc, %6:gprnopc, 14, %noreg, %noreg
+# CHECK: SU(7): %7:gprnopc, %8:gprnopc = UMULL %6:gprnopc, %6:gprnopc, 14, $noreg, $noreg
# CHECK_A9: Latency : 3
# CHECK_SWIFT: Latency : 5
# CHECK_R52: Latency : 4
#
-# CHECK: SU(11): %13:gpr, %14:gprnopc = UMLAL %6:gprnopc, %6:gprnopc, %13:gpr, %14:gprnopc, 14, %noreg, %noreg
+# CHECK: SU(11): %13:gpr, %14:gprnopc = UMLAL %6:gprnopc, %6:gprnopc, %13:gpr, %14:gprnopc, 14, $noreg, $noreg
# CHECK_SWIFT: Latency : 7
# CHECK_A9: Latency : 3
# CHECK_R52: Latency : 4
@@ -89,8 +89,8 @@ registers:
- { id: 13, class: gpr }
- { id: 14, class: gprnopc }
liveins:
- - { reg: '%r0', virtual-reg: '%0' }
- - { reg: '%r1', virtual-reg: '%1' }
+ - { reg: '$r0', virtual-reg: '%0' }
+ - { reg: '$r1', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -107,22 +107,22 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %1 = COPY %r1
- %0 = COPY %r0
- %2 = SMULBB %1, %1, 14, %noreg
- %3 = SMLABB %0, %0, %2, 14, %noreg
- %4 = UXTH %3, 0, 14, %noreg
- %5 = MUL %4, %4, 14, %noreg, %noreg
- %6 = MLA %5, %5, %5, 14, %noreg, %noreg
- %7, %8 = UMULL %6, %6, 14, %noreg, %noreg
- %13, %10 = UMULL %7, %7, 14, %noreg, %noreg
- %11 = MLA %7, %8, %10, 14, %noreg, %noreg
- %14 = MLA %7, %8, %11, 14, %noreg, %noreg
- %13, %14 = UMLAL %6, %6, %13, %14, 14, %noreg, %noreg
- %r0 = COPY %13
- %r1 = COPY %14
- BX_RET 14, %noreg, implicit %r0, implicit %r1
+ %1 = COPY $r1
+ %0 = COPY $r0
+ %2 = SMULBB %1, %1, 14, $noreg
+ %3 = SMLABB %0, %0, %2, 14, $noreg
+ %4 = UXTH %3, 0, 14, $noreg
+ %5 = MUL %4, %4, 14, $noreg, $noreg
+ %6 = MLA %5, %5, %5, 14, $noreg, $noreg
+ %7, %8 = UMULL %6, %6, 14, $noreg, $noreg
+ %13, %10 = UMULL %7, %7, 14, $noreg, $noreg
+ %11 = MLA %7, %8, %10, 14, $noreg, $noreg
+ %14 = MLA %7, %8, %11, 14, $noreg, $noreg
+ %13, %14 = UMLAL %6, %6, %13, %14, 14, $noreg, $noreg
+ $r0 = COPY %13
+ $r1 = COPY %14
+ BX_RET 14, $noreg, implicit $r0, implicit $r1
...
Modified: llvm/trunk/test/CodeGen/ARM/peephole-phi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/peephole-phi.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/peephole-phi.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/peephole-phi.mir Wed Jan 31 14:04:26 2018
@@ -7,39 +7,39 @@
# CHECK-LABEL: name: func
# CHECK: body: |
# CHECK: bb.0:
-# CHECK: Bcc %bb.2, 1, undef %cpsr
+# CHECK: Bcc %bb.2, 1, undef $cpsr
#
# CHECK: bb.1:
# CHECK: %0:dpr = IMPLICIT_DEF
-# CHECK: %1:gpr, %2:gpr = VMOVRRD %0, 14, %noreg
+# CHECK: %1:gpr, %2:gpr = VMOVRRD %0, 14, $noreg
# CHECK: B %bb.3
#
# CHECK: bb.2:
# CHECK: %3:spr = IMPLICIT_DEF
-# CHECK: %4:gpr = VMOVRS %3, 14, %noreg
+# CHECK: %4:gpr = VMOVRS %3, 14, $noreg
#
# CHECK: bb.3:
# CHECK: %5:gpr = PHI %1, %bb.1, %4, %bb.2
-# CHECK: %6:spr = VMOVSR %5, 14, %noreg
+# CHECK: %6:spr = VMOVSR %5, 14, $noreg
---
name: func0
tracksRegLiveness: true
body: |
bb.0:
- Bcc %bb.2, 1, undef %cpsr
+ Bcc %bb.2, 1, undef $cpsr
bb.1:
%0:dpr = IMPLICIT_DEF
- %1:gpr, %2:gpr = VMOVRRD %0:dpr, 14, %noreg
+ %1:gpr, %2:gpr = VMOVRRD %0:dpr, 14, $noreg
B %bb.3
bb.2:
%3:spr = IMPLICIT_DEF
- %4:gpr = VMOVRS %3:spr, 14, %noreg
+ %4:gpr = VMOVRS %3:spr, 14, $noreg
bb.3:
%5:gpr = PHI %1, %bb.1, %4, %bb.2
- %6:spr = VMOVSR %5, 14, %noreg
+ %6:spr = VMOVSR %5, 14, $noreg
...
# CHECK-LABEL: name: func1
@@ -50,20 +50,20 @@ name: func1
tracksRegLiveness: true
body: |
bb.0:
- Bcc %bb.2, 1, undef %cpsr
+ Bcc %bb.2, 1, undef $cpsr
bb.1:
%1:spr = IMPLICIT_DEF
- %0:gpr = VMOVRS %1, 14, %noreg
+ %0:gpr = VMOVRS %1, 14, $noreg
B %bb.3
bb.2:
%3:spr = IMPLICIT_DEF
- %2:gpr = VMOVRS %3:spr, 14, %noreg
+ %2:gpr = VMOVRS %3:spr, 14, $noreg
bb.3:
%4:gpr = PHI %0, %bb.1, %2, %bb.2
- %5:spr = VMOVSR %4, 14, %noreg
+ %5:spr = VMOVSR %4, 14, $noreg
...
# The current implementation doesn't perform any transformations if undef
@@ -71,33 +71,33 @@ body: |
# CHECK-LABEL: name: func-undefops
# CHECK: body: |
# CHECK: bb.0:
-# CHECK: Bcc %bb.2, 1, undef %cpsr
+# CHECK: Bcc %bb.2, 1, undef $cpsr
#
# CHECK: bb.1:
-# CHECK: %0:gpr = VMOVRS undef %1:spr, 14, %noreg
+# CHECK: %0:gpr = VMOVRS undef %1:spr, 14, $noreg
# CHECK: B %bb.3
#
# CHECK: bb.2:
-# CHECK: %2:gpr = VMOVRS undef %3:spr, 14, %noreg
+# CHECK: %2:gpr = VMOVRS undef %3:spr, 14, $noreg
#
# CHECK: bb.3:
# CHECK: %4:gpr = PHI %0, %bb.1, %2, %bb.2
-# CHECK: %5:spr = VMOVSR %4, 14, %noreg
+# CHECK: %5:spr = VMOVSR %4, 14, $noreg
---
name: func-undefops
tracksRegLiveness: true
body: |
bb.0:
- Bcc %bb.2, 1, undef %cpsr
+ Bcc %bb.2, 1, undef $cpsr
bb.1:
- %0:gpr = VMOVRS undef %1:spr, 14, %noreg
+ %0:gpr = VMOVRS undef %1:spr, 14, $noreg
B %bb.3
bb.2:
- %2:gpr = VMOVRS undef %3:spr, 14, %noreg
+ %2:gpr = VMOVRS undef %3:spr, 14, $noreg
bb.3:
%4:gpr = PHI %0, %bb.1, %2, %bb.2
- %5:spr = VMOVSR %4, 14, %noreg
+ %5:spr = VMOVSR %4, 14, $noreg
...
Modified: llvm/trunk/test/CodeGen/ARM/pei-swiftself.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/pei-swiftself.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/pei-swiftself.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/pei-swiftself.mir Wed Jan 31 14:04:26 2018
@@ -17,44 +17,44 @@ stack:
- { id: 1, type: default, size: 4096, alignment: 8 }
body: |
bb.0:
- liveins: %r10 ; swiftself parameter comes in as %r10
+ liveins: $r10 ; swiftself parameter comes in as $r10
; Bring up register pressure to force emergency spilling, coax scavenging
- ; to use %r10 as that one is not spilled/restored.
- %r0 = IMPLICIT_DEF
- %r1 = IMPLICIT_DEF
- %r2 = IMPLICIT_DEF
- %r3 = IMPLICIT_DEF
- %r4 = IMPLICIT_DEF
- %r5 = IMPLICIT_DEF
- %r6 = IMPLICIT_DEF
- %r7 = IMPLICIT_DEF
- %r8 = IMPLICIT_DEF
- %r9 = IMPLICIT_DEF
- %r11 = IMPLICIT_DEF
- %r12 = IMPLICIT_DEF
- %lr = IMPLICIT_DEF
+ ; to use $r10 as that one is not spilled/restored.
+ $r0 = IMPLICIT_DEF
+ $r1 = IMPLICIT_DEF
+ $r2 = IMPLICIT_DEF
+ $r3 = IMPLICIT_DEF
+ $r4 = IMPLICIT_DEF
+ $r5 = IMPLICIT_DEF
+ $r6 = IMPLICIT_DEF
+ $r7 = IMPLICIT_DEF
+ $r8 = IMPLICIT_DEF
+ $r9 = IMPLICIT_DEF
+ $r11 = IMPLICIT_DEF
+ $r12 = IMPLICIT_DEF
+ $lr = IMPLICIT_DEF
; Computing the large stack offset requires an extra register. We should
- ; not just use %r10 for that.
- ; CHECK-NOT: STRi12 %1,{{.*}}%r10
+ ; not just use $r10 for that.
+ ; CHECK-NOT: STRi12 %1,{{.*}}$r10
- STRi12 %r1, %stack.0, 0, 14, %noreg :: (store 4)
+ STRi12 $r1, %stack.0, 0, 14, $noreg :: (store 4)
; use the swiftself parameter value.
- KILL %r10
+ KILL $r10
- KILL %r0
- KILL %r1
- KILL %r2
- KILL %r3
- KILL %r4
- KILL %r5
- KILL %r6
- KILL %r7
- KILL %r8
- KILL %r9
- KILL %r11
- KILL %r12
- KILL %lr
+ KILL $r0
+ KILL $r1
+ KILL $r2
+ KILL $r3
+ KILL $r4
+ KILL $r5
+ KILL $r6
+ KILL $r7
+ KILL $r8
+ KILL $r9
+ KILL $r11
+ KILL $r12
+ KILL $lr
...
Modified: llvm/trunk/test/CodeGen/ARM/prera-ldst-aliasing.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/prera-ldst-aliasing.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/prera-ldst-aliasing.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/prera-ldst-aliasing.mir Wed Jan 31 14:04:26 2018
@@ -18,23 +18,23 @@ name: ldrd_strd_aa
alignment: 1
tracksRegLiveness: true
liveins:
- - { reg: '%r0', virtual-reg: '%0' }
- - { reg: '%r1', virtual-reg: '%1' }
+ - { reg: '$r0', virtual-reg: '%0' }
+ - { reg: '$r1', virtual-reg: '%1' }
body: |
bb.0.entry:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %1 : gpr = COPY %r1
- %0 : gpr = COPY %r0
- %2 : gpr = t2LDRi12 %1, 0, 14, %noreg :: (load 4 from %ir.y)
- t2STRi12 killed %2, %0, 0, 14, %noreg :: (store 4 into %ir.x)
- %3 : gpr = t2LDRi12 %1, 4, 14, %noreg :: (load 4 from %ir.arrayidx2)
- t2STRi12 killed %3, %0, 4, 14, %noreg :: (store 4 into %ir.arrayidx3)
+ %1 : gpr = COPY $r1
+ %0 : gpr = COPY $r0
+ %2 : gpr = t2LDRi12 %1, 0, 14, $noreg :: (load 4 from %ir.y)
+ t2STRi12 killed %2, %0, 0, 14, $noreg :: (store 4 into %ir.x)
+ %3 : gpr = t2LDRi12 %1, 4, 14, $noreg :: (load 4 from %ir.arrayidx2)
+ t2STRi12 killed %3, %0, 4, 14, $noreg :: (store 4 into %ir.arrayidx3)
; CHECK: t2LDRi12
; CHECK-NEXT: t2LDRi12
; CHECK-NEXT: t2STRi12
; CHECK-NEXT: t2STRi12
- tBX_RET 14, %noreg
+ tBX_RET 14, $noreg
...
Modified: llvm/trunk/test/CodeGen/ARM/prera-ldst-insertpt.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/prera-ldst-insertpt.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/prera-ldst-insertpt.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/prera-ldst-insertpt.mir Wed Jan 31 14:04:26 2018
@@ -18,24 +18,24 @@ name: a
alignment: 1
tracksRegLiveness: true
liveins:
- - { reg: '%r0', virtual-reg: '%0' }
- - { reg: '%r1', virtual-reg: '%1' }
- - { reg: '%r2', virtual-reg: '%2' }
+ - { reg: '$r0', virtual-reg: '%0' }
+ - { reg: '$r1', virtual-reg: '%1' }
+ - { reg: '$r2', virtual-reg: '%2' }
body: |
bb.0.entry:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %2 : rgpr = COPY %r2
- %1 : rgpr = COPY %r1
- %0 : gpr = COPY %r0
- %3 : rgpr = t2MUL %2, %2, 14, %noreg
- %4 : rgpr = t2MUL %1, %1, 14, %noreg
+ %2 : rgpr = COPY $r2
+ %1 : rgpr = COPY $r1
+ %0 : gpr = COPY $r0
+ %3 : rgpr = t2MUL %2, %2, 14, $noreg
+ %4 : rgpr = t2MUL %1, %1, 14, $noreg
%5 : rgpr = t2MOVi32imm -858993459
- %6 : rgpr, %7 : rgpr = t2UMULL killed %3, %5, 14, %noreg
- %8 : rgpr, %9 : rgpr = t2UMULL killed %4, %5, 14, %noreg
- t2STRi12 %1, %0, 0, 14, %noreg :: (store 4)
- %10 : rgpr = t2LSLri %2, 1, 14, %noreg, %noreg
- t2STRi12 killed %10, %0, 4, 14, %noreg :: (store 4)
+ %6 : rgpr, %7 : rgpr = t2UMULL killed %3, %5, 14, $noreg
+ %8 : rgpr, %9 : rgpr = t2UMULL killed %4, %5, 14, $noreg
+ t2STRi12 %1, %0, 0, 14, $noreg :: (store 4)
+ %10 : rgpr = t2LSLri %2, 1, 14, $noreg, $noreg
+ t2STRi12 killed %10, %0, 4, 14, $noreg :: (store 4)
; Make sure we move the paired stores next to each other, and
; insert them in an appropriate location.
@@ -44,38 +44,38 @@ body: |
; CHECK-NEXT: t2MOVi
; CHECK-NEXT: t2ADDrs
- %11 : rgpr = t2MOVi 55, 14, %noreg, %noreg
- %12 : gprnopc = t2ADDrs %11, killed %7, 19, 14, %noreg, %noreg
- t2STRi12 killed %12, %0, 16, 14, %noreg :: (store 4)
- %13 : gprnopc = t2ADDrs %11, killed %9, 19, 14, %noreg, %noreg
- t2STRi12 killed %13, %0, 20, 14, %noreg :: (store 4)
+ %11 : rgpr = t2MOVi 55, 14, $noreg, $noreg
+ %12 : gprnopc = t2ADDrs %11, killed %7, 19, 14, $noreg, $noreg
+ t2STRi12 killed %12, %0, 16, 14, $noreg :: (store 4)
+ %13 : gprnopc = t2ADDrs %11, killed %9, 19, 14, $noreg, $noreg
+ t2STRi12 killed %13, %0, 20, 14, $noreg :: (store 4)
; Make sure we move the paired stores next to each other.
; CHECK: t2STRi12 killed %12,
; CHECK-NEXT: t2STRi12 killed %13,
- tBX_RET 14, %noreg
+ tBX_RET 14, $noreg
---
# CHECK-LABEL: name: b
name: b
alignment: 1
tracksRegLiveness: true
liveins:
- - { reg: '%r0', virtual-reg: '%0' }
- - { reg: '%r1', virtual-reg: '%1' }
- - { reg: '%r2', virtual-reg: '%2' }
+ - { reg: '$r0', virtual-reg: '%0' }
+ - { reg: '$r1', virtual-reg: '%1' }
+ - { reg: '$r2', virtual-reg: '%2' }
body: |
bb.0.entry:
- liveins: %r0, %r1, %r2
+ liveins: $r0, $r1, $r2
- %2 : rgpr = COPY %r2
- %1 : rgpr = COPY %r1
- %0 : gpr = COPY %r0
- t2STRi12 %1, %0, 0, 14, %noreg :: (store 4)
- %10 : rgpr = t2LSLri %2, 1, 14, %noreg, %noreg
- t2STRi12 killed %10, %0, 4, 14, %noreg :: (store 4)
- %3 : rgpr = t2MUL %2, %2, 14, %noreg
- t2STRi12 %3, %0, 8, 14, %noreg :: (store 4)
+ %2 : rgpr = COPY $r2
+ %1 : rgpr = COPY $r1
+ %0 : gpr = COPY $r0
+ t2STRi12 %1, %0, 0, 14, $noreg :: (store 4)
+ %10 : rgpr = t2LSLri %2, 1, 14, $noreg, $noreg
+ t2STRi12 killed %10, %0, 4, 14, $noreg :: (store 4)
+ %3 : rgpr = t2MUL %2, %2, 14, $noreg
+ t2STRi12 %3, %0, 8, 14, $noreg :: (store 4)
; Make sure we move the paired stores next to each other, and
; insert them in an appropriate location.
@@ -85,21 +85,21 @@ body: |
; CHECK-NEXT: t2MUL
; CHECK-NEXT: t2MOVi32imm
- %4 : rgpr = t2MUL %1, %1, 14, %noreg
+ %4 : rgpr = t2MUL %1, %1, 14, $noreg
%5 : rgpr = t2MOVi32imm -858993459
- %6 : rgpr, %7 : rgpr = t2UMULL killed %3, %5, 14, %noreg
- %8 : rgpr, %9 : rgpr = t2UMULL killed %4, %5, 14, %noreg
- %10 : rgpr = t2LSLri %2, 1, 14, %noreg, %noreg
- %11 : rgpr = t2MOVi 55, 14, %noreg, %noreg
- %12 : gprnopc = t2ADDrs %11, killed %7, 19, 14, %noreg, %noreg
- t2STRi12 killed %12, %0, 16, 14, %noreg :: (store 4)
- %13 : gprnopc = t2ADDrs %11, killed %9, 19, 14, %noreg, %noreg
- t2STRi12 killed %13, %0, 20, 14, %noreg :: (store 4)
+ %6 : rgpr, %7 : rgpr = t2UMULL killed %3, %5, 14, $noreg
+ %8 : rgpr, %9 : rgpr = t2UMULL killed %4, %5, 14, $noreg
+ %10 : rgpr = t2LSLri %2, 1, 14, $noreg, $noreg
+ %11 : rgpr = t2MOVi 55, 14, $noreg, $noreg
+ %12 : gprnopc = t2ADDrs %11, killed %7, 19, 14, $noreg, $noreg
+ t2STRi12 killed %12, %0, 16, 14, $noreg :: (store 4)
+ %13 : gprnopc = t2ADDrs %11, killed %9, 19, 14, $noreg, $noreg
+ t2STRi12 killed %13, %0, 20, 14, $noreg :: (store 4)
; Make sure we move the paired stores next to each other.
; CHECK: t2STRi12 {{.*}}, 16
; CHECK-NEXT: t2STRi12 {{.*}}, 20
- tBX_RET 14, %noreg
+ tBX_RET 14, $noreg
...
Modified: llvm/trunk/test/CodeGen/ARM/scavenging.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/scavenging.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/scavenging.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/scavenging.mir Wed Jan 31 14:04:26 2018
@@ -3,64 +3,64 @@
# CHECK-LABEL: name: scavengebug0
# Make sure we are not spilling/using a physreg used in the very last
# instruction of the scavenging range.
-# CHECK-NOT: tSTRi {{.*}}%r0,{{.*}}%r0
-# CHECK-NOT: tSTRi {{.*}}%r1,{{.*}}%r1
-# CHECK-NOT: tSTRi {{.*}}%r2,{{.*}}%r2
-# CHECK-NOT: tSTRi {{.*}}%r3,{{.*}}%r3
-# CHECK-NOT: tSTRi {{.*}}%r4,{{.*}}%r4
-# CHECK-NOT: tSTRi {{.*}}%r5,{{.*}}%r5
-# CHECK-NOT: tSTRi {{.*}}%r6,{{.*}}%r6
-# CHECK-NOT: tSTRi {{.*}}%r7,{{.*}}%r7
+# CHECK-NOT: tSTRi {{.*}}$r0,{{.*}}$r0
+# CHECK-NOT: tSTRi {{.*}}$r1,{{.*}}$r1
+# CHECK-NOT: tSTRi {{.*}}$r2,{{.*}}$r2
+# CHECK-NOT: tSTRi {{.*}}$r3,{{.*}}$r3
+# CHECK-NOT: tSTRi {{.*}}$r4,{{.*}}$r4
+# CHECK-NOT: tSTRi {{.*}}$r5,{{.*}}$r5
+# CHECK-NOT: tSTRi {{.*}}$r6,{{.*}}$r6
+# CHECK-NOT: tSTRi {{.*}}$r7,{{.*}}$r7
name: scavengebug0
body: |
bb.0:
; Bring up register pressure to force emergency spilling
- %r0 = IMPLICIT_DEF
- %r1 = IMPLICIT_DEF
- %r2 = IMPLICIT_DEF
- %r3 = IMPLICIT_DEF
- %r4 = IMPLICIT_DEF
- %r5 = IMPLICIT_DEF
- %r6 = IMPLICIT_DEF
- %r7 = IMPLICIT_DEF
+ $r0 = IMPLICIT_DEF
+ $r1 = IMPLICIT_DEF
+ $r2 = IMPLICIT_DEF
+ $r3 = IMPLICIT_DEF
+ $r4 = IMPLICIT_DEF
+ $r5 = IMPLICIT_DEF
+ $r6 = IMPLICIT_DEF
+ $r7 = IMPLICIT_DEF
%0 : tgpr = IMPLICIT_DEF
- %0 = tADDhirr %0, %sp, 14, %noreg
- tSTRi %r0, %0, 0, 14, %noreg
+ %0 = tADDhirr %0, $sp, 14, $noreg
+ tSTRi $r0, %0, 0, 14, $noreg
%1 : tgpr = IMPLICIT_DEF
- %1 = tADDhirr %1, %sp, 14, %noreg
- tSTRi %r1, %1, 0, 14, %noreg
+ %1 = tADDhirr %1, $sp, 14, $noreg
+ tSTRi $r1, %1, 0, 14, $noreg
%2 : tgpr = IMPLICIT_DEF
- %2 = tADDhirr %2, %sp, 14, %noreg
- tSTRi %r2, %2, 0, 14, %noreg
+ %2 = tADDhirr %2, $sp, 14, $noreg
+ tSTRi $r2, %2, 0, 14, $noreg
%3 : tgpr = IMPLICIT_DEF
- %3 = tADDhirr %3, %sp, 14, %noreg
- tSTRi %r3, %3, 0, 14, %noreg
+ %3 = tADDhirr %3, $sp, 14, $noreg
+ tSTRi $r3, %3, 0, 14, $noreg
%4 : tgpr = IMPLICIT_DEF
- %4 = tADDhirr %4, %sp, 14, %noreg
- tSTRi %r4, %4, 0, 14, %noreg
+ %4 = tADDhirr %4, $sp, 14, $noreg
+ tSTRi $r4, %4, 0, 14, $noreg
%5 : tgpr = IMPLICIT_DEF
- %5 = tADDhirr %5, %sp, 14, %noreg
- tSTRi %r5, %5, 0, 14, %noreg
+ %5 = tADDhirr %5, $sp, 14, $noreg
+ tSTRi $r5, %5, 0, 14, $noreg
%6 : tgpr = IMPLICIT_DEF
- %6 = tADDhirr %6, %sp, 14, %noreg
- tSTRi %r6, %6, 0, 14, %noreg
+ %6 = tADDhirr %6, $sp, 14, $noreg
+ tSTRi $r6, %6, 0, 14, $noreg
%7 : tgpr = IMPLICIT_DEF
- %7 = tADDhirr %7, %sp, 14, %noreg
- tSTRi %r7, %7, 0, 14, %noreg
+ %7 = tADDhirr %7, $sp, 14, $noreg
+ tSTRi $r7, %7, 0, 14, $noreg
- KILL %r0
- KILL %r1
- KILL %r2
- KILL %r3
- KILL %r4
- KILL %r5
- KILL %r6
- KILL %r7
+ KILL $r0
+ KILL $r1
+ KILL $r2
+ KILL $r3
+ KILL $r4
+ KILL $r5
+ KILL $r6
+ KILL $r7
Modified: llvm/trunk/test/CodeGen/ARM/sched-it-debug-nodes.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/sched-it-debug-nodes.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/sched-it-debug-nodes.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/sched-it-debug-nodes.mir Wed Jan 31 14:04:26 2018
@@ -32,9 +32,9 @@
; debug value as KILL'ed, resulting in a DEBUG_VALUE node changing codegen! (or
; hopefully, triggering an assert).
- ; CHECK: BUNDLE implicit-def dead %itstate
- ; CHECK: * DBG_VALUE debug-use %r1, debug-use %noreg, !"u"
- ; CHECK-NOT: * DBG_VALUE killed %r1, %noreg, !"u"
+ ; CHECK: BUNDLE implicit-def dead $itstate
+ ; CHECK: * DBG_VALUE debug-use $r1, debug-use $noreg, !"u"
+ ; CHECK-NOT: * DBG_VALUE killed $r1, $noreg, !"u"
declare arm_aapcscc void @g(%struct.s*, i8*, i32) #1
@@ -92,24 +92,24 @@ alignment: 1
exposesReturnsTwice: false
tracksRegLiveness: true
liveins:
- - { reg: '%r0' }
- - { reg: '%r1' }
- - { reg: '%r2' }
- - { reg: '%r3' }
-calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13',
- '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4',
- '%r5', '%r6', '%r7', '%r8', '%r9', '%r10', '%r11',
- '%s16', '%s17', '%s18', '%s19', '%s20', '%s21',
- '%s22', '%s23', '%s24', '%s25', '%s26', '%s27',
- '%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11',
- '%d10_d12', '%d11_d13', '%d12_d14', '%d13_d15',
- '%q4_q5', '%q5_q6', '%q6_q7', '%q4_q5_q6_q7', '%r4_r5',
- '%r6_r7', '%r8_r9', '%r10_r11', '%d8_d9_d10', '%d9_d10_d11',
- '%d10_d11_d12', '%d11_d12_d13', '%d12_d13_d14',
- '%d13_d14_d15', '%d8_d10_d12', '%d9_d11_d13', '%d10_d12_d14',
- '%d11_d13_d15', '%d8_d10_d12_d14', '%d9_d11_d13_d15',
- '%d9_d10', '%d11_d12', '%d13_d14', '%d9_d10_d11_d12',
- '%d11_d12_d13_d14' ]
+ - { reg: '$r0' }
+ - { reg: '$r1' }
+ - { reg: '$r2' }
+ - { reg: '$r3' }
+calleeSavedRegisters: [ '$lr', '$d8', '$d9', '$d10', '$d11', '$d12', '$d13',
+ '$d14', '$d15', '$q4', '$q5', '$q6', '$q7', '$r4',
+ '$r5', '$r6', '$r7', '$r8', '$r9', '$r10', '$r11',
+ '$s16', '$s17', '$s18', '$s19', '$s20', '$s21',
+ '$s22', '$s23', '$s24', '$s25', '$s26', '$s27',
+ '$s28', '$s29', '$s30', '$s31', '$d8_d10', '$d9_d11',
+ '$d10_d12', '$d11_d13', '$d12_d14', '$d13_d15',
+ '$q4_q5', '$q5_q6', '$q6_q7', '$q4_q5_q6_q7', '$r4_r5',
+ '$r6_r7', '$r8_r9', '$r10_r11', '$d8_d9_d10', '$d9_d10_d11',
+ '$d10_d11_d12', '$d11_d12_d13', '$d12_d13_d14',
+ '$d13_d14_d15', '$d8_d10_d12', '$d9_d11_d13', '$d10_d12_d14',
+ '$d11_d13_d15', '$d8_d10_d12_d14', '$d9_d11_d13_d15',
+ '$d9_d10', '$d11_d12', '$d13_d14', '$d9_d10_d11_d12',
+ '$d11_d12_d13_d14' ]
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -125,33 +125,33 @@ frameInfo:
hasVAStart: false
hasMustTailInVarArgFunc: false
stack:
- - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr', callee-saved-restored: false }
- - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7' }
+ - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '$lr', callee-saved-restored: false }
+ - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '$r7' }
body: |
bb.0.entry:
- liveins: %r0, %r1, %r2, %r3, %lr, %r7
+ liveins: $r0, $r1, $r2, $r3, $lr, $r7
- DBG_VALUE debug-use %r0, debug-use %noreg, !18, !27, debug-location !28
- DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
- DBG_VALUE debug-use %r2, debug-use %noreg, !20, !27, debug-location !28
- DBG_VALUE debug-use %r3, debug-use %noreg, !21, !27, debug-location !28
- t2CMPri %r3, 4, 14, %noreg, implicit-def %cpsr, debug-location !31
- DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
- %r0 = t2MOVi -1, 3, %cpsr, %noreg, implicit undef %r0
- DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
- tBX_RET 3, %cpsr, implicit %r0, debug-location !34
- %sp = frame-setup t2STMDB_UPD %sp, 14, %noreg, killed %r7, killed %lr
+ DBG_VALUE debug-use $r0, debug-use $noreg, !18, !27, debug-location !28
+ DBG_VALUE debug-use $r1, debug-use $noreg, !19, !27, debug-location !28
+ DBG_VALUE debug-use $r2, debug-use $noreg, !20, !27, debug-location !28
+ DBG_VALUE debug-use $r3, debug-use $noreg, !21, !27, debug-location !28
+ t2CMPri $r3, 4, 14, $noreg, implicit-def $cpsr, debug-location !31
+ DBG_VALUE debug-use $r1, debug-use $noreg, !19, !27, debug-location !28
+ $r0 = t2MOVi -1, 3, $cpsr, $noreg, implicit undef $r0
+ DBG_VALUE debug-use $r1, debug-use $noreg, !19, !27, debug-location !28
+ tBX_RET 3, $cpsr, implicit $r0, debug-location !34
+ $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr
frame-setup CFI_INSTRUCTION def_cfa_offset 8
- frame-setup CFI_INSTRUCTION offset %lr, -4
- frame-setup CFI_INSTRUCTION offset %r7, -8
- DBG_VALUE debug-use %r0, debug-use %noreg, !18, !27, debug-location !28
- DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
- DBG_VALUE debug-use %r2, debug-use %noreg, !20, !27, debug-location !28
- DBG_VALUE debug-use %r3, debug-use %noreg, !21, !27, debug-location !28
- %r1 = tMOVr killed %r2, 14, %noreg, debug-location !32
- %r2 = tMOVr killed %r3, 14, %noreg, debug-location !32
- tBL 14, %noreg, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32
- %r0 = t2MOVi 0, 14, %noreg, %noreg
- %sp = t2LDMIA_RET %sp, 14, %noreg, def %r7, def %pc, implicit %r0
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r7, -8
+ DBG_VALUE debug-use $r0, debug-use $noreg, !18, !27, debug-location !28
+ DBG_VALUE debug-use $r1, debug-use $noreg, !19, !27, debug-location !28
+ DBG_VALUE debug-use $r2, debug-use $noreg, !20, !27, debug-location !28
+ DBG_VALUE debug-use $r3, debug-use $noreg, !21, !27, debug-location !28
+ $r1 = tMOVr killed $r2, 14, $noreg, debug-location !32
+ $r2 = tMOVr killed $r3, 14, $noreg, debug-location !32
+ tBL 14, $noreg, @g, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp, debug-location !32
+ $r0 = t2MOVi 0, 14, $noreg, $noreg
+ $sp = t2LDMIA_RET $sp, 14, $noreg, def $r7, def $pc, implicit $r0
...
Modified: llvm/trunk/test/CodeGen/ARM/single-issue-r52.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/single-issue-r52.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/single-issue-r52.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/single-issue-r52.mir Wed Jan 31 14:04:26 2018
@@ -20,13 +20,13 @@
# CHECK: ********** MI Scheduling **********
# CHECK: ScheduleDAGMILive::schedule starting
-# CHECK: SU(1): %1:qqpr = VLD4d8Pseudo %0:gpr, 8, 14, %noreg; mem:LD32[%A](align=8)
+# CHECK: SU(1): %1:qqpr = VLD4d8Pseudo %0:gpr, 8, 14, $noreg; mem:LD32[%A](align=8)
# CHECK: Latency : 8
# CHECK: Single Issue : true;
-# CHECK: SU(2): %4:dpr = VADDv8i8 %1.dsub_0:qqpr, %1.dsub_1:qqpr, 14, %noreg
+# CHECK: SU(2): %4:dpr = VADDv8i8 %1.dsub_0:qqpr, %1.dsub_1:qqpr, 14, $noreg
# CHECK: Latency : 5
# CHECK: Single Issue : false;
-# CHECK: SU(3): %5:gpr, %6:gpr = VMOVRRD %4:dpr, 14, %noreg
+# CHECK: SU(3): %5:gpr, %6:gpr = VMOVRRD %4:dpr, 14, $noreg
# CHECK: Latency : 4
# CHECK: Single Issue : false;
@@ -56,7 +56,7 @@ registers:
- { id: 5, class: gpr }
- { id: 6, class: gpr }
liveins:
- - { reg: '%r0', virtual-reg: '%0' }
+ - { reg: '$r0', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -73,14 +73,14 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0 (%ir-block.0):
- liveins: %r0
+ liveins: $r0
- %0 = COPY %r0
- %1 = VLD4d8Pseudo %0, 8, 14, %noreg :: (load 32 from %ir.A, align 8)
- %4 = VADDv8i8 %1.dsub_0, %1.dsub_1, 14, %noreg
- %5, %6 = VMOVRRD %4, 14, %noreg
- %r0 = COPY %5
- %r1 = COPY %6
- BX_RET 14, %noreg, implicit %r0, implicit killed %r1
+ %0 = COPY $r0
+ %1 = VLD4d8Pseudo %0, 8, 14, $noreg :: (load 32 from %ir.A, align 8)
+ %4 = VADDv8i8 %1.dsub_0, %1.dsub_1, 14, $noreg
+ %5, %6 = VMOVRRD %4, 14, $noreg
+ $r0 = COPY %5
+ $r1 = COPY %6
+ BX_RET 14, $noreg, implicit $r0, implicit killed $r1
...
Modified: llvm/trunk/test/CodeGen/ARM/tail-dup-bundle.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/tail-dup-bundle.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/tail-dup-bundle.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/tail-dup-bundle.mir Wed Jan 31 14:04:26 2018
@@ -2,35 +2,35 @@
---
# CHECK-LABEL: name: func
# Make sure the bundle gets duplicated correctly
-# CHECK: BUNDLE implicit-def dead %itstate, implicit-def %cpsr, implicit killed %r0, implicit killed %cpsr {
-# CHECK: t2IT 1, 24, implicit-def %itstate
-# CHECK: t2CMPri killed %r0, 9, 1, killed %cpsr, implicit-def %cpsr, implicit internal killed %itstate
+# CHECK: BUNDLE implicit-def dead $itstate, implicit-def $cpsr, implicit killed $r0, implicit killed $cpsr {
+# CHECK: t2IT 1, 24, implicit-def $itstate
+# CHECK: t2CMPri killed $r0, 9, 1, killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate
# CHECK: }
-# CHECK: BUNDLE implicit-def dead %itstate, implicit-def %cpsr, implicit killed %r0, implicit killed %cpsr {
-# CHECK: t2IT 1, 24, implicit-def %itstate
-# CHECK: t2CMPri killed %r0, 9, 1, killed %cpsr, implicit-def %cpsr, implicit internal killed %itstate
+# CHECK: BUNDLE implicit-def dead $itstate, implicit-def $cpsr, implicit killed $r0, implicit killed $cpsr {
+# CHECK: t2IT 1, 24, implicit-def $itstate
+# CHECK: t2CMPri killed $r0, 9, 1, killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate
# CHECK: }
name: func
tracksRegLiveness: true
body: |
bb.0:
- liveins: %r0, %lr, %r7
+ liveins: $r0, $lr, $r7
bb.1:
- liveins: %r0
+ liveins: $r0
- t2CMPri %r0, 32, 14, %noreg, implicit-def %cpsr
- BUNDLE implicit-def dead %itstate, implicit-def %cpsr, implicit killed %r0, implicit killed %cpsr {
- t2IT 1, 24, implicit-def %itstate
- t2CMPri killed %r0, 9, 1, killed %cpsr, implicit-def %cpsr, implicit internal killed %itstate
+ t2CMPri $r0, 32, 14, $noreg, implicit-def $cpsr
+ BUNDLE implicit-def dead $itstate, implicit-def $cpsr, implicit killed $r0, implicit killed $cpsr {
+ t2IT 1, 24, implicit-def $itstate
+ t2CMPri killed $r0, 9, 1, killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate
}
- t2Bcc %bb.3, 1, killed %cpsr
+ t2Bcc %bb.3, 1, killed $cpsr
bb.2:
- %r0 = IMPLICIT_DEF
- t2B %bb.1, 14, %noreg
+ $r0 = IMPLICIT_DEF
+ t2B %bb.1, 14, $noreg
bb.3:
- %r0 = IMPLICIT_DEF
- t2B %bb.1, 14, %noreg
+ $r0 = IMPLICIT_DEF
+ t2B %bb.1, 14, $noreg
...
Modified: llvm/trunk/test/CodeGen/ARM/thumb1-ldst-opt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/thumb1-ldst-opt.ll?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/thumb1-ldst-opt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/thumb1-ldst-opt.ll Wed Jan 31 14:04:26 2018
@@ -22,6 +22,6 @@ entry:
declare void @g(i32)
; CHECK-LABEL: name: foo
-; CHECK: [[BASE:%r[0-7]]], {{.*}} tADDi8
+; CHECK: [[BASE:\$r[0-7]]], {{.*}} tADDi8
; CHECK-NOT: [[BASE]] = tLDMIA_UPD {{.*}} [[BASE]]
; CHECK: tLDMIA killed [[BASE]], {{.*}} def [[BASE]]
Modified: llvm/trunk/test/CodeGen/ARM/v6-jumptable-clobber.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/v6-jumptable-clobber.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/v6-jumptable-clobber.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/v6-jumptable-clobber.mir Wed Jan 31 14:04:26 2018
@@ -12,7 +12,7 @@
# CHECK: JUMPTABLE_ADDRS
# CHECK-LABEL: name: bar
-# CHECK: tTBB_JT %pc, killed %r1
+# CHECK: tTBB_JT $pc, killed $r1
--- |
; ModuleID = 'simple.ll'
@@ -195,8 +195,8 @@ regBankSelected: false
selected: false
tracksRegLiveness: true
liveins:
- - { reg: '%r0' }
- - { reg: '%r1' }
+ - { reg: '$r0' }
+ - { reg: '$r1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -229,24 +229,24 @@ jumpTable:
body: |
bb.0 (%ir-block.0):
successors: %bb.2.d1(0x03c3c3c4), %bb.1(0x7c3c3c3c)
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %r2 = tLDRpci %const.0, 14, %noreg
- tSTRi killed %r2, killed %r1, 0, 14, %noreg :: (store 4 into %ir.addr)
- dead %r1 = SPACE 980, undef %r0
- %r0 = tUXTB killed %r0, 14, %noreg
- %r1, dead %cpsr = tSUBi3 killed %r0, 1, 14, %noreg
- tCMPi8 %r1, 25, 14, %noreg, implicit-def %cpsr
- tBcc %bb.2.d1, 8, killed %cpsr
+ $r2 = tLDRpci %const.0, 14, $noreg
+ tSTRi killed $r2, killed $r1, 0, 14, $noreg :: (store 4 into %ir.addr)
+ dead $r1 = SPACE 980, undef $r0
+ $r0 = tUXTB killed $r0, 14, $noreg
+ $r1, dead $cpsr = tSUBi3 killed $r0, 1, 14, $noreg
+ tCMPi8 $r1, 25, 14, $noreg, implicit-def $cpsr
+ tBcc %bb.2.d1, 8, killed $cpsr
bb.1 (%ir-block.0):
successors: %bb.3.d2(0x07c549d2), %bb.9.d8(0x07c549d2), %bb.4.d3(0x07c549d2), %bb.5.d4(0x07c549d2), %bb.6.d5(0x07c549d2), %bb.7.d6(0x07c549d2), %bb.8.d7(0x07c549d2), %bb.10.d9(0x07c549d2), %bb.11.d10(0x07c549d2), %bb.2.d1(0x03ab62db), %bb.12.d11(0x07c549d2), %bb.13.d12(0x07c549d2), %bb.14.d13(0x07c549d2), %bb.15.d14(0x07c549d2), %bb.16.d15(0x07c549d2), %bb.17.d16(0x07c549d2), %bb.18.d17(0x07c549d2)
- liveins: %r1
+ liveins: $r1
- %r0, dead %cpsr = tLSLri killed %r1, 2, 14, %noreg
- %r1 = tLEApcrelJT %jump-table.0, 14, %noreg
- %r0 = tLDRr killed %r1, killed %r0, 14, %noreg :: (load 4 from jump-table)
- tBR_JTr killed %r0, %jump-table.0
+ $r0, dead $cpsr = tLSLri killed $r1, 2, 14, $noreg
+ $r1 = tLEApcrelJT %jump-table.0, 14, $noreg
+ $r0 = tLDRr killed $r1, killed $r0, 14, $noreg :: (load 4 from jump-table)
+ tBR_JTr killed $r0, %jump-table.0
bb.3.d2:
@@ -293,8 +293,8 @@ regBankSelected: false
selected: false
tracksRegLiveness: true
liveins:
- - { reg: '%r0' }
- - { reg: '%r1' }
+ - { reg: '$r0' }
+ - { reg: '$r1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -327,23 +327,23 @@ jumpTable:
body: |
bb.0 (%ir-block.0):
successors: %bb.2.d1(0x03c3c3c4), %bb.1(0x7c3c3c3c)
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %r2 = tLDRpci %const.0, 14, %noreg
- tSTRi killed %r2, killed %r1, 0, 14, %noreg :: (store 4 into %ir.addr)
- %r0 = tUXTB killed %r0, 14, %noreg
- %r1, dead %cpsr = tSUBi3 killed %r0, 1, 14, %noreg
- tCMPi8 %r1, 25, 14, %noreg, implicit-def %cpsr
- tBcc %bb.2.d1, 8, killed %cpsr
+ $r2 = tLDRpci %const.0, 14, $noreg
+ tSTRi killed $r2, killed $r1, 0, 14, $noreg :: (store 4 into %ir.addr)
+ $r0 = tUXTB killed $r0, 14, $noreg
+ $r1, dead $cpsr = tSUBi3 killed $r0, 1, 14, $noreg
+ tCMPi8 $r1, 25, 14, $noreg, implicit-def $cpsr
+ tBcc %bb.2.d1, 8, killed $cpsr
bb.1 (%ir-block.0):
successors: %bb.3.d2(0x07c549d2), %bb.9.d8(0x07c549d2), %bb.4.d3(0x07c549d2), %bb.5.d4(0x07c549d2), %bb.6.d5(0x07c549d2), %bb.7.d6(0x07c549d2), %bb.8.d7(0x07c549d2), %bb.10.d9(0x07c549d2), %bb.11.d10(0x07c549d2), %bb.2.d1(0x03ab62db), %bb.12.d11(0x07c549d2), %bb.13.d12(0x07c549d2), %bb.14.d13(0x07c549d2), %bb.15.d14(0x07c549d2), %bb.16.d15(0x07c549d2), %bb.17.d16(0x07c549d2), %bb.18.d17(0x07c549d2)
- liveins: %r1
+ liveins: $r1
- %r0, dead %cpsr = tLSLri killed %r1, 2, 14, %noreg
- %r1 = tLEApcrelJT %jump-table.0, 14, %noreg
- %r0 = tLDRr killed %r1, killed %r0, 14, %noreg :: (load 4 from jump-table)
- tBR_JTr killed %r0, %jump-table.0
+ $r0, dead $cpsr = tLSLri killed $r1, 2, 14, $noreg
+ $r1 = tLEApcrelJT %jump-table.0, 14, $noreg
+ $r0 = tLDRr killed $r1, killed $r0, 14, $noreg :: (load 4 from jump-table)
+ tBR_JTr killed $r0, %jump-table.0
bb.3.d2:
Modified: llvm/trunk/test/CodeGen/ARM/virtregrewriter-subregliveness.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/virtregrewriter-subregliveness.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/virtregrewriter-subregliveness.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/virtregrewriter-subregliveness.mir Wed Jan 31 14:04:26 2018
@@ -22,18 +22,18 @@ registers:
- { id: 0, class: gprpair }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; That copy is being coalesced so we should use a KILL
; placeholder. If that's not a kill that means we probably
- ; not coalescing %0 and %r0_r1 and thus we are not testing
+ ; not coalescing %0 and $r0_r1 and thus we are not testing
; the problematic code anymore.
;
- ; CHECK: %r0 = KILL %r0, implicit killed %r0_r1, implicit-def %r0_r1
- ; CHECK-NEXT: %r1 = KILL %r1, implicit killed %r0_r1
- undef %0.gsub_0 = COPY %r0
- %0.gsub_1 = COPY %r1
- tBX_RET 14, %noreg, implicit %0
+ ; CHECK: $r0 = KILL $r0, implicit killed $r0_r1, implicit-def $r0_r1
+ ; CHECK-NEXT: $r1 = KILL $r1, implicit killed $r0_r1
+ undef %0.gsub_0 = COPY $r0
+ %0.gsub_1 = COPY $r1
+ tBX_RET 14, $noreg, implicit %0
...
@@ -48,14 +48,14 @@ registers:
- { id: 0, class: gprpair }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; r1 is not live through so check we are not implicitly using
; the big register.
- ; CHECK: %r0 = KILL %r0, implicit-def %r0_r1
+ ; CHECK: $r0 = KILL $r0, implicit-def $r0_r1
; CHECK-NEXT: tBX_RET
- undef %0.gsub_0 = COPY %r0
- tBX_RET 14, %noreg, implicit %0
+ undef %0.gsub_0 = COPY $r0
+ tBX_RET 14, $noreg, implicit %0
...
@@ -71,14 +71,14 @@ registers:
- { id: 0, class: gprpair }
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
; r1 is not live through so check we are not implicitly using
; the big register.
- ; CHECK: %r0 = KILL %r0, implicit-def %r1, implicit-def %r0_r1
+ ; CHECK: $r0 = KILL $r0, implicit-def $r1, implicit-def $r0_r1
; CHECK-NEXT: tBX_RET
- undef %0.gsub_0 = COPY %r0, implicit-def %r1
- tBX_RET 14, %noreg, implicit %0
+ undef %0.gsub_0 = COPY $r0, implicit-def $r1
+ tBX_RET 14, $noreg, implicit %0
...
Modified: llvm/trunk/test/CodeGen/ARM/vldm-liveness.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vldm-liveness.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vldm-liveness.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/vldm-liveness.mir Wed Jan 31 14:04:26 2018
@@ -21,20 +21,20 @@
name: foo
alignment: 1
liveins:
- - { reg: '%r0' }
+ - { reg: '$r0' }
body: |
bb.0 (%ir-block.0):
- liveins: %r0
+ liveins: $r0
- %s1 = VLDRS %r0, 1, 14, %noreg, implicit-def %q0 :: (load 4)
- %s3 = VLDRS %r0, 2, 14, %noreg, implicit killed %q0, implicit-def %q0 :: (load 4)
- ; CHECK: %s3 = VLDRS %r0, 2, 14, %noreg, implicit killed undef %q0, implicit-def %q0 :: (load 4)
+ $s1 = VLDRS $r0, 1, 14, $noreg, implicit-def $q0 :: (load 4)
+ $s3 = VLDRS $r0, 2, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4)
+ ; CHECK: $s3 = VLDRS $r0, 2, 14, $noreg, implicit killed undef $q0, implicit-def $q0 :: (load 4)
- %s0 = VLDRS %r0, 0, 14, %noreg, implicit killed %q0, implicit-def %q0 :: (load 4)
- ; CHECK: VLDMSIA %r0, 14, %noreg, def %s0, def %s1, implicit-def %noreg
+ $s0 = VLDRS $r0, 0, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4)
+ ; CHECK: VLDMSIA $r0, 14, $noreg, def $s0, def $s1, implicit-def $noreg
- %s2 = VLDRS killed %r0, 4, 14, %noreg, implicit killed %q0, implicit-def %q0 :: (load 4)
- ; CHECK: %s2 = VLDRS killed %r0, 4, 14, %noreg, implicit killed %q0, implicit-def %q0 :: (load 4)
+ $s2 = VLDRS killed $r0, 4, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4)
+ ; CHECK: $s2 = VLDRS killed $r0, 4, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4)
- tBX_RET 14, %noreg, implicit %q0
+ tBX_RET 14, $noreg, implicit $q0
...
Modified: llvm/trunk/test/CodeGen/BPF/sockex2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/BPF/sockex2.ll?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/BPF/sockex2.ll (original)
+++ llvm/trunk/test/CodeGen/BPF/sockex2.ll Wed Jan 31 14:04:26 2018
@@ -311,7 +311,7 @@ flow_dissector.exit.thread:
; CHECK-LABEL: bpf_prog2:
; CHECK: r0 = *(u16 *)skb[12] # encoding: [0x28,0x00,0x00,0x00,0x0c,0x00,0x00,0x00]
; CHECK: r0 = *(u16 *)skb[16] # encoding: [0x28,0x00,0x00,0x00,0x10,0x00,0x00,0x00]
-; CHECK: implicit-def: %r1
+; CHECK: implicit-def: $r1
; CHECK: r1 =
; CHECK: call 1 # encoding: [0x85,0x00,0x00,0x00,0x01,0x00,0x00,0x00]
; CHECK: call 2 # encoding: [0x85,0x00,0x00,0x00,0x02,0x00,0x00,0x00]
Modified: llvm/trunk/test/CodeGen/Hexagon/addrmode-globoff.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/addrmode-globoff.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/addrmode-globoff.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/addrmode-globoff.mir Wed Jan 31 14:04:26 2018
@@ -13,13 +13,13 @@ tracksRegLiveness: true
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
; Make sure that the offset in @g0 is 8.
- ; CHECK: S4_storerh_ur killed %r0, 2, @g0 + 8, %r0
+ ; CHECK: S4_storerh_ur killed $r0, 2, @g0 + 8, $r0
- %r1 = A2_tfrsi @g0+4
- %r2 = S2_addasl_rrri %r1, %r0, 2
- S2_storerh_io %r2, 4, %r0
+ $r1 = A2_tfrsi @g0+4
+ $r2 = S2_addasl_rrri $r1, $r0, 2
+ S2_storerh_io $r2, 4, $r0
...
Modified: llvm/trunk/test/CodeGen/Hexagon/addrmode-keepdeadphis.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/addrmode-keepdeadphis.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/addrmode-keepdeadphis.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/addrmode-keepdeadphis.mir Wed Jan 31 14:04:26 2018
@@ -14,17 +14,17 @@ tracksRegLiveness: true
body: |
bb.0:
- liveins: %p0
- %r0 = A2_tfrsi @g
- %r1 = A2_tfrsi 1
- %r2 = S2_addasl_rrri %r0, %r1, 1
- J2_jumpt %p0, %bb.2, implicit-def %pc
+ liveins: $p0
+ $r0 = A2_tfrsi @g
+ $r1 = A2_tfrsi 1
+ $r2 = S2_addasl_rrri $r0, $r1, 1
+ J2_jumpt $p0, %bb.2, implicit-def $pc
bb.1:
- liveins: %r0, %r2
- %r1 = A2_tfrsi 2
+ liveins: $r0, $r2
+ $r1 = A2_tfrsi 2
bb.2:
- liveins: %r0, %r2
- %r3 = L2_loadri_io %r2, 0
+ liveins: $r0, $r2
+ $r3 = L2_loadri_io $r2, 0
...
Modified: llvm/trunk/test/CodeGen/Hexagon/addrmode-rr-to-io.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/addrmode-rr-to-io.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/addrmode-rr-to-io.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/addrmode-rr-to-io.mir Wed Jan 31 14:04:26 2018
@@ -1,7 +1,7 @@
# RUN: llc -march=hexagon -run-pass amode-opt %s -o - | FileCheck %s
# This testcase used to crash.
-# CHECK: S2_storerb_io killed %r0, @var_i8, killed %r2
+# CHECK: S2_storerb_io killed $r0, @var_i8, killed $r2
--- |
define void @fred() { ret void }
@@ -13,10 +13,10 @@ name: fred
tracksRegLiveness: true
body: |
bb.0:
- liveins: %r0
- %r1 = A2_tfrsi @var_i8
- %r2 = A2_tfrsi 255
- S4_storerb_rr killed %r0, killed %r1, 0, killed %r2
- PS_jmpret %r31, implicit-def %pc
+ liveins: $r0
+ $r1 = A2_tfrsi @var_i8
+ $r2 = A2_tfrsi 255
+ S4_storerb_rr killed $r0, killed $r1, 0, killed $r2
+ PS_jmpret $r31, implicit-def $pc
...
Modified: llvm/trunk/test/CodeGen/Hexagon/anti-dep-partial.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/anti-dep-partial.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/anti-dep-partial.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/anti-dep-partial.mir Wed Jan 31 14:04:26 2018
@@ -13,22 +13,22 @@ tracksRegLiveness: true
body: |
bb.0:
successors:
- liveins: %r0, %r1, %d1, %d2, %r16, %r17, %r19, %r22, %r23
- %r2 = A2_add %r23, killed %r17
- %r6 = M2_mpyi %r16, %r16
- %r22 = M2_accii %r22, killed %r2, 2
- %r7 = A2_tfrsi 12345678
- %r3 = A2_tfr killed %r16
- %d2 = A2_tfrp killed %d0
- %r2 = L2_loadri_io %r29, 28
- %r2 = M2_mpyi killed %r6, killed %r2
- %r23 = S2_asr_i_r %r22, 31
- S2_storeri_io killed %r29, 0, killed %r7
+ liveins: $r0, $r1, $d1, $d2, $r16, $r17, $r19, $r22, $r23
+ $r2 = A2_add $r23, killed $r17
+ $r6 = M2_mpyi $r16, $r16
+ $r22 = M2_accii $r22, killed $r2, 2
+ $r7 = A2_tfrsi 12345678
+ $r3 = A2_tfr killed $r16
+ $d2 = A2_tfrp killed $d0
+ $r2 = L2_loadri_io $r29, 28
+ $r2 = M2_mpyi killed $r6, killed $r2
+ $r23 = S2_asr_i_r $r22, 31
+ S2_storeri_io killed $r29, 0, killed $r7
; The anti-dependency on r23 between the first A2_add and the
; S2_asr_i_r was causing d11 to be renamed, while r22 remained
; unchanged. Check that the renaming of d11 does not happen.
; CHECK: d11
- %d0 = A2_tfrp killed %d11
- J2_call @check, implicit-def %d0, implicit-def %d1, implicit-def %d2, implicit %d0, implicit %d1, implicit %d2
+ $d0 = A2_tfrp killed $d11
+ J2_call @check, implicit-def $d0, implicit-def $d1, implicit-def $d2, implicit $d0, implicit $d1, implicit $d2
...
Modified: llvm/trunk/test/CodeGen/Hexagon/bank-conflict-load.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bank-conflict-load.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/bank-conflict-load.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/bank-conflict-load.mir Wed Jan 31 14:04:26 2018
@@ -1,11 +1,11 @@
# RUN: llc -march=hexagon -run-pass post-RA-sched %s -o - | FileCheck %s
-# The two loads from %a (%r0) can cause a bank conflict. Check that they
+# The two loads from %a ($r0) can cause a bank conflict. Check that they
# are not scheduled next to each other.
-# CHECK: L2_loadri_io %r0, 8
-# CHECK: L2_loadri_io killed %r1, 0
-# CHECK: L2_loadri_io killed %r0, 12
+# CHECK: L2_loadri_io $r0, 8
+# CHECK: L2_loadri_io killed $r1, 0
+# CHECK: L2_loadri_io killed $r0, 12
--- |
define void @foo(i32* %a, i32* %b) {
@@ -19,10 +19,10 @@ tracksRegLiveness: true
body: |
bb.0:
- liveins: %r0, %r1
+ liveins: $r0, $r1
- %r2 = L2_loadri_io %r0, 8 :: (load 4 from %ir.a)
- %r3 = L2_loadri_io killed %r0, 12 :: (load 4 from %ir.a)
- %r4 = L2_loadri_io killed %r1, 0 :: (load 4 from %ir.b)
+ $r2 = L2_loadri_io $r0, 8 :: (load 4 from %ir.a)
+ $r3 = L2_loadri_io killed $r0, 12 :: (load 4 from %ir.a)
+ $r4 = L2_loadri_io killed $r1, 0 :: (load 4 from %ir.b)
...
Modified: llvm/trunk/test/CodeGen/Hexagon/branch-folder-hoist-kills.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/branch-folder-hoist-kills.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/branch-folder-hoist-kills.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/branch-folder-hoist-kills.mir Wed Jan 31 14:04:26 2018
@@ -21,10 +21,10 @@
# J2_jumpr %R31, implicit dead %PC
#
-# CHECK: %r1 = A2_sxth killed %r0
-# CHECK: %r0 = C2_cmoveit %p0, 2
-# CHECK-NOT: implicit-def %r0
-# CHECK: %r0 = C2_cmoveif killed %p0, 1, implicit killed %r0
+# CHECK: $r1 = A2_sxth killed $r0
+# CHECK: $r0 = C2_cmoveit $p0, 2
+# CHECK-NOT: implicit-def $r0
+# CHECK: $r0 = C2_cmoveif killed $p0, 1, implicit killed $r0
---
name: fred
@@ -32,28 +32,28 @@ tracksRegLiveness: true
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
successors: %bb.1, %bb.2
- A2_nop implicit-def %p0
- J2_jumpt killed %p0, %bb.2, implicit-def dead %pc
+ A2_nop implicit-def $p0
+ J2_jumpt killed $p0, %bb.2, implicit-def dead $pc
bb.1:
successors: %bb.3
- liveins: %r0
- %r1 = A2_sxth killed %r0
- %r0 = A2_tfrsi 1
- J2_jump %bb.3, implicit-def %pc
+ liveins: $r0
+ $r1 = A2_sxth killed $r0
+ $r0 = A2_tfrsi 1
+ J2_jump %bb.3, implicit-def $pc
bb.2:
successors: %bb.3
- liveins: %r0
- %r1 = A2_sxth killed %r0
- %r0 = A2_tfrsi 2
+ liveins: $r0
+ $r1 = A2_sxth killed $r0
+ $r0 = A2_tfrsi 2
bb.3:
- liveins: %r0, %r1
- %r0 = A2_add killed %r0, killed %r1
- J2_jumpr %r31, implicit-def dead %pc
+ liveins: $r0, $r1
+ $r0 = A2_add killed $r0, killed $r1
+ J2_jumpr $r31, implicit-def dead $pc
...
Modified: llvm/trunk/test/CodeGen/Hexagon/branchfolder-insert-impdef.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/branchfolder-insert-impdef.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/branchfolder-insert-impdef.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/branchfolder-insert-impdef.mir Wed Jan 31 14:04:26 2018
@@ -10,11 +10,11 @@
# CHECK-LABEL: name: func0
# CHECK-LABEL: bb.0:
-# CHECK: %r0 = IMPLICIT_DEF
+# CHECK: $r0 = IMPLICIT_DEF
# CHECK-LABEL: bb.1:
# CHECK-LABEL: bb.2:
-# CHECK: liveins: %r0
-# CHECK: PS_storerhabs 0, %r0
+# CHECK: liveins: $r0
+# CHECK: PS_storerhabs 0, $r0
# CHECK: PS_jmpret
---
@@ -23,36 +23,36 @@ tracksRegLiveness: true
body: |
bb.0:
- liveins: %r31
+ liveins: $r31
successors: %bb.1, %bb.2
- J2_jumpt undef %p0, %bb.2, implicit-def %pc
- J2_jump %bb.1, implicit-def %pc
+ J2_jumpt undef $p0, %bb.2, implicit-def $pc
+ J2_jump %bb.1, implicit-def $pc
bb.1:
- liveins: %r31
+ liveins: $r31
successors: %bb.3
- %r0 = L2_loadruh_io undef %r1, 0
- PS_storerhabs 0, killed %r0
- J2_jump %bb.3, implicit-def %pc
+ $r0 = L2_loadruh_io undef $r1, 0
+ PS_storerhabs 0, killed $r0
+ J2_jump %bb.3, implicit-def $pc
bb.2:
- liveins: %r31
+ liveins: $r31
successors: %bb.3
- PS_storerhabs 0, undef %r0
- J2_jump %bb.3, implicit-def %pc
+ PS_storerhabs 0, undef $r0
+ J2_jump %bb.3, implicit-def $pc
bb.3:
- liveins: %r31
- PS_jmpret killed %r31, implicit-def %pc
+ liveins: $r31
+ PS_jmpret killed $r31, implicit-def $pc
...
---
# CHECK-LABEL: name: func1
# CHECK-LABEL: bb.1:
-# CHECK: %r0 = IMPLICIT_DEF
+# CHECK: $r0 = IMPLICIT_DEF
# CHECK-LABEL: bb.2:
# CHECK-LABEL: bb.3:
-# CHECK: liveins: %r0
-# CHECK: PS_storerhabs 0, killed %r0
+# CHECK: liveins: $r0
+# CHECK: PS_storerhabs 0, killed $r0
# CHECK: PS_jmpret
name: func1
@@ -60,28 +60,28 @@ tracksRegLiveness: true
body: |
bb.0:
- liveins: %r31
+ liveins: $r31
successors: %bb.1, %bb.2
- J2_jumpt undef %p0, %bb.2, implicit-def %pc
- J2_jump %bb.1, implicit-def %pc
+ J2_jumpt undef $p0, %bb.2, implicit-def $pc
+ J2_jump %bb.1, implicit-def $pc
bb.1:
- liveins: %r31
+ liveins: $r31
successors: %bb.3
- %r1 = A2_tfrsi 1
- PS_storerhabs 0, undef %r0
- %r0 = A2_tfrsi 1
- J2_jump %bb.3, implicit-def %pc
+ $r1 = A2_tfrsi 1
+ PS_storerhabs 0, undef $r0
+ $r0 = A2_tfrsi 1
+ J2_jump %bb.3, implicit-def $pc
bb.2:
- liveins: %r31
+ liveins: $r31
successors: %bb.3
- %r0 = L2_loadruh_io undef %r1, 0
- PS_storerhabs 0, killed %r0
- %r0 = A2_tfrsi 1
- J2_jump %bb.3, implicit-def %pc
+ $r0 = L2_loadruh_io undef $r1, 0
+ PS_storerhabs 0, killed $r0
+ $r0 = A2_tfrsi 1
+ J2_jump %bb.3, implicit-def $pc
bb.3:
- liveins: %r31
- PS_jmpret killed %r31, implicit undef %r0, implicit-def %pc
+ liveins: $r31
+ PS_jmpret killed $r31, implicit undef $r0, implicit-def $pc
...
Modified: llvm/trunk/test/CodeGen/Hexagon/cext-opt-basic.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/cext-opt-basic.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/cext-opt-basic.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/cext-opt-basic.mir Wed Jan 31 14:04:26 2018
@@ -26,7 +26,7 @@ body: |
...
# CHECK-LABEL: name: test1
-# CHECK: [[C:%[0-9]+]]:intregs = COPY %r0
+# CHECK: [[C:%[0-9]+]]:intregs = COPY $r0
# CHECK: [[B:%[0-9]+]]:intregs = A2_addi [[C]], @global_address
# CHECK: L2_loadri_io [[B]], 0
# CHECK: L2_loadri_io [[B]], 4
@@ -40,20 +40,20 @@ registers:
- { id: 3, class: intregs }
body: |
bb.0:
- liveins: %r0
- %0 = COPY %r0
+ liveins: $r0
+ %0 = COPY $r0
%1 = L4_loadri_ur %0, 0, @global_address
%2 = L4_loadri_ur %0, 0, @global_address+4
%3 = L4_loadri_ur %0, 0, @global_address+8
...
# CHECK-LABEL: name: test2
-# CHECK: [[C:%[0-9]+]]:intregs = COPY %r0
+# CHECK: [[C:%[0-9]+]]:intregs = COPY $r0
# CHECK: [[B:%[0-9]+]]:intregs = A2_tfrsi @global_address + 4
# CHECK: [[T0:%[0-9]+]]:intregs = A2_addi [[B]], -4
-# CHECK: %r0 = COPY [[T0]]
+# CHECK: $r0 = COPY [[T0]]
# CHECK: [[T1:%[0-9]+]]:intregs = A2_addi [[B]], -2
-# CHECK: %r1 = COPY [[T1]]
+# CHECK: $r1 = COPY [[T1]]
# CHECK: L4_loadri_rr [[B]], [[C]], 0
---
name: test2
@@ -64,11 +64,11 @@ registers:
- { id: 3, class: intregs }
body: |
bb.0:
- liveins: %r0
- %0 = COPY %r0
+ liveins: $r0
+ %0 = COPY $r0
%1 = A2_tfrsi @global_address
- %r0 = COPY %1
+ $r0 = COPY %1
%2 = A2_tfrsi @global_address+2
- %r1 = COPY %2
+ $r1 = COPY %2
%3 = L4_loadri_ur %0, 0, @global_address+4
...
Modified: llvm/trunk/test/CodeGen/Hexagon/cext-opt-numops.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/cext-opt-numops.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/cext-opt-numops.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/cext-opt-numops.mir Wed Jan 31 14:04:26 2018
@@ -28,9 +28,9 @@ registers:
body: |
bb.0:
- liveins: %r0, %r1
- %0 = COPY %r1
- %1 = COPY %r0
+ liveins: $r0, $r1
+ %0 = COPY $r1
+ %1 = COPY $r0
%2 = A2_tfrsi @array
%3 = IMPLICIT_DEF
%4 = A2_tfrsi @array+424
@@ -41,5 +41,5 @@ body: |
%8 = A2_tfrsi @array+144
%9 = C2_mux %3, %4, %8
S4_storeiri_io %9, 0, 0
- PS_jmpret %r31, implicit-def %pc
+ PS_jmpret $r31, implicit-def $pc
...
Modified: llvm/trunk/test/CodeGen/Hexagon/cext-opt-range-assert.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/cext-opt-range-assert.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/cext-opt-range-assert.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/cext-opt-range-assert.mir Wed Jan 31 14:04:26 2018
@@ -22,12 +22,12 @@ body: |
%6:intregs = A2_tfrsi @G
%7:intregs = A2_addi killed %6, 2
%8:intregs = A2_tfrsi 127
- ADJCALLSTACKDOWN 0, 0, implicit-def %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
- %r0 = COPY %7
- %r1 = COPY %8
+ ADJCALLSTACKDOWN 0, 0, implicit-def $r29, implicit-def dead $r30, implicit $r31, implicit $r30, implicit $r29
+ $r0 = COPY %7
+ $r1 = COPY %8
%9:intregs = IMPLICIT_DEF
- J2_callr killed %9, implicit-def dead %pc, implicit-def dead %r31, implicit %r29, implicit %r0, implicit %r1, implicit-def %r29
- ADJCALLSTACKUP 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit-def dead %r31, implicit %r29
+ J2_callr killed %9, implicit-def dead $pc, implicit-def dead $r31, implicit $r29, implicit $r0, implicit $r1, implicit-def $r29
+ ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit-def dead $r31, implicit $r29
%5:intregs = A2_tfrsi 8
%10:intregs = A2_tfrsi @G + 8
%4:intregs = A2_addi killed %10, 2
@@ -39,16 +39,16 @@ body: |
%11:predregs = C2_cmpgtui %1, 127
%2:intregs = A2_addi %1, 8
%3:intregs = A2_addi %0, 16
- J2_jumpf %11, %bb.1, implicit-def %pc
+ J2_jumpf %11, %bb.1, implicit-def $pc
bb.2:
%13:intregs = A2_tfrsi @G
%14:intregs = A2_addi killed %13, 2
%15:intregs = A2_tfrsi 127
- ADJCALLSTACKDOWN 0, 0, implicit-def %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
- %r0 = COPY %14
- %r1 = COPY %15
+ ADJCALLSTACKDOWN 0, 0, implicit-def $r29, implicit-def dead $r30, implicit $r31, implicit $r30, implicit $r29
+ $r0 = COPY %14
+ $r1 = COPY %15
%16:intregs = IMPLICIT_DEF
- PS_callr_nr killed %16, implicit %r0, implicit %r1, implicit-def %r29
- ADJCALLSTACKUP 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit-def dead %r31, implicit %r29
+ PS_callr_nr killed %16, implicit $r0, implicit $r1, implicit-def $r29
+ ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit-def dead $r31, implicit $r29
...
Modified: llvm/trunk/test/CodeGen/Hexagon/cext-opt-range-offset.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/cext-opt-range-offset.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/cext-opt-range-offset.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/cext-opt-range-offset.mir Wed Jan 31 14:04:26 2018
@@ -29,8 +29,8 @@ body: |
bb.2:
successors: %bb.3, %bb.4
%4 = IMPLICIT_DEF
- J2_jumpt %4, %bb.4, implicit-def %pc
- J2_jump %bb.3, implicit-def %pc
+ J2_jumpt %4, %bb.4, implicit-def $pc
+ J2_jump %bb.3, implicit-def $pc
bb.3:
successors: %bb.4
Modified: llvm/trunk/test/CodeGen/Hexagon/cext-opt-shifted-range.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/cext-opt-shifted-range.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/cext-opt-shifted-range.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/cext-opt-shifted-range.mir Wed Jan 31 14:04:26 2018
@@ -22,8 +22,8 @@ name: fred
tracksRegLiveness: true
body: |
bb.0:
- liveins: %r0
- %0:intregs = COPY %r0
+ liveins: $r0
+ %0:intregs = COPY $r0
%1:intregs = S4_ori_asl_ri 2, %0, 1
%2:doubleregs = A2_tfrpi 0
S2_storerd_io %1, @array + 174, %2
Modified: llvm/trunk/test/CodeGen/Hexagon/duplex-addi-global-imm.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/duplex-addi-global-imm.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/duplex-addi-global-imm.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/duplex-addi-global-imm.mir Wed Jan 31 14:04:26 2018
@@ -15,8 +15,8 @@ tracksRegLiveness: true
body: |
bb.0:
- liveins: %r0
- %r0 = A2_addi %r0, @g
- %r1 = A2_tfrsi 0
+ liveins: $r0
+ $r0 = A2_addi $r0, @g
+ $r1 = A2_tfrsi 0
...
Modified: llvm/trunk/test/CodeGen/Hexagon/early-if-debug.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/early-if-debug.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/early-if-debug.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/early-if-debug.mir Wed Jan 31 14:04:26 2018
@@ -3,14 +3,14 @@
# if-converted.
# CHECK-LABEL: bb.0:
-# CHECK: %0:intregs = COPY %r0
+# CHECK: %0:intregs = COPY $r0
# CHECK: %1:predregs = C2_cmpeqi %0, 0
# CHECK: %2:intregs = A2_tfrsi 123
-# CHECK: DBG_VALUE debug-use %0, debug-use %noreg
-# CHECK: DBG_VALUE debug-use %0, debug-use %noreg
-# CHECK: DBG_VALUE debug-use %0, debug-use %noreg
-# CHECK: DBG_VALUE debug-use %0, debug-use %noreg
-# CHECK: DBG_VALUE debug-use %0, debug-use %noreg
+# CHECK: DBG_VALUE debug-use %0, debug-use $noreg
+# CHECK: DBG_VALUE debug-use %0, debug-use $noreg
+# CHECK: DBG_VALUE debug-use %0, debug-use $noreg
+# CHECK: DBG_VALUE debug-use %0, debug-use $noreg
+# CHECK: DBG_VALUE debug-use %0, debug-use $noreg
# CHECK: %3:intregs = A2_tfrsi 321
# CHECK: %5:intregs = C2_mux %1, %2, %3
@@ -31,20 +31,20 @@ registers:
- { id: 4, class: intregs }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
- %0 = COPY %r0
+ %0 = COPY $r0
%1 = C2_cmpeqi %0, 0
%2 = A2_tfrsi 123
- J2_jumpt %1, %bb.2, implicit-def dead %pc
- J2_jump %bb.1, implicit-def dead %pc
+ J2_jumpt %1, %bb.2, implicit-def dead $pc
+ J2_jump %bb.1, implicit-def dead $pc
bb.1:
- DBG_VALUE debug-use %0, debug-use %noreg, !1, !1
- DBG_VALUE debug-use %0, debug-use %noreg, !1, !1
- DBG_VALUE debug-use %0, debug-use %noreg, !1, !1
- DBG_VALUE debug-use %0, debug-use %noreg, !1, !1
- DBG_VALUE debug-use %0, debug-use %noreg, !1, !1
+ DBG_VALUE debug-use %0, debug-use $noreg, !1, !1
+ DBG_VALUE debug-use %0, debug-use $noreg, !1, !1
+ DBG_VALUE debug-use %0, debug-use $noreg, !1, !1
+ DBG_VALUE debug-use %0, debug-use $noreg, !1, !1
+ DBG_VALUE debug-use %0, debug-use $noreg, !1, !1
%3 = A2_tfrsi 321
bb.2:
Modified: llvm/trunk/test/CodeGen/Hexagon/expand-condsets-def-undef.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/expand-condsets-def-undef.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/expand-condsets-def-undef.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/expand-condsets-def-undef.mir Wed Jan 31 14:04:26 2018
@@ -21,16 +21,16 @@ registers:
- { id: 2, class: doubleregs }
- { id: 3, class: intregs }
liveins:
- - { reg: '%p0', virtual-reg: '%0' }
- - { reg: '%r0', virtual-reg: '%1' }
- - { reg: '%d0', virtual-reg: '%2' }
+ - { reg: '$p0', virtual-reg: '%0' }
+ - { reg: '$r0', virtual-reg: '%1' }
+ - { reg: '$d0', virtual-reg: '%2' }
body: |
bb.0:
- liveins: %r0, %d0, %p0
- %0 = COPY %p0
- %1 = COPY %r0
- %2 = COPY %d0
+ liveins: $r0, $d0, $p0
+ %0 = COPY $p0
+ %1 = COPY $r0
+ %2 = COPY $d0
; Check that this instruction is unchanged (remains unpredicated)
; CHECK: %3:intregs = A2_addi %2.isub_hi, 1
%3 = A2_addi %2.isub_hi, 1
Modified: llvm/trunk/test/CodeGen/Hexagon/expand-condsets-imm.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/expand-condsets-imm.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/expand-condsets-imm.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/expand-condsets-imm.mir Wed Jan 31 14:04:26 2018
@@ -17,5 +17,5 @@ body: |
bb.1:
%1 = IMPLICIT_DEF
%1 = C2_muxir undef %0, %1, @G
- %r0 = COPY %1
+ $r0 = COPY %1
...
Modified: llvm/trunk/test/CodeGen/Hexagon/expand-condsets-impuse.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/expand-condsets-impuse.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/expand-condsets-impuse.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/expand-condsets-impuse.mir Wed Jan 31 14:04:26 2018
@@ -28,17 +28,17 @@ registers:
- { id: 14, class: intregs }
- { id: 99, class: intregs }
liveins:
- - { reg: '%r0', virtual-reg: '%99' }
+ - { reg: '$r0', virtual-reg: '%99' }
body: |
bb.0:
- liveins: %r0
+ liveins: $r0
successors: %bb.298, %bb.301
- %99 = COPY %r0
- J2_jumpr %99, implicit-def %pc
+ %99 = COPY $r0
+ J2_jumpr %99, implicit-def $pc
bb.298:
- liveins: %r0
+ liveins: $r0
successors: %bb.299, %bb.301, %bb.309
%0 = A2_tfrsi 123
%1 = A2_tfrsi -1
@@ -46,7 +46,7 @@ body: |
%4 = C2_cmpeqi %3, 33
%5 = A2_tfrsi -2
%6 = C2_mux %4, %5, %1
- J2_jumpr %6, implicit-def %pc
+ J2_jumpr %6, implicit-def $pc
bb.299:
successors: %bb.300, %bb.309
@@ -55,12 +55,12 @@ body: |
%9 = A2_tfrsi -999
; CHECK: %10:intregs = C2_cmoveit killed %8, -999, implicit %10
%10 = C2_mux %8, %9, %1
- J2_jumpr %10, implicit-def %pc
+ J2_jumpr %10, implicit-def $pc
bb.300:
successors: %bb.309
S2_storeri_io %99, 0, %0
- J2_jump %bb.309, implicit-def %pc
+ J2_jump %bb.309, implicit-def $pc
bb.301:
successors: %bb.299, %bb.309
@@ -70,7 +70,7 @@ body: |
%12 = C2_cmpeqi %11, 33
%13 = A2_tfrsi -2
%14 = C2_mux %12, %13, %1
- J2_jumpr %14, implicit-def %pc
+ J2_jumpr %14, implicit-def $pc
bb.309:
Modified: llvm/trunk/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir Wed Jan 31 14:04:26 2018
@@ -27,23 +27,23 @@ registers:
- { id: 3, class: intregs }
- { id: 4, class: intregs }
liveins:
- - { reg: '%r0', virtual-reg: '%0' }
- - { reg: '%r1', virtual-reg: '%1' }
- - { reg: '%p0', virtual-reg: '%2' }
+ - { reg: '$r0', virtual-reg: '%0' }
+ - { reg: '$r1', virtual-reg: '%1' }
+ - { reg: '$p0', virtual-reg: '%2' }
body: |
bb.0:
- liveins: %r0, %r1, %p0
- %0 = COPY %r0
- %0 = COPY %r0 ; Force isSSA = false.
- %1 = COPY %r1
- %2 = COPY %p0
+ liveins: $r0, $r1, $p0
+ %0 = COPY $r0
+ %0 = COPY $r0 ; Force isSSA = false.
+ %1 = COPY $r1
+ %2 = COPY $p0
; Check that %3 was coalesced into %4.
; CHECK: %4:intregs = A2_abs %1
; CHECK: %4:intregs = A2_tfrt killed %2, killed %0, implicit %4
%3 = A2_abs %1
%4 = C2_mux %2, %0, %3
- %r0 = COPY %4
- J2_jumpr %r31, implicit %r0, implicit-def %pc
+ $r0 = COPY %4
+ J2_jumpr $r31, implicit $r0, implicit-def $pc
...
Modified: llvm/trunk/test/CodeGen/Hexagon/expand-condsets-same-inputs.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/expand-condsets-same-inputs.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/expand-condsets-same-inputs.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/expand-condsets-same-inputs.mir Wed Jan 31 14:04:26 2018
@@ -18,15 +18,15 @@ registers:
body: |
bb.0:
- liveins: %r0, %r1, %r2, %p0
- %0 = COPY %p0
- %0 = COPY %p0 ; Cheat: convince MIR parser that this is not SSA.
- %1 = COPY %r1
+ liveins: $r0, $r1, $r2, $p0
+ %0 = COPY $p0
+ %0 = COPY $p0 ; Cheat: convince MIR parser that this is not SSA.
+ %1 = COPY $r1
; Make sure we do not expand/predicate a mux with identical inputs.
; CHECK-NOT: A2_paddit
%2 = A2_addi %1, 1
%3 = C2_mux %0, killed %2, %2
- %r0 = COPY %3
+ $r0 = COPY %3
...
Modified: llvm/trunk/test/CodeGen/Hexagon/hwloop-redef-imm.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/hwloop-redef-imm.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/hwloop-redef-imm.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/hwloop-redef-imm.mir Wed Jan 31 14:04:26 2018
@@ -40,11 +40,11 @@ registers:
- { id: 8, class: predregs }
body: |
bb.0.b0:
- liveins: %r0
+ liveins: $r0
successors: %bb.1
%0 = A2_tfrsi 0
%1 = A2_tfrsi 0
- %2 = COPY %r0
+ %2 = COPY $r0
bb.1.b1:
successors: %bb.1, %bb.2
@@ -56,8 +56,8 @@ body: |
; This definition of %7 should not prevent conversion to hardware loop.
%7 = A2_tfrsi 3840
%8 = C2_cmpeq %5, %7
- J2_jumpf %8, %bb.1, implicit-def %pc
- J2_jump %bb.2, implicit-def %pc
+ J2_jumpf %8, %bb.1, implicit-def $pc
+ J2_jump %bb.2, implicit-def $pc
bb.2.b2:
...
Modified: llvm/trunk/test/CodeGen/Hexagon/ifcvt-common-kill.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/ifcvt-common-kill.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/ifcvt-common-kill.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/ifcvt-common-kill.mir Wed Jan 31 14:04:26 2018
@@ -1,7 +1,7 @@
# RUN: llc -march=hexagon -run-pass if-converter -o - %s -verify-machineinstrs | FileCheck %s
-# CHECK: %r26 = A2_tfr %r1
-# CHECK: S2_pstorerhf_io undef %p0, undef %r0, 0, killed %r1
+# CHECK: $r26 = A2_tfr $r1
+# CHECK: S2_pstorerhf_io undef $p0, undef $r0, 0, killed $r1
---
name: foo
@@ -9,26 +9,26 @@ tracksRegLiveness: true
body: |
bb.0:
successors: %bb.1, %bb.2
- liveins: %r0, %r1
- J2_jumpf undef %p0, %bb.2, implicit-def %pc
+ liveins: $r0, $r1
+ J2_jumpf undef $p0, %bb.2, implicit-def $pc
bb.1:
successors: %bb.3
- liveins: %r1
+ liveins: $r1
; This <kill> flag should be cleared. It didn't use to be, because
; this instruction is treated as a duplicate of the corresponding
; instruction from the "false" block bb.2. Clearing of the <kill>
; flags was limited to the non-common part of the "true" block.
- %r26 = A2_tfr killed %r1
- J2_jump %bb.3, implicit-def %pc
+ $r26 = A2_tfr killed $r1
+ J2_jump %bb.3, implicit-def $pc
bb.2:
successors: %bb.3
- liveins: %r1
- %r26 = A2_tfr %r1
- S2_storerh_io undef %r0, 0, killed %r1
- J2_jump %bb.3, implicit-def %pc
+ liveins: $r1
+ $r26 = A2_tfr $r1
+ S2_storerh_io undef $r0, 0, killed $r1
+ J2_jump %bb.3, implicit-def $pc
bb.3:
- liveins: %r26
+ liveins: $r26
...
Modified: llvm/trunk/test/CodeGen/Hexagon/ifcvt-impuse-livein.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/ifcvt-impuse-livein.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/ifcvt-impuse-livein.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/ifcvt-impuse-livein.mir Wed Jan 31 14:04:26 2018
@@ -17,26 +17,26 @@ tracksRegLiveness: true
body: |
bb.0:
successors: %bb.1, %bb.2
- liveins: %r0, %r2, %p1
- J2_jumpf %p1, %bb.1, implicit-def %pc
- J2_jump %bb.2, implicit-def %pc
+ liveins: $r0, $r2, $p1
+ J2_jumpf $p1, %bb.1, implicit-def $pc
+ J2_jump %bb.2, implicit-def $pc
bb.1:
successors: %bb.3
- liveins: %r2
- %r0 = A2_tfrsi 2
- J2_jump %bb.3, implicit-def %pc
+ liveins: $r2
+ $r0 = A2_tfrsi 2
+ J2_jump %bb.3, implicit-def $pc
bb.2:
successors: %bb.3
- liveins: %r0
+ liveins: $r0
; Even though r2 was not live on entry to this block, it was live across
; block bb.1 in the original diamond. After if-conversion, the diamond
; became a single block, and so r2 is now live on entry to the instructions
; originating from bb.2.
- ; CHECK: %r2 = C2_cmoveit %p1, 1, implicit killed %r2
- %r2 = A2_tfrsi 1
+ ; CHECK: $r2 = C2_cmoveit $p1, 1, implicit killed $r2
+ $r2 = A2_tfrsi 1
bb.3:
- liveins: %r0, %r2
- %r0 = A2_add %r0, %r2
- J2_jumpr %r31, implicit-def %pc
+ liveins: $r0, $r2
+ $r0 = A2_add $r0, $r2
+ J2_jumpr $r31, implicit-def $pc
...
Modified: llvm/trunk/test/CodeGen/Hexagon/ifcvt-live-subreg.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/ifcvt-live-subreg.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/ifcvt-live-subreg.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/ifcvt-live-subreg.mir Wed Jan 31 14:04:26 2018
@@ -6,10 +6,10 @@
# Verify the predicated block:
# CHECK-LABEL: bb.0:
-# CHECK: liveins: %r0, %r1, %p0, %d8
-# CHECK: %d8 = A2_combinew killed %r0, killed %r1
-# CHECK: %d8 = L2_ploadrdf_io %p0, %r29, 0, implicit killed %d8
-# CHECK: J2_jumprf killed %p0, %r31, implicit-def %pc, implicit-def %pc, implicit %d8
+# CHECK: liveins: $r0, $r1, $p0, $d8
+# CHECK: $d8 = A2_combinew killed $r0, killed $r1
+# CHECK: $d8 = L2_ploadrdf_io $p0, $r29, 0, implicit killed $d8
+# CHECK: J2_jumprf killed $p0, $r31, implicit-def $pc, implicit-def $pc, implicit $d8
--- |
define void @foo() {
@@ -23,28 +23,28 @@ name: foo
alignment: 4
tracksRegLiveness: true
liveins:
- - { reg: '%r0' }
- - { reg: '%r1' }
- - { reg: '%p0' }
- - { reg: '%d8' }
+ - { reg: '$r0' }
+ - { reg: '$r1' }
+ - { reg: '$p0' }
+ - { reg: '$d8' }
body: |
bb.0:
successors: %bb.1, %bb.2
- liveins: %r0, %r1, %p0, %d8
- %d8 = A2_combinew killed %r0, killed %r1
- J2_jumpf killed %p0, %bb.2, implicit-def %pc
+ liveins: $r0, $r1, $p0, $d8
+ $d8 = A2_combinew killed $r0, killed $r1
+ J2_jumpf killed $p0, %bb.2, implicit-def $pc
bb.1:
- liveins: %r17
- %r0 = A2_tfrsi 0
- %r1 = A2_tfrsi 0
+ liveins: $r17
+ $r0 = A2_tfrsi 0
+ $r1 = A2_tfrsi 0
A2_nop ; non-predicable
- J2_jumpr killed %r31, implicit-def dead %pc, implicit killed %d0
+ J2_jumpr killed $r31, implicit-def dead $pc, implicit killed $d0
bb.2:
; Predicate this block.
- %d8 = L2_loadrd_io %r29, 0
- J2_jumpr killed %r31, implicit-def dead %pc, implicit killed %d8
+ $d8 = L2_loadrd_io $r29, 0
+ J2_jumpr killed $r31, implicit-def dead $pc, implicit killed $d8
...
Modified: llvm/trunk/test/CodeGen/Hexagon/invalid-dotnew-attempt.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/invalid-dotnew-attempt.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/invalid-dotnew-attempt.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/invalid-dotnew-attempt.mir Wed Jan 31 14:04:26 2018
@@ -10,8 +10,8 @@ name: fred
tracksRegLiveness: true
body: |
bb.0:
- liveins: %d0
- %p0 = C2_tfrrp %r0
- J2_jumpr %r31, implicit-def %pc, implicit %p0
+ liveins: $d0
+ $p0 = C2_tfrrp $r0
+ J2_jumpr $r31, implicit-def $pc, implicit $p0
...
Modified: llvm/trunk/test/CodeGen/Hexagon/livephysregs-add-pristines.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/livephysregs-add-pristines.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/livephysregs-add-pristines.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/livephysregs-add-pristines.mir Wed Jan 31 14:04:26 2018
@@ -2,7 +2,7 @@
# The register r23 is live on the path bb.0->bb.2->bb.3. Make sure we add
# an implicit use of r23 to the predicated redefinition:
-# CHECK: %r23 = A2_tfrt killed %p0, killed %r1, implicit killed %r23
+# CHECK: $r23 = A2_tfrt killed $p0, killed $r1, implicit killed $r23
# LivePhysRegs::addPristines could accidentally remove a callee-saved
# register, if it determined that it wasn't pristine. Doing that caused
@@ -13,25 +13,25 @@
name: foo
tracksRegLiveness: true
fixedStack:
- - { id: 0, offset: 0, size: 4, alignment: 4, callee-saved-register: '%r23' }
+ - { id: 0, offset: 0, size: 4, alignment: 4, callee-saved-register: '$r23' }
body: |
bb.0:
successors: %bb.1, %bb.2
- liveins: %r0, %r1, %r23
- %p0 = C2_cmpgti killed %r0, 0
- J2_jumpf killed %p0, %bb.2, implicit-def %pc
+ liveins: $r0, $r1, $r23
+ $p0 = C2_cmpgti killed $r0, 0
+ J2_jumpf killed $p0, %bb.2, implicit-def $pc
bb.1:
successors: %bb.3
- liveins: %r1
- %r23 = A2_tfr killed %r1
- J2_jump %bb.3, implicit-def %pc
+ liveins: $r1
+ $r23 = A2_tfr killed $r1
+ J2_jump %bb.3, implicit-def $pc
bb.2:
successors: %bb.3
- liveins: %r1, %r23
- %r0 = A2_tfr %r1
+ liveins: $r1, $r23
+ $r0 = A2_tfr $r1
bb.3:
- liveins: %r23
+ liveins: $r23
...
Modified: llvm/trunk/test/CodeGen/Hexagon/livephysregs-lane-masks.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/livephysregs-lane-masks.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/livephysregs-lane-masks.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/livephysregs-lane-masks.mir Wed Jan 31 14:04:26 2018
@@ -1,9 +1,9 @@
# RUN: llc -march=hexagon -run-pass if-converter -verify-machineinstrs -o - %s | FileCheck %s
# CHECK-LABEL: name: foo
-# CHECK: %p0 = C2_cmpeqi %r16, 0
+# CHECK: $p0 = C2_cmpeqi $r16, 0
# Make sure there is no implicit use of r1.
-# CHECK: %r1 = L2_ploadruhf_io %p0, %r29, 6
+# CHECK: $r1 = L2_ploadruhf_io $p0, $r29, 6
--- |
define void @foo() {
@@ -18,23 +18,23 @@ tracksRegLiveness: true
body: |
bb.0:
- liveins: %r16
+ liveins: $r16
successors: %bb.1, %bb.2
- %p0 = C2_cmpeqi %r16, 0
- J2_jumpt %p0, %bb.2, implicit-def %pc
+ $p0 = C2_cmpeqi $r16, 0
+ J2_jumpt $p0, %bb.2, implicit-def $pc
bb.1:
- ; The lane mask %d0:0002 is equivalent to %r0. LivePhysRegs would ignore
- ; it and treat it as the whole %d0, which is a pair %r1, %r0. The extra
- ; %r1 would cause an (undefined) implicit use to be added during
+ ; The lane mask $d0:0002 is equivalent to $r0. LivePhysRegs would ignore
+ ; it and treat it as the whole $d0, which is a pair $r1, $r0. The extra
+ ; $r1 would cause an (undefined) implicit use to be added during
; if-conversion.
- liveins: %d0:0x00000002, %d15:0x00000001, %r16
+ liveins: $d0:0x00000002, $d15:0x00000001, $r16
successors: %bb.2
- %r1 = L2_loadruh_io %r29, 6
- S2_storeri_io killed %r16, 0, %r1
+ $r1 = L2_loadruh_io $r29, 6
+ S2_storeri_io killed $r16, 0, $r1
bb.2:
- liveins: %r0
- %d8 = L2_loadrd_io %r29, 8
- %d15 = L4_return %r29, implicit-def %r29, implicit-def %pc, implicit %r30, implicit %framekey
+ liveins: $r0
+ $d8 = L2_loadrd_io $r29, 8
+ $d15 = L4_return $r29, implicit-def $r29, implicit-def $pc, implicit $r30, implicit $framekey
Modified: llvm/trunk/test/CodeGen/Hexagon/livephysregs-lane-masks2.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/livephysregs-lane-masks2.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/livephysregs-lane-masks2.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/livephysregs-lane-masks2.mir Wed Jan 31 14:04:26 2018
@@ -13,27 +13,27 @@ tracksRegLiveness: true
body: |
bb.0:
- liveins: %p0:0x1, %p2, %r0
+ liveins: $p0:0x1, $p2, $r0
successors: %bb.1, %bb.2
- J2_jumpt killed %p2, %bb.1, implicit-def %pc
- J2_jump %bb.2, implicit-def %pc
+ J2_jumpt killed $p2, %bb.1, implicit-def $pc
+ J2_jump %bb.2, implicit-def $pc
bb.1:
- liveins: %p0:0x1, %r0, %r19
+ liveins: $p0:0x1, $r0, $r19
successors: %bb.3
- %r2 = A2_tfrsi 4
- %r1 = COPY %r19
- %r0 = S2_asl_r_r killed %r0, killed %r2
- %r0 = A2_asrh killed %r0
- J2_jump %bb.3, implicit-def %pc
+ $r2 = A2_tfrsi 4
+ $r1 = COPY $r19
+ $r0 = S2_asl_r_r killed $r0, killed $r2
+ $r0 = A2_asrh killed $r0
+ J2_jump %bb.3, implicit-def $pc
bb.2:
- liveins: %p0:0x1, %r0, %r18
+ liveins: $p0:0x1, $r0, $r18
successors: %bb.3
- %r2 = A2_tfrsi 5
- %r1 = L2_loadrh_io %r18, 0
- %r0 = S2_asl_r_r killed %r0, killed %r2
- %r0 = A2_asrh killed %r0
+ $r2 = A2_tfrsi 5
+ $r1 = L2_loadrh_io $r18, 0
+ $r0 = S2_asl_r_r killed $r0, killed $r2
+ $r0 = A2_asrh killed $r0
bb.3:
; A live-in register without subregs, but with a lane mask that is not ~0
@@ -41,15 +41,15 @@ body: |
; (through tail merging).
;
; CHECK: bb.3:
- ; CHECK: liveins:{{.*}}%p0
- ; CHECK: %r0 = S2_asl_r_r killed %r0, killed %r2
- ; CHECK: %r0 = A2_asrh killed %r0
- ; CHECK: %r0 = C2_cmoveit killed %p0, 1
- ; CHECK: J2_jumpr %r31, implicit-def %pc, implicit %r0
+ ; CHECK: liveins:{{.*}}$p0
+ ; CHECK: $r0 = S2_asl_r_r killed $r0, killed $r2
+ ; CHECK: $r0 = A2_asrh killed $r0
+ ; CHECK: $r0 = C2_cmoveit killed $p0, 1
+ ; CHECK: J2_jumpr $r31, implicit-def $pc, implicit $r0
;
- liveins: %p0:0x1
- %r0 = C2_cmoveit killed %p0, 1
- J2_jumpr %r31, implicit-def %pc, implicit %r0
+ liveins: $p0:0x1
+ $r0 = C2_cmoveit killed $p0, 1
+ J2_jumpr $r31, implicit-def $pc, implicit $r0
...
Modified: llvm/trunk/test/CodeGen/Hexagon/mux-kill1.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/mux-kill1.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/mux-kill1.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/mux-kill1.mir Wed Jan 31 14:04:26 2018
@@ -1,15 +1,15 @@
# RUN: llc -march=hexagon -run-pass hexagon-gen-mux -o - %s -verify-machineinstrs | FileCheck %s
-# CHECK: %r2 = C2_mux killed %p0, killed %r0, %r1
+# CHECK: $r2 = C2_mux killed $p0, killed $r0, $r1
---
name: fred
tracksRegLiveness: true
body: |
bb.0:
- liveins: %d0, %p0
+ liveins: $d0, $p0
- %r2 = A2_tfrt %p0, %r0
- %r0 = A2_tfr %r1
- %r2 = A2_tfrf %p0, killed %r1
+ $r2 = A2_tfrt $p0, $r0
+ $r0 = A2_tfr $r1
+ $r2 = A2_tfrf $p0, killed $r1
...
Modified: llvm/trunk/test/CodeGen/Hexagon/mux-kill2.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/mux-kill2.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/mux-kill2.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/mux-kill2.mir Wed Jan 31 14:04:26 2018
@@ -1,17 +1,17 @@
# RUN: llc -march=hexagon -run-pass hexagon-gen-mux -o - -verify-machineinstrs %s | FileCheck %s
-# CHECK: %r1 = C2_muxri %p0, 123, %r0
-# CHECK: %r2 = C2_muxir killed %p0, killed %r0, 321
+# CHECK: $r1 = C2_muxri $p0, 123, $r0
+# CHECK: $r2 = C2_muxir killed $p0, killed $r0, 321
---
name: fred
tracksRegLiveness: true
body: |
bb.0:
- liveins: %r0, %p0
+ liveins: $r0, $p0
- %r2 = A2_tfrt %p0, %r0
- %r1 = C2_cmoveit %p0, 123
- %r1 = A2_tfrf %p0, killed %r0, implicit killed %r1
- %r2 = C2_cmoveif killed %p0, 321, implicit killed %r2
+ $r2 = A2_tfrt $p0, $r0
+ $r1 = C2_cmoveit $p0, 123
+ $r1 = A2_tfrf $p0, killed $r0, implicit killed $r1
+ $r2 = C2_cmoveif killed $p0, 321, implicit killed $r2
...
Modified: llvm/trunk/test/CodeGen/Hexagon/mux-kill3.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/mux-kill3.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/mux-kill3.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/mux-kill3.mir Wed Jan 31 14:04:26 2018
@@ -1,31 +1,31 @@
# RUN: llc -march=hexagon -run-pass hexagon-gen-mux -o - %s -verify-machineinstrs | FileCheck %s
# Make sure this verifies correctly.
-# CHECK: PS_jmpret killed %r31, implicit-def %pc
+# CHECK: PS_jmpret killed $r31, implicit-def $pc
---
name: fred
tracksRegLiveness: true
body: |
bb.0:
- liveins: %d0, %d1, %d2, %d3
+ liveins: $d0, $d1, $d2, $d3
- %p0 = C2_cmpeqi killed %r4, 128
- %d4 = A2_tfrpi 0
- %r3 = A2_tfrsi 0
- %r4 = A2_tfrsi 0
- %r7 = A2_tfrt %p0, %r0
- %p1 = C2_cmpeqp %d0, killed %d4
- %r8 = A2_tfrt %p0, killed %r0
- %r9 = A2_tfrt %p0, killed %r1
- %r7 = A2_tfrf %p0, %r3, implicit killed %r7
- %r9 = A2_tfrf %p0, killed %r3, implicit killed %r9
- %r8 = C2_cmoveif killed %p0, 1, implicit killed %r8
- %d0 = A4_combineri killed %r4, 0
- %r2 = A2_tfrt %p1, killed %r7, implicit killed %r2
- %r3 = A2_tfr killed %r9
- %r2 = A2_tfrf killed %p1, killed %r8, implicit killed %r2
- S2_storerd_io killed %r6, 0, killed %d1
- S2_storerd_io killed %r5, 0, killed %d0
- PS_jmpret %r31, implicit-def %pc
+ $p0 = C2_cmpeqi killed $r4, 128
+ $d4 = A2_tfrpi 0
+ $r3 = A2_tfrsi 0
+ $r4 = A2_tfrsi 0
+ $r7 = A2_tfrt $p0, $r0
+ $p1 = C2_cmpeqp $d0, killed $d4
+ $r8 = A2_tfrt $p0, killed $r0
+ $r9 = A2_tfrt $p0, killed $r1
+ $r7 = A2_tfrf $p0, $r3, implicit killed $r7
+ $r9 = A2_tfrf $p0, killed $r3, implicit killed $r9
+ $r8 = C2_cmoveif killed $p0, 1, implicit killed $r8
+ $d0 = A4_combineri killed $r4, 0
+ $r2 = A2_tfrt $p1, killed $r7, implicit killed $r2
+ $r3 = A2_tfr killed $r9
+ $r2 = A2_tfrf killed $p1, killed $r8, implicit killed $r2
+ S2_storerd_io killed $r6, 0, killed $d1
+ S2_storerd_io killed $r5, 0, killed $d0
+ PS_jmpret $r31, implicit-def $pc
...
Modified: llvm/trunk/test/CodeGen/Hexagon/newvaluejump-c4.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/newvaluejump-c4.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/newvaluejump-c4.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/newvaluejump-c4.mir Wed Jan 31 14:04:26 2018
@@ -2,46 +2,46 @@
---
# CHECK-LABEL: name: test0
-# CHECK: J4_cmpeqi_f_jumpnv_t killed %r1, 0
+# CHECK: J4_cmpeqi_f_jumpnv_t killed $r1, 0
name: test0
tracksRegLiveness: true
body: |
bb.0:
- liveins: %r0
- %r1 = A2_addi %r0, -1
- %p0 = C4_cmpneqi killed %r1, 0
- J2_jumpt killed %p0, %bb.1, implicit-def %pc
+ liveins: $r0
+ $r1 = A2_addi $r0, -1
+ $p0 = C4_cmpneqi killed $r1, 0
+ J2_jumpt killed $p0, %bb.1, implicit-def $pc
bb.1:
...
---
# CHECK-LABEL: name: test1
-# CHECK: J4_cmpgti_f_jumpnv_t killed %r1, 27
+# CHECK: J4_cmpgti_f_jumpnv_t killed $r1, 27
name: test1
tracksRegLiveness: true
body: |
bb.0:
- liveins: %r0
- %r1 = A2_addi %r0, -1
- %p0 = C4_cmpltei killed %r1, 27
- J2_jumpt killed %p0, %bb.1, implicit-def %pc
+ liveins: $r0
+ $r1 = A2_addi $r0, -1
+ $p0 = C4_cmpltei killed $r1, 27
+ J2_jumpt killed $p0, %bb.1, implicit-def $pc
bb.1:
...
---
# CHECK-LABEL: name: test2
-# CHECK: J4_cmpgtui_f_jumpnv_t killed %r1, 31
+# CHECK: J4_cmpgtui_f_jumpnv_t killed $r1, 31
name: test2
tracksRegLiveness: true
body: |
bb.0:
- liveins: %r0
- %r1 = A2_addi %r0, -1
- %p0 = C4_cmplteui killed %r1, 31
- J2_jumpt killed %p0, %bb.1, implicit-def %pc
+ liveins: $r0
+ $r1 = A2_addi $r0, -1
+ $p0 = C4_cmplteui killed $r1, 31
+ J2_jumpt killed $p0, %bb.1, implicit-def $pc
bb.1:
...
Modified: llvm/trunk/test/CodeGen/Hexagon/newvaluejump-kill2.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/newvaluejump-kill2.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/newvaluejump-kill2.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/newvaluejump-kill2.mir Wed Jan 31 14:04:26 2018
@@ -1,5 +1,5 @@
# RUN: llc -march=hexagon -run-pass hexagon-nvj -verify-machineinstrs %s -o - | FileCheck %s
-# CHECK: J4_cmpgtu_t_jumpnv_t killed %r3, killed %r1, %bb.1, implicit-def %pc
+# CHECK: J4_cmpgtu_t_jumpnv_t killed $r3, killed $r1, %bb.1, implicit-def $pc
---
name: fred
@@ -7,12 +7,12 @@ tracksRegLiveness: true
body: |
bb.0:
- liveins: %r0
- %r1 = A2_addi %r0, -1
- %r2 = A2_tfrsi -1431655765
- %r3 = A2_tfrsi 2
- %p0 = C2_cmpgtu killed %r3, %r1
- %r2 = S4_subaddi killed %r1, 1, killed %r2
- J2_jumpt killed %p0, %bb.1, implicit-def %pc
+ liveins: $r0
+ $r1 = A2_addi $r0, -1
+ $r2 = A2_tfrsi -1431655765
+ $r3 = A2_tfrsi 2
+ $p0 = C2_cmpgtu killed $r3, $r1
+ $r2 = S4_subaddi killed $r1, 1, killed $r2
+ J2_jumpt killed $p0, %bb.1, implicit-def $pc
bb.1:
...
Modified: llvm/trunk/test/CodeGen/Hexagon/newvaluejump-solo.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/newvaluejump-solo.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/newvaluejump-solo.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/newvaluejump-solo.mir Wed Jan 31 14:04:26 2018
@@ -10,10 +10,10 @@ tracksRegLiveness: true
body: |
bb.0:
successors: %bb.1
- %r0 = A2_tfrsi 0
- %r0 = V6_extractw killed undef %v0, %r0
- %p0 = C2_cmpeqi killed %r0, 1
- J2_jumpf killed %p0, %bb.1, implicit-def %pc
+ $r0 = A2_tfrsi 0
+ $r0 = V6_extractw killed undef $v0, $r0
+ $p0 = C2_cmpeqi killed $r0, 1
+ J2_jumpf killed $p0, %bb.1, implicit-def $pc
bb.1:
...
Modified: llvm/trunk/test/CodeGen/Hexagon/packetize-load-store-aliasing.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/packetize-load-store-aliasing.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/packetize-load-store-aliasing.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/packetize-load-store-aliasing.mir Wed Jan 31 14:04:26 2018
@@ -14,9 +14,9 @@ stack:
- { id: 1, type: default, size: 4, alignment: 4 }
body: |
bb.0:
- liveins: %r0
- S2_storeri_io %r29, 0, %r0 :: (store 4 into %stack.0)
- %r1 = L2_loadri_io %r29, 4 :: (load 4 from %stack.1)
+ liveins: $r0
+ S2_storeri_io $r29, 0, $r0 :: (store 4 into %stack.0)
+ $r1 = L2_loadri_io $r29, 4 :: (load 4 from %stack.1)
...
@@ -24,8 +24,8 @@ body: |
# if these instructions are aliased.
# CHECK-LABEL: name: sammy
# CHECK-NOT: BUNDLE
-# CHECK: S2_storeri_io %r29, 0, %r0
-# CHECK: %r1 = L2_loadri_io %r29, 0
+# CHECK: S2_storeri_io $r29, 0, $r0
+# CHECK: $r1 = L2_loadri_io $r29, 0
---
name: sammy
@@ -34,8 +34,8 @@ stack:
- { id: 0, type: default, size: 4, alignment: 4 }
body: |
bb.0:
- liveins: %r0
- S2_storeri_io %r29, 0, %r0 :: (store 4 into %stack.0)
- %r1 = L2_loadri_io %r29, 0 :: (load 4 from %stack.0)
+ liveins: $r0
+ S2_storeri_io $r29, 0, $r0 :: (store 4 into %stack.0)
+ $r1 = L2_loadri_io $r29, 0 :: (load 4 from %stack.0)
...
Modified: llvm/trunk/test/CodeGen/Hexagon/packetize-nvj-no-prune.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/packetize-nvj-no-prune.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/packetize-nvj-no-prune.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/packetize-nvj-no-prune.mir Wed Jan 31 14:04:26 2018
@@ -7,8 +7,8 @@
# CHECK-LABEL: name: fred
# CHECK: BUNDLE
-# CHECK-NEXT: %r3 = L2_loadri_io %r1, 0
-# CHECK-NEXT: J4_cmpgtu_f_jumpnv_t internal killed %r3
+# CHECK-NEXT: $r3 = L2_loadri_io $r1, 0
+# CHECK-NEXT: J4_cmpgtu_f_jumpnv_t internal killed $r3
--- |
@@ -22,10 +22,10 @@ tracksRegLiveness: true
body: |
bb.0:
successors: %bb.1
- %r1 = A2_tfrsi @array
- %r2, %r1 = L2_loadri_pi %r1, 4
- %r3 = L2_loadri_io %r1, 0
- J4_cmpgtu_f_jumpnv_t killed %r3, killed %r2, %bb.1, implicit-def %pc
+ $r1 = A2_tfrsi @array
+ $r2, $r1 = L2_loadri_pi $r1, 4
+ $r3 = L2_loadri_io $r1, 0
+ J4_cmpgtu_f_jumpnv_t killed $r3, killed $r2, %bb.1, implicit-def $pc
bb.1:
...
Modified: llvm/trunk/test/CodeGen/Hexagon/post-ra-kill-update.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/post-ra-kill-update.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/post-ra-kill-update.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/post-ra-kill-update.mir Wed Jan 31 14:04:26 2018
@@ -6,8 +6,8 @@
# CHECK-LABEL: name: foo
# Check for no-kill of r9 in the first instruction, after reordering:
-# CHECK: %d7 = S2_lsr_r_p_or killed %d7, killed %d1, %r9
-# CHECK: %d13 = S2_lsr_r_p killed %d0, killed %r9
+# CHECK: $d7 = S2_lsr_r_p_or killed $d7, killed $d1, $r9
+# CHECK: $d13 = S2_lsr_r_p killed $d0, killed $r9
--- |
define void @foo() {
@@ -21,15 +21,15 @@ tracksRegLiveness: true
body: |
bb.0:
successors: %bb.1
- liveins: %d0, %d1, %r9, %r13
+ liveins: $d0, $d1, $r9, $r13
- %d7 = S2_asl_r_p %d0, %r13
- %d5 = S2_asl_r_p %d1, killed %r13
- %d6 = S2_lsr_r_p killed %d0, %r9
- %d7 = S2_lsr_r_p_or killed %d7, killed %d1, killed %r9
- %d1 = A2_combinew killed %r11, killed %r10
- %d0 = A2_combinew killed %r15, killed %r14
- J2_jump %bb.1, implicit-def %pc
+ $d7 = S2_asl_r_p $d0, $r13
+ $d5 = S2_asl_r_p $d1, killed $r13
+ $d6 = S2_lsr_r_p killed $d0, $r9
+ $d7 = S2_lsr_r_p_or killed $d7, killed $d1, killed $r9
+ $d1 = A2_combinew killed $r11, killed $r10
+ $d0 = A2_combinew killed $r15, killed $r14
+ J2_jump %bb.1, implicit-def $pc
bb.1:
A2_nop
Modified: llvm/trunk/test/CodeGen/Hexagon/postinc-baseoffset.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/postinc-baseoffset.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/postinc-baseoffset.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/postinc-baseoffset.mir Wed Jan 31 14:04:26 2018
@@ -17,6 +17,6 @@ tracksRegLiveness: true
body: |
bb.0:
- liveins: %r0
- S4_storeiri_io %r0, 0, -1 :: (store 4 into %ir.a)
- %r1, %r0 = L2_loadri_pi %r0, 8 :: (load 4 from %ir.a)
+ liveins: $r0
+ S4_storeiri_io $r0, 0, -1 :: (store 4 into %ir.a)
+ $r1, $r0 = L2_loadri_pi $r0, 8 :: (load 4 from %ir.a)
Modified: llvm/trunk/test/CodeGen/Hexagon/rdf-copy-renamable-reserved.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/rdf-copy-renamable-reserved.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/rdf-copy-renamable-reserved.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/rdf-copy-renamable-reserved.mir Wed Jan 31 14:04:26 2018
@@ -3,7 +3,7 @@
# Check that r29 gets propagated into the A2_addi, and that the renamable
# flag is cleared.
-# CHECK: renamable %r28 = COPY %r29
+# CHECK: renamable $r28 = COPY $r29
# CHECK-NOT: renamable
---
@@ -12,8 +12,8 @@ tracksRegLiveness: true
body: |
bb.0:
- renamable %r28 = COPY %r29
- %r0 = A2_addi renamable %r28, 1
- J2_jumpr %r31, implicit-def %pc, implicit %r0
+ renamable $r28 = COPY $r29
+ $r0 = A2_addi renamable $r28, 1
+ J2_jumpr $r31, implicit-def $pc, implicit $r0
...
Modified: llvm/trunk/test/CodeGen/Hexagon/rdf-ehlabel-live.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/rdf-ehlabel-live.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/rdf-ehlabel-live.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/rdf-ehlabel-live.mir Wed Jan 31 14:04:26 2018
@@ -11,7 +11,7 @@ tracksRegLiveness: true
body: |
bb.0:
- %r0 = A2_tfrsi 0
+ $r0 = A2_tfrsi 0
EH_LABEL 0
...
Modified: llvm/trunk/test/CodeGen/Hexagon/regalloc-bad-undef.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/regalloc-bad-undef.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/regalloc-bad-undef.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/regalloc-bad-undef.mir Wed Jan 31 14:04:26 2018
@@ -153,51 +153,51 @@ body: |
%13 = S2_asl_r_p_acc %13, %47, %8.isub_lo
%51 = A2_tfrpi 0
- ; CHECK: %d2 = S2_extractup undef renamable %d0, 6, 25
- ; CHECK: %d0 = A2_tfrpi 2
- ; CHECK: %d13 = A2_tfrpi -1
- ; CHECK-NOT: undef %r4
+ ; CHECK: $d2 = S2_extractup undef renamable $d0, 6, 25
+ ; CHECK: $d0 = A2_tfrpi 2
+ ; CHECK: $d13 = A2_tfrpi -1
+ ; CHECK-NOT: undef $r4
bb.1.for.body:
successors: %bb.3.for.end, %bb.2.if.end82
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
- J2_call @lrand48, implicit-def dead %d0, implicit-def dead %d1, implicit-def dead %d2, implicit-def dead %d3, implicit-def dead %d4, implicit-def dead %d5, implicit-def dead %d6, implicit-def dead %d7, implicit-def dead %r28, implicit-def dead %r31, implicit-def dead %p0, implicit-def dead %p1, implicit-def dead %p2, implicit-def dead %p3, implicit-def dead %m0, implicit-def dead %m1, implicit-def dead %lc0, implicit-def dead %lc1, implicit-def dead %sa0, implicit-def dead %sa1, implicit-def dead %usr, implicit-def %usr_ovf, implicit-def dead %cs0, implicit-def dead %cs1, implicit-def dead %w0, implicit-def dead %w1, implicit-def dead %w2, implicit-def dead %w3, implicit-def dead %w4, implicit-def dead %w5, implicit-def dead %w6, implicit-def dead %w7, implicit-def dead %w8, implicit-def dead %w9, implicit-def dead %w10, implicit-def dead %w11, implicit-def dead %w12, implicit-def dead %w13, implicit-def dead %w14, implicit-def dead %w15, implicit-def dead %q0, implicit-def dead %q1, implicit-def dead %q2, implicit-def dead %q3, implicit-def %r0
- ADJCALLSTACKUP 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit-def dead %r31, implicit %r29
- undef %29.isub_lo = COPY killed %r0
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit $r31, implicit $r30, implicit $r29
+ J2_call @lrand48, implicit-def dead $d0, implicit-def dead $d1, implicit-def dead $d2, implicit-def dead $d3, implicit-def dead $d4, implicit-def dead $d5, implicit-def dead $d6, implicit-def dead $d7, implicit-def dead $r28, implicit-def dead $r31, implicit-def dead $p0, implicit-def dead $p1, implicit-def dead $p2, implicit-def dead $p3, implicit-def dead $m0, implicit-def dead $m1, implicit-def dead $lc0, implicit-def dead $lc1, implicit-def dead $sa0, implicit-def dead $sa1, implicit-def dead $usr, implicit-def $usr_ovf, implicit-def dead $cs0, implicit-def dead $cs1, implicit-def dead $w0, implicit-def dead $w1, implicit-def dead $w2, implicit-def dead $w3, implicit-def dead $w4, implicit-def dead $w5, implicit-def dead $w6, implicit-def dead $w7, implicit-def dead $w8, implicit-def dead $w9, implicit-def dead $w10, implicit-def dead $w11, implicit-def dead $w12, implicit-def dead $w13, implicit-def dead $w14, implicit-def dead $w15, implicit-def dead $q0, implicit-def dead $q1, implicit-def dead $q2, implicit-def dead $q3, implicit-def $r0
+ ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit-def dead $r31, implicit $r29
+ undef %29.isub_lo = COPY killed $r0
%29.isub_hi = S2_asr_i_r %29.isub_lo, 31
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
- J2_call @lrand48, implicit-def dead %d0, implicit-def dead %d1, implicit-def dead %d2, implicit-def dead %d3, implicit-def dead %d4, implicit-def dead %d5, implicit-def dead %d6, implicit-def dead %d7, implicit-def dead %r28, implicit-def dead %r31, implicit-def dead %p0, implicit-def dead %p1, implicit-def dead %p2, implicit-def dead %p3, implicit-def dead %m0, implicit-def dead %m1, implicit-def dead %lc0, implicit-def dead %lc1, implicit-def dead %sa0, implicit-def dead %sa1, implicit-def dead %usr, implicit-def %usr_ovf, implicit-def dead %cs0, implicit-def dead %cs1, implicit-def dead %w0, implicit-def dead %w1, implicit-def dead %w2, implicit-def dead %w3, implicit-def dead %w4, implicit-def dead %w5, implicit-def dead %w6, implicit-def dead %w7, implicit-def dead %w8, implicit-def dead %w9, implicit-def dead %w10, implicit-def dead %w11, implicit-def dead %w12, implicit-def dead %w13, implicit-def dead %w14, implicit-def dead %w15, implicit-def dead %q0, implicit-def dead %q1, implicit-def dead %q2, implicit-def dead %q3, implicit-def %r0
- ADJCALLSTACKUP 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit-def dead %r31, implicit %r29
- %32.isub_lo = COPY killed %r0
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit $r31, implicit $r30, implicit $r29
+ J2_call @lrand48, implicit-def dead $d0, implicit-def dead $d1, implicit-def dead $d2, implicit-def dead $d3, implicit-def dead $d4, implicit-def dead $d5, implicit-def dead $d6, implicit-def dead $d7, implicit-def dead $r28, implicit-def dead $r31, implicit-def dead $p0, implicit-def dead $p1, implicit-def dead $p2, implicit-def dead $p3, implicit-def dead $m0, implicit-def dead $m1, implicit-def dead $lc0, implicit-def dead $lc1, implicit-def dead $sa0, implicit-def dead $sa1, implicit-def dead $usr, implicit-def $usr_ovf, implicit-def dead $cs0, implicit-def dead $cs1, implicit-def dead $w0, implicit-def dead $w1, implicit-def dead $w2, implicit-def dead $w3, implicit-def dead $w4, implicit-def dead $w5, implicit-def dead $w6, implicit-def dead $w7, implicit-def dead $w8, implicit-def dead $w9, implicit-def dead $w10, implicit-def dead $w11, implicit-def dead $w12, implicit-def dead $w13, implicit-def dead $w14, implicit-def dead $w15, implicit-def dead $q0, implicit-def dead $q1, implicit-def dead $q2, implicit-def dead $q3, implicit-def $r0
+ ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit-def dead $r31, implicit $r29
+ %32.isub_lo = COPY killed $r0
%7 = S2_extractup %32, 22, 9
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
- J2_call @lrand48, implicit-def dead %d0, implicit-def dead %d1, implicit-def dead %d2, implicit-def dead %d3, implicit-def dead %d4, implicit-def dead %d5, implicit-def dead %d6, implicit-def dead %d7, implicit-def dead %r28, implicit-def dead %r31, implicit-def dead %p0, implicit-def dead %p1, implicit-def dead %p2, implicit-def dead %p3, implicit-def dead %m0, implicit-def dead %m1, implicit-def dead %lc0, implicit-def dead %lc1, implicit-def dead %sa0, implicit-def dead %sa1, implicit-def dead %usr, implicit-def %usr_ovf, implicit-def dead %cs0, implicit-def dead %cs1, implicit-def dead %w0, implicit-def dead %w1, implicit-def dead %w2, implicit-def dead %w3, implicit-def dead %w4, implicit-def dead %w5, implicit-def dead %w6, implicit-def dead %w7, implicit-def dead %w8, implicit-def dead %w9, implicit-def dead %w10, implicit-def dead %w11, implicit-def dead %w12, implicit-def dead %w13, implicit-def dead %w14, implicit-def dead %w15, implicit-def dead %q0, implicit-def dead %q1, implicit-def dead %q2, implicit-def dead %q3, implicit-def %r0
- ADJCALLSTACKUP 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit-def dead %r31, implicit %r29
- undef %43.isub_lo = COPY killed %r0
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit $r31, implicit $r30, implicit $r29
+ J2_call @lrand48, implicit-def dead $d0, implicit-def dead $d1, implicit-def dead $d2, implicit-def dead $d3, implicit-def dead $d4, implicit-def dead $d5, implicit-def dead $d6, implicit-def dead $d7, implicit-def dead $r28, implicit-def dead $r31, implicit-def dead $p0, implicit-def dead $p1, implicit-def dead $p2, implicit-def dead $p3, implicit-def dead $m0, implicit-def dead $m1, implicit-def dead $lc0, implicit-def dead $lc1, implicit-def dead $sa0, implicit-def dead $sa1, implicit-def dead $usr, implicit-def $usr_ovf, implicit-def dead $cs0, implicit-def dead $cs1, implicit-def dead $w0, implicit-def dead $w1, implicit-def dead $w2, implicit-def dead $w3, implicit-def dead $w4, implicit-def dead $w5, implicit-def dead $w6, implicit-def dead $w7, implicit-def dead $w8, implicit-def dead $w9, implicit-def dead $w10, implicit-def dead $w11, implicit-def dead $w12, implicit-def dead $w13, implicit-def dead $w14, implicit-def dead $w15, implicit-def dead $q0, implicit-def dead $q1, implicit-def dead $q2, implicit-def dead $q3, implicit-def $r0
+ ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit-def dead $r31, implicit $r29
+ undef %43.isub_lo = COPY killed $r0
%43.isub_hi = COPY %32.isub_hi
%16 = S2_extractup %43, 6, 25
%18 = A2_tfrpi -1
%18 = S2_asl_r_p_acc %18, %47, %16.isub_lo
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
- J2_call @lrand48, implicit-def dead %d0, implicit-def dead %d1, implicit-def dead %d2, implicit-def dead %d3, implicit-def dead %d4, implicit-def dead %d5, implicit-def dead %d6, implicit-def dead %d7, implicit-def dead %r28, implicit-def dead %r31, implicit-def dead %p0, implicit-def dead %p1, implicit-def dead %p2, implicit-def dead %p3, implicit-def dead %m0, implicit-def dead %m1, implicit-def dead %lc0, implicit-def dead %lc1, implicit-def dead %sa0, implicit-def dead %sa1, implicit-def dead %usr, implicit-def %usr_ovf, implicit-def dead %cs0, implicit-def dead %cs1, implicit-def dead %w0, implicit-def dead %w1, implicit-def dead %w2, implicit-def dead %w3, implicit-def dead %w4, implicit-def dead %w5, implicit-def dead %w6, implicit-def dead %w7, implicit-def dead %w8, implicit-def dead %w9, implicit-def dead %w10, implicit-def dead %w11, implicit-def dead %w12, implicit-def dead %w13, implicit-def dead %w14, implicit-def dead %w15, implicit-def dead %q0, implicit-def dead %q1, implicit-def dead %q2, implicit-def dead %q3
- ADJCALLSTACKUP 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit-def dead %r31, implicit %r29
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit $r31, implicit $r30, implicit $r29
+ J2_call @lrand48, implicit-def dead $d0, implicit-def dead $d1, implicit-def dead $d2, implicit-def dead $d3, implicit-def dead $d4, implicit-def dead $d5, implicit-def dead $d6, implicit-def dead $d7, implicit-def dead $r28, implicit-def dead $r31, implicit-def dead $p0, implicit-def dead $p1, implicit-def dead $p2, implicit-def dead $p3, implicit-def dead $m0, implicit-def dead $m1, implicit-def dead $lc0, implicit-def dead $lc1, implicit-def dead $sa0, implicit-def dead $sa1, implicit-def dead $usr, implicit-def $usr_ovf, implicit-def dead $cs0, implicit-def dead $cs1, implicit-def dead $w0, implicit-def dead $w1, implicit-def dead $w2, implicit-def dead $w3, implicit-def dead $w4, implicit-def dead $w5, implicit-def dead $w6, implicit-def dead $w7, implicit-def dead $w8, implicit-def dead $w9, implicit-def dead $w10, implicit-def dead $w11, implicit-def dead $w12, implicit-def dead $w13, implicit-def dead $w14, implicit-def dead $w15, implicit-def dead $q0, implicit-def dead $q1, implicit-def dead $q2, implicit-def dead $q3
+ ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit-def dead $r31, implicit $r29
%22 = S2_asl_r_p %18, %8.isub_lo
%21 = COPY %13
%21 = S2_lsr_i_p_and %21, %29, 9
%22 = S2_asl_i_p_and %22, %7, 42
S2_storerd_io undef %23, 0, %22 :: (store 8 into `i64* undef`)
%25 = C2_cmpeqp %21, %51
- J2_jumpt %25, %bb.3.for.end, implicit-def dead %pc
- J2_jump %bb.2.if.end82, implicit-def dead %pc
+ J2_jumpt %25, %bb.3.for.end, implicit-def dead $pc
+ J2_jump %bb.2.if.end82, implicit-def dead $pc
bb.2.if.end82:
successors: %bb.3.for.end, %bb.1.for.body
%59 = A2_addi %59, -1
%26 = C2_cmpeqi %59, 0
- J2_jumpf %26, %bb.1.for.body, implicit-def dead %pc
- J2_jump %bb.3.for.end, implicit-def dead %pc
+ J2_jumpf %26, %bb.1.for.body, implicit-def dead $pc
+ J2_jump %bb.3.for.end, implicit-def dead $pc
bb.3.for.end:
Modified: llvm/trunk/test/CodeGen/Hexagon/regalloc-liveout-undef.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/regalloc-liveout-undef.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/regalloc-liveout-undef.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/regalloc-liveout-undef.mir Wed Jan 31 14:04:26 2018
@@ -19,10 +19,10 @@ registers:
- { id: 3, class: doubleregs }
body: |
bb.0:
- liveins: %d0
+ liveins: $d0
successors: %bb.1
%0 = IMPLICIT_DEF
- %1 = COPY %d0
+ %1 = COPY $d0
bb.1:
successors: %bb.1
@@ -30,5 +30,5 @@ body: |
%3 = COPY %1
%1 = COPY %3
undef %1.isub_lo = A2_addi %1.isub_lo, 1
- J2_jump %bb.1, implicit-def %pc
+ J2_jump %bb.1, implicit-def $pc
...
Modified: llvm/trunk/test/CodeGen/Hexagon/target-flag-ext.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/target-flag-ext.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/target-flag-ext.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/target-flag-ext.mir Wed Jan 31 14:04:26 2018
@@ -13,12 +13,12 @@ body: |
; testing this is not possible otherwise.
; CHECK: BUNDLE
- ; CHECK-DAG: %r0 = A2_tfrsi
- ; CHECK-DAG: %r1 = A2_tfrsi
- ; CHECK-DAG: %r2 = A2_tfrsi
+ ; CHECK-DAG: $r0 = A2_tfrsi
+ ; CHECK-DAG: $r1 = A2_tfrsi
+ ; CHECK-DAG: $r2 = A2_tfrsi
; CHECK: }
- %r0 = A2_tfrsi target-flags (hexagon-pcrel) 0
- %r1 = A2_tfrsi target-flags (hexagon-pcrel) 0
- %r2 = A2_tfrsi target-flags (hexagon-pcrel) 0
+ $r0 = A2_tfrsi target-flags (hexagon-pcrel) 0
+ $r1 = A2_tfrsi target-flags (hexagon-pcrel) 0
+ $r2 = A2_tfrsi target-flags (hexagon-pcrel) 0
...
Modified: llvm/trunk/test/CodeGen/Hexagon/unreachable-mbb-phi-subreg.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/unreachable-mbb-phi-subreg.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/unreachable-mbb-phi-subreg.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/unreachable-mbb-phi-subreg.mir Wed Jan 31 14:04:26 2018
@@ -5,11 +5,11 @@ name: fred
tracksRegLiveness: true
body: |
bb.0:
- liveins: %d0
+ liveins: $d0
successors: %bb.2
- %0 : doubleregs = COPY %d0
- J2_jump %bb.2, implicit-def %pc
+ %0 : doubleregs = COPY $d0
+ J2_jump %bb.2, implicit-def $pc
bb.1:
successors: %bb.2
@@ -18,7 +18,7 @@ body: |
bb.2:
; Make sure that the subregister from the PHI operand is preserved.
; CHECK: %[[REG:[0-9]+]]:intregs = COPY %0.isub_lo
- ; CHECK: %r0 = COPY %[[REG]]
+ ; CHECK: $r0 = COPY %[[REG]]
%1 : intregs = PHI %0.isub_lo, %bb.0, %0.isub_hi, %bb.1
- %r0 = COPY %1
+ $r0 = COPY %1
...
Modified: llvm/trunk/test/CodeGen/Hexagon/vextract-basic.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/vextract-basic.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/vextract-basic.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/vextract-basic.mir Wed Jan 31 14:04:26 2018
@@ -6,10 +6,10 @@ tracksRegLiveness: true
body: |
bb.0:
- liveins: %r0, %r1, %v0
- %0:hvxvr = COPY %v0
- %1:intregs = COPY %r0
- %2:intregs = COPY %r1
+ liveins: $r0, $r1, $v0
+ %0:hvxvr = COPY $v0
+ %1:intregs = COPY $r0
+ %2:intregs = COPY $r1
%3:intregs = A2_tfrsi 5
%4:intregs = V6_extractw %0, %1
; CHECK: %[[A0:[0-9]+]]:intregs = A2_andir %{{[0-9]+}}, -4
Modified: llvm/trunk/test/CodeGen/Lanai/peephole-compare.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Lanai/peephole-compare.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Lanai/peephole-compare.mir (original)
+++ llvm/trunk/test/CodeGen/Lanai/peephole-compare.mir Wed Jan 31 14:04:26 2018
@@ -4,31 +4,31 @@
# CHECK-LABEL: name: test0a
# TODO: Enhance combiner to handle this case. This expands into:
-# sub %r7, %r6, %r3
-# sub.f %r7, %r6, %r0
-# sel.eq %r18, %r3, %rv
+# sub $r7, $r6, $r3
+# sub.f $r7, $r6, $r0
+# sel.eq $r18, $r3, $rv
# This is different from the pattern currently matched. If the lowered form had
-# been sub.f %r3, 0, %r0 then it would have matched.
+# been sub.f $r3, 0, $r0 then it would have matched.
# CHECK-LABEL: name: test1a
-# CHECK: [[IN1:%.*]]:gpr = COPY %r7
-# CHECK: [[IN2:%.*]]:gpr = COPY %r6
-# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def %sr
+# CHECK: [[IN1:%.*]]:gpr = COPY $r7
+# CHECK: [[IN2:%.*]]:gpr = COPY $r6
+# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def $sr
# CHECK-LABEL: name: test1b
-# CHECK: [[IN1:%.*]]:gpr = COPY %r7
-# CHECK: [[IN2:%.*]]:gpr = COPY %r6
-# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def %sr
+# CHECK: [[IN1:%.*]]:gpr = COPY $r7
+# CHECK: [[IN2:%.*]]:gpr = COPY $r6
+# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def $sr
# CHECK-LABEL: name: test2a
-# CHECK: [[IN1:%.*]]:gpr = COPY %r7
-# CHECK: [[IN2:%.*]]:gpr = COPY %r6
-# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def %sr
+# CHECK: [[IN1:%.*]]:gpr = COPY $r7
+# CHECK: [[IN2:%.*]]:gpr = COPY $r6
+# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def $sr
# CHECK-LABEL: name: test2b
-# CHECK: [[IN1:%.*]]:gpr = COPY %r7
-# CHECK: [[IN2:%.*]]:gpr = COPY %r6
-# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def %sr
+# CHECK: [[IN1:%.*]]:gpr = COPY $r7
+# CHECK: [[IN2:%.*]]:gpr = COPY $r6
+# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def $sr
# CHECK-LABEL: name: test3
# CHECK: AND_F_R
@@ -184,9 +184,9 @@ registers:
- { id: 4, class: gpr }
- { id: 5, class: gpr }
liveins:
- - { reg: '%r6', virtual-reg: '%0' }
- - { reg: '%r7', virtual-reg: '%1' }
- - { reg: '%r18', virtual-reg: '%2' }
+ - { reg: '$r6', virtual-reg: '%0' }
+ - { reg: '$r7', virtual-reg: '%1' }
+ - { reg: '$r18', virtual-reg: '%2' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -203,16 +203,16 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %r6, %r7, %r18
+ liveins: $r6, $r7, $r18
- %2 = COPY %r18
- %1 = COPY %r7
- %0 = COPY %r6
+ %2 = COPY $r18
+ %1 = COPY $r7
+ %0 = COPY $r6
%4 = SUB_R %1, %0, 0
- SFSUB_F_RI_LO %4, 0, implicit-def %sr
- %5 = SELECT %2, %4, 7, implicit %sr
- %rv = COPY %5
- RET implicit %rca, implicit %rv
+ SFSUB_F_RI_LO %4, 0, implicit-def $sr
+ %5 = SELECT %2, %4, 7, implicit $sr
+ $rv = COPY %5
+ RET implicit $rca, implicit $rv
...
---
@@ -227,9 +227,9 @@ registers:
- { id: 3, class: gpr }
- { id: 4, class: gpr }
liveins:
- - { reg: '%r6', virtual-reg: '%0' }
- - { reg: '%r7', virtual-reg: '%1' }
- - { reg: '%r18', virtual-reg: '%2' }
+ - { reg: '$r6', virtual-reg: '%0' }
+ - { reg: '$r7', virtual-reg: '%1' }
+ - { reg: '$r18', virtual-reg: '%2' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -246,15 +246,15 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %r6, %r7, %r18
+ liveins: $r6, $r7, $r18
- %2 = COPY %r18
- %1 = COPY %r7
- %0 = COPY %r6
- SFSUB_F_RR %1, %0, implicit-def %sr
- %4 = SELECT %2, %1, 7, implicit %sr
- %rv = COPY %4
- RET implicit %rca, implicit %rv
+ %2 = COPY $r18
+ %1 = COPY $r7
+ %0 = COPY $r6
+ SFSUB_F_RR %1, %0, implicit-def $sr
+ %4 = SELECT %2, %1, 7, implicit $sr
+ $rv = COPY %4
+ RET implicit $rca, implicit $rv
...
---
@@ -270,10 +270,10 @@ registers:
- { id: 4, class: gpr }
- { id: 5, class: gpr }
liveins:
- - { reg: '%r6', virtual-reg: '%0' }
- - { reg: '%r7', virtual-reg: '%1' }
- - { reg: '%r18', virtual-reg: '%2' }
- - { reg: '%r19', virtual-reg: '%3' }
+ - { reg: '$r6', virtual-reg: '%0' }
+ - { reg: '$r7', virtual-reg: '%1' }
+ - { reg: '$r18', virtual-reg: '%2' }
+ - { reg: '$r19', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -290,17 +290,17 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %r6, %r7, %r18, %r19
+ liveins: $r6, $r7, $r18, $r19
- %3 = COPY %r19
- %2 = COPY %r18
- %1 = COPY %r7
- %0 = COPY %r6
+ %3 = COPY $r19
+ %2 = COPY $r18
+ %1 = COPY $r7
+ %0 = COPY $r6
%4 = SUB_R %1, %0, 0
- SFSUB_F_RI_LO killed %4, 0, implicit-def %sr
- %5 = SELECT %2, %3, 11, implicit %sr
- %rv = COPY %5
- RET implicit %rca, implicit %rv
+ SFSUB_F_RI_LO killed %4, 0, implicit-def $sr
+ %5 = SELECT %2, %3, 11, implicit $sr
+ $rv = COPY %5
+ RET implicit $rca, implicit $rv
...
---
@@ -316,10 +316,10 @@ registers:
- { id: 4, class: gpr }
- { id: 5, class: gpr }
liveins:
- - { reg: '%r6', virtual-reg: '%0' }
- - { reg: '%r7', virtual-reg: '%1' }
- - { reg: '%r18', virtual-reg: '%2' }
- - { reg: '%r19', virtual-reg: '%3' }
+ - { reg: '$r6', virtual-reg: '%0' }
+ - { reg: '$r7', virtual-reg: '%1' }
+ - { reg: '$r18', virtual-reg: '%2' }
+ - { reg: '$r19', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -336,17 +336,17 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %r6, %r7, %r18, %r19
+ liveins: $r6, $r7, $r18, $r19
- %3 = COPY %r19
- %2 = COPY %r18
- %1 = COPY %r7
- %0 = COPY %r6
+ %3 = COPY $r19
+ %2 = COPY $r18
+ %1 = COPY $r7
+ %0 = COPY $r6
%4 = SUB_R %1, %0, 0
- SFSUB_F_RI_LO killed %4, 0, implicit-def %sr
- %5 = SELECT %2, %3, 11, implicit %sr
- %rv = COPY %5
- RET implicit %rca, implicit %rv
+ SFSUB_F_RI_LO killed %4, 0, implicit-def $sr
+ %5 = SELECT %2, %3, 11, implicit $sr
+ $rv = COPY %5
+ RET implicit $rca, implicit $rv
...
---
@@ -362,10 +362,10 @@ registers:
- { id: 4, class: gpr }
- { id: 5, class: gpr }
liveins:
- - { reg: '%r6', virtual-reg: '%0' }
- - { reg: '%r7', virtual-reg: '%1' }
- - { reg: '%r18', virtual-reg: '%2' }
- - { reg: '%r19', virtual-reg: '%3' }
+ - { reg: '$r6', virtual-reg: '%0' }
+ - { reg: '$r7', virtual-reg: '%1' }
+ - { reg: '$r18', virtual-reg: '%2' }
+ - { reg: '$r19', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -382,17 +382,17 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %r6, %r7, %r18, %r19
+ liveins: $r6, $r7, $r18, $r19
- %3 = COPY %r19
- %2 = COPY %r18
- %1 = COPY %r7
- %0 = COPY %r6
+ %3 = COPY $r19
+ %2 = COPY $r18
+ %1 = COPY $r7
+ %0 = COPY $r6
%4 = SUB_R %1, %0, 0
- SFSUB_F_RI_LO killed %4, 0, implicit-def %sr
- %5 = SELECT %2, %3, 10, implicit %sr
- %rv = COPY %5
- RET implicit %rca, implicit %rv
+ SFSUB_F_RI_LO killed %4, 0, implicit-def $sr
+ %5 = SELECT %2, %3, 10, implicit $sr
+ $rv = COPY %5
+ RET implicit $rca, implicit $rv
...
---
@@ -408,10 +408,10 @@ registers:
- { id: 4, class: gpr }
- { id: 5, class: gpr }
liveins:
- - { reg: '%r6', virtual-reg: '%0' }
- - { reg: '%r7', virtual-reg: '%1' }
- - { reg: '%r18', virtual-reg: '%2' }
- - { reg: '%r19', virtual-reg: '%3' }
+ - { reg: '$r6', virtual-reg: '%0' }
+ - { reg: '$r7', virtual-reg: '%1' }
+ - { reg: '$r18', virtual-reg: '%2' }
+ - { reg: '$r19', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -428,17 +428,17 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %r6, %r7, %r18, %r19
+ liveins: $r6, $r7, $r18, $r19
- %3 = COPY %r19
- %2 = COPY %r18
- %1 = COPY %r7
- %0 = COPY %r6
+ %3 = COPY $r19
+ %2 = COPY $r18
+ %1 = COPY $r7
+ %0 = COPY $r6
%4 = SUB_R %1, %0, 0
- SFSUB_F_RI_LO killed %4, 0, implicit-def %sr
- %5 = SELECT %2, %3, 10, implicit %sr
- %rv = COPY %5
- RET implicit %rca, implicit %rv
+ SFSUB_F_RI_LO killed %4, 0, implicit-def $sr
+ %5 = SELECT %2, %3, 10, implicit $sr
+ $rv = COPY %5
+ RET implicit $rca, implicit $rv
...
---
@@ -454,10 +454,10 @@ registers:
- { id: 4, class: gpr }
- { id: 5, class: gpr }
liveins:
- - { reg: '%r6', virtual-reg: '%0' }
- - { reg: '%r7', virtual-reg: '%1' }
- - { reg: '%r18', virtual-reg: '%2' }
- - { reg: '%r19', virtual-reg: '%3' }
+ - { reg: '$r6', virtual-reg: '%0' }
+ - { reg: '$r7', virtual-reg: '%1' }
+ - { reg: '$r18', virtual-reg: '%2' }
+ - { reg: '$r19', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -474,17 +474,17 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %r6, %r7, %r18, %r19
+ liveins: $r6, $r7, $r18, $r19
- %3 = COPY %r19
- %2 = COPY %r18
- %1 = COPY %r7
- %0 = COPY %r6
+ %3 = COPY $r19
+ %2 = COPY $r18
+ %1 = COPY $r7
+ %0 = COPY $r6
%4 = SUB_R %1, %0, 0
- SFSUB_F_RI_LO killed %4, 1, implicit-def %sr
- %5 = SELECT %2, %3, 13, implicit %sr
- %rv = COPY %5
- RET implicit %rca, implicit %rv
+ SFSUB_F_RI_LO killed %4, 1, implicit-def $sr
+ %5 = SELECT %2, %3, 13, implicit $sr
+ $rv = COPY %5
+ RET implicit $rca, implicit $rv
...
---
@@ -517,10 +517,10 @@ registers:
- { id: 21, class: gpr }
- { id: 22, class: gpr }
liveins:
- - { reg: '%r6', virtual-reg: '%1' }
- - { reg: '%r7', virtual-reg: '%2' }
- - { reg: '%r18', virtual-reg: '%3' }
- - { reg: '%r19', virtual-reg: '%4' }
+ - { reg: '$r6', virtual-reg: '%1' }
+ - { reg: '$r7', virtual-reg: '%2' }
+ - { reg: '$r18', virtual-reg: '%3' }
+ - { reg: '$r19', virtual-reg: '%4' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -538,63 +538,63 @@ frameInfo:
body: |
bb.0.entry:
successors: %bb.4.return, %bb.1.if.end
- liveins: %r6, %r7, %r18, %r19
+ liveins: $r6, $r7, $r18, $r19
- %4 = COPY %r19
- %3 = COPY %r18
- %2 = COPY %r7
- %1 = COPY %r6
- SFSUB_F_RI_LO %1, 0, implicit-def %sr
- %5 = SCC 6, implicit %sr
- SFSUB_F_RR %1, %2, implicit-def %sr
- %6 = SCC 4, implicit %sr
+ %4 = COPY $r19
+ %3 = COPY $r18
+ %2 = COPY $r7
+ %1 = COPY $r6
+ SFSUB_F_RI_LO %1, 0, implicit-def $sr
+ %5 = SCC 6, implicit $sr
+ SFSUB_F_RR %1, %2, implicit-def $sr
+ %6 = SCC 4, implicit $sr
%7 = AND_R killed %5, killed %6, 0
%8 = SLI 1
%9 = AND_R killed %7, %8, 0
- SFSUB_F_RI_LO killed %9, 0, implicit-def %sr
- BRCC %bb.4.return, 6, implicit %sr
+ SFSUB_F_RI_LO killed %9, 0, implicit-def $sr
+ BRCC %bb.4.return, 6, implicit $sr
BT %bb.1.if.end
bb.1.if.end:
successors: %bb.4.return, %bb.2.if.end6
- SFSUB_F_RI_LO %2, 0, implicit-def %sr
- %10 = SCC 6, implicit %sr
- SFSUB_F_RR %2, %3, implicit-def %sr
- %11 = SCC 4, implicit %sr
+ SFSUB_F_RI_LO %2, 0, implicit-def $sr
+ %10 = SCC 6, implicit $sr
+ SFSUB_F_RR %2, %3, implicit-def $sr
+ %11 = SCC 4, implicit $sr
%12 = AND_R killed %10, killed %11, 0
%14 = AND_R killed %12, %8, 0
- SFSUB_F_RI_LO killed %14, 0, implicit-def %sr
- BRCC %bb.4.return, 6, implicit %sr
+ SFSUB_F_RI_LO killed %14, 0, implicit-def $sr
+ BRCC %bb.4.return, 6, implicit $sr
BT %bb.2.if.end6
bb.2.if.end6:
successors: %bb.4.return, %bb.3.if.end11
- SFSUB_F_RI_LO %3, 0, implicit-def %sr
- %15 = SCC 6, implicit %sr
- SFSUB_F_RR %3, %4, implicit-def %sr
- %16 = SCC 4, implicit %sr
+ SFSUB_F_RI_LO %3, 0, implicit-def $sr
+ %15 = SCC 6, implicit $sr
+ SFSUB_F_RR %3, %4, implicit-def $sr
+ %16 = SCC 4, implicit $sr
%17 = AND_R killed %15, killed %16, 0
%18 = SLI 1
%19 = AND_R killed %17, killed %18, 0
- SFSUB_F_RI_LO killed %19, 0, implicit-def %sr
- BRCC %bb.4.return, 6, implicit %sr
+ SFSUB_F_RI_LO killed %19, 0, implicit-def $sr
+ BRCC %bb.4.return, 6, implicit $sr
BT %bb.3.if.end11
bb.3.if.end11:
%20 = SLI 21
- SFSUB_F_RR %4, %1, implicit-def %sr
- %21 = SELECT %2, %20, 4, implicit %sr
- SFSUB_F_RI_LO %4, 0, implicit-def %sr
- %22 = SELECT killed %21, %20, 6, implicit %sr
- %rv = COPY %22
- RET implicit %rca, implicit %rv
+ SFSUB_F_RR %4, %1, implicit-def $sr
+ %21 = SELECT %2, %20, 4, implicit $sr
+ SFSUB_F_RI_LO %4, 0, implicit-def $sr
+ %22 = SELECT killed %21, %20, 6, implicit $sr
+ $rv = COPY %22
+ RET implicit $rca, implicit $rv
bb.4.return:
%0 = PHI %3, %bb.0.entry, %4, %bb.1.if.end, %1, %bb.2.if.end6
- %rv = COPY %0
- RET implicit %rca, implicit %rv
+ $rv = COPY %0
+ RET implicit $rca, implicit $rv
...
---
@@ -637,16 +637,16 @@ body: |
%5 = OR_I_LO killed %4, target-flags(lanai-lo) @b
%6 = LDW_RI killed %5, 0, 0 :: (load 4 from @b, !tbaa !0)
%0 = SUB_R killed %6, killed %3, 0
- SFSUB_F_RI_LO %0, 0, implicit-def %sr
- BRCC %bb.3.if.end, 10, implicit %sr
+ SFSUB_F_RI_LO %0, 0, implicit-def $sr
+ BRCC %bb.3.if.end, 10, implicit $sr
BT %bb.1.if.then
bb.1.if.then:
successors: %bb.2.while.body
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
- CALL @g, csr, implicit-def dead %rca, implicit %sp, implicit-def %sp, implicit-def %rv
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ CALL @g, csr, implicit-def dead $rca, implicit $sp, implicit-def $sp, implicit-def $rv
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
bb.2.while.body:
successors: %bb.2.while.body
@@ -655,17 +655,17 @@ body: |
bb.3.if.end:
successors: %bb.4.if.then4, %bb.6.if.end7
- liveins: %sr
+ liveins: $sr
- BRCC %bb.6.if.end7, 14, implicit %sr
+ BRCC %bb.6.if.end7, 14, implicit $sr
BT %bb.4.if.then4
bb.4.if.then4:
successors: %bb.5.while.body6
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
- CALL @g, csr, implicit-def dead %rca, implicit %sp, implicit-def %sp, implicit-def %rv
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ CALL @g, csr, implicit-def dead $rca, implicit $sp, implicit-def $sp, implicit-def $rv
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
bb.5.while.body6:
successors: %bb.5.while.body6
@@ -673,6 +673,6 @@ body: |
BT %bb.5.while.body6
bb.6.if.end7:
- RET implicit %rca
+ RET implicit $rca
...
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/addrspace-memoperands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/addrspace-memoperands.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/addrspace-memoperands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/addrspace-memoperands.mir Wed Jan 31 14:04:26 2018
@@ -13,14 +13,14 @@ body: |
bb.0:
; CHECK-LABEL: name: addrspace_memoperands
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load 8, addrspace 1)
; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4, align 2, addrspace 3)
; CHECK: G_STORE [[LOAD]](s64), [[COPY]](p0) :: (store 8, addrspace 1)
; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p0) :: (store 4, align 2, addrspace 3)
; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p0) :: (store 4)
; CHECK: RET_ReallyLR
- %0:_(p0) = COPY %x0
+ %0:_(p0) = COPY $x0
%1:_(s64) = G_LOAD %0(p0) :: (load 8, addrspace 1)
%2:_(s32) = G_LOAD %0(p0) :: (load 4, align 2, addrspace 3)
G_STORE %1(s64), %0(p0) :: (store 8, addrspace 1)
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/atomic-memoperands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/atomic-memoperands.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/atomic-memoperands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/atomic-memoperands.mir Wed Jan 31 14:04:26 2018
@@ -14,7 +14,7 @@ body: |
bb.0:
; CHECK-LABEL: name: atomic_memoperands
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load unordered 8)
; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load monotonic 4)
; CHECK: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load acquire 2)
@@ -22,7 +22,7 @@ body: |
; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p0) :: (store acq_rel 4)
; CHECK: G_STORE [[LOAD]](s64), [[COPY]](p0) :: (store syncscope("singlethread") seq_cst 8)
; CHECK: RET_ReallyLR
- %0:_(p0) = COPY %x0
+ %0:_(p0) = COPY $x0
%1:_(s64) = G_LOAD %0(p0) :: (load unordered 8)
%2:_(s32) = G_LOAD %0(p0) :: (load monotonic 4)
%3:_(s16) = G_LOAD %0(p0) :: (load acquire 2)
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/cfi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/cfi.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/cfi.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/cfi.mir Wed Jan 31 14:04:26 2018
@@ -17,26 +17,26 @@ name: trivial_fp_func
# CHECK-LABEL: name: trivial_fp_func
body: |
bb.0.entry:
- ; CHECK: CFI_INSTRUCTION def_cfa %w29, 16
- frame-setup CFI_INSTRUCTION def_cfa %w29, 16
- ; CHECK: CFI_INSTRUCTION def_cfa_register %w29
- frame-setup CFI_INSTRUCTION def_cfa_register %w29
+ ; CHECK: CFI_INSTRUCTION def_cfa $w29, 16
+ frame-setup CFI_INSTRUCTION def_cfa $w29, 16
+ ; CHECK: CFI_INSTRUCTION def_cfa_register $w29
+ frame-setup CFI_INSTRUCTION def_cfa_register $w29
; CHECK: CFI_INSTRUCTION def_cfa_offset -8
frame-setup CFI_INSTRUCTION def_cfa_offset -8
- ; CHECK: CFI_INSTRUCTION offset %w30, -8
- frame-setup CFI_INSTRUCTION offset %w30, -8
- ; CHECK: CFI_INSTRUCTION rel_offset %w30, -8
- frame-setup CFI_INSTRUCTION rel_offset %w30, -8
+ ; CHECK: CFI_INSTRUCTION offset $w30, -8
+ frame-setup CFI_INSTRUCTION offset $w30, -8
+ ; CHECK: CFI_INSTRUCTION rel_offset $w30, -8
+ frame-setup CFI_INSTRUCTION rel_offset $w30, -8
; CHECK: CFI_INSTRUCTION adjust_cfa_offset -8
frame-setup CFI_INSTRUCTION adjust_cfa_offset -8
- CFI_INSTRUCTION restore %w30
- ; CHECK: CFI_INSTRUCTION restore %w30
- CFI_INSTRUCTION undefined %w30
- ; CHECK: CFI_INSTRUCTION undefined %w30
- CFI_INSTRUCTION same_value %w29
- ; CHECK: CFI_INSTRUCTION same_value %w29
- CFI_INSTRUCTION register %w20, %w30
- ; CHECK: CFI_INSTRUCTION register %w20, %w30
+ CFI_INSTRUCTION restore $w30
+ ; CHECK: CFI_INSTRUCTION restore $w30
+ CFI_INSTRUCTION undefined $w30
+ ; CHECK: CFI_INSTRUCTION undefined $w30
+ CFI_INSTRUCTION same_value $w29
+ ; CHECK: CFI_INSTRUCTION same_value $w29
+ CFI_INSTRUCTION register $w20, $w30
+ ; CHECK: CFI_INSTRUCTION register $w20, $w30
CFI_INSTRUCTION remember_state
; CHECK: CFI_INSTRUCTION remember_state
CFI_INSTRUCTION restore_state
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/expected-target-flag-name.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/expected-target-flag-name.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/expected-target-flag-name.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/expected-target-flag-name.mir Wed Jan 31 14:04:26 2018
@@ -16,8 +16,8 @@
name: sub_small
body: |
bb.0.entry:
- %x8 = ADRP target-flags(aarch64-page) @var_i32
+ $x8 = ADRP target-flags(aarch64-page) @var_i32
; CHECK: [[@LINE+1]]:60: expected the name of the target flag
- %w0 = LDRWui killed %x8, target-flags(aarch64-pageoff, ) @var_i32
- RET_ReallyLR implicit %w0
+ $w0 = LDRWui killed $x8, target-flags(aarch64-pageoff, ) @var_i32
+ RET_ReallyLR implicit $w0
...
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir Wed Jan 31 14:04:26 2018
@@ -14,8 +14,8 @@ registers:
- { id: 0, class: _ }
body: |
bb.0:
- liveins: %w0
+ liveins: $w0
; ERR: generic virtual registers must have a type
; ERR-NEXT: %0
- %0 = G_ADD i32 %w0, %w0
+ %0 = G_ADD i32 $w0, $w0
...
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir Wed Jan 31 14:04:26 2018
@@ -15,8 +15,8 @@ registers:
- { id: 0, class: gpr }
body: |
bb.0:
- liveins: %w0
+ liveins: $w0
; ERR: generic virtual registers must have a type
; ERR-NEXT: %0
- %0 = G_ADD i32 %w0, %w0
+ %0 = G_ADD i32 $w0, $w0
...
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/intrinsics.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/intrinsics.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/intrinsics.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/intrinsics.mir Wed Jan 31 14:04:26 2018
@@ -9,10 +9,10 @@
...
---
# Completely invalid code, but it checks that intrinsics round-trip properly.
-# CHECK: %x0 = COPY intrinsic(@llvm.returnaddress)
+# CHECK: $x0 = COPY intrinsic(@llvm.returnaddress)
name: use_intrin
body: |
bb.0:
- %x0 = COPY intrinsic(@llvm.returnaddress)
+ $x0 = COPY intrinsic(@llvm.returnaddress)
RET_ReallyLR
...
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/invalid-target-flag-name.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/invalid-target-flag-name.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/invalid-target-flag-name.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/invalid-target-flag-name.mir Wed Jan 31 14:04:26 2018
@@ -16,8 +16,8 @@
name: sub_small
body: |
bb.0.entry:
- %x8 = ADRP target-flags(aarch64-page) @var_i32
+ $x8 = ADRP target-flags(aarch64-page) @var_i32
; CHECK: [[@LINE+1]]:60: use of undefined target flag 'ncc'
- %w0 = LDRWui killed %x8, target-flags(aarch64-pageoff, ncc) @var_i32
- RET_ReallyLR implicit %w0
+ $w0 = LDRWui killed $x8, target-flags(aarch64-pageoff, ncc) @var_i32
+ RET_ReallyLR implicit $w0
...
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/invalid-target-memoperands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/invalid-target-memoperands.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/invalid-target-memoperands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/invalid-target-memoperands.mir Wed Jan 31 14:04:26 2018
@@ -12,7 +12,7 @@ name: target_memoperands_erro
body: |
bb.0:
- %0:_(p0) = COPY %x0
+ %0:_(p0) = COPY $x0
; CHECK: [[@LINE+1]]:35: use of undefined target MMO flag 'aarch64-invalid'
%1:_(s64) = G_LOAD %0(p0) :: ("aarch64-invalid" load 8)
RET_ReallyLR
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir Wed Jan 31 14:04:26 2018
@@ -17,12 +17,12 @@
name: trivial_fp_func
body: |
bb.0.entry:
- liveins: %lr, %fp, %lr, %fp
+ liveins: $lr, $fp, $lr, $fp
- %sp = frame-setup STPXpre killed %fp, killed %lr, %sp, -2
- %fp = frame-setup ADDXri %sp, 0, 0
- BL @foo, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
- ; CHECK: %sp, %fp, %lr = LDPXpost %sp, 2
- %sp, %fp, %lr = LDPXpost %sp, 2
+ $sp = frame-setup STPXpre killed $fp, killed $lr, $sp, -2
+ $fp = frame-setup ADDXri $sp, 0, 0
+ BL @foo, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
+ ; CHECK: $sp, $fp, $lr = LDPXpost $sp, 2
+ $sp, $fp, $lr = LDPXpost $sp, 2
RET_ReallyLR
...
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/register-operand-bank.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/register-operand-bank.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/register-operand-bank.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/register-operand-bank.mir Wed Jan 31 14:04:26 2018
@@ -12,9 +12,9 @@
name: func
body: |
bb.0:
- %0 : gpr(s64) = COPY %x9
- %x9 = COPY %0
+ %0 : gpr(s64) = COPY $x9
+ $x9 = COPY %0
- %3 : fpr(s64) = COPY %d0
- %d1 = COPY %3 : fpr
+ %3 : fpr(s64) = COPY $d0
+ $d1 = COPY %3 : fpr
...
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/swp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/swp.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/swp.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/swp.mir Wed Jan 31 14:04:26 2018
@@ -18,16 +18,16 @@ registers:
- { id: 1, class: gpr32 }
- { id: 2, class: gpr32 }
liveins:
- - { reg: '%x0', virtual-reg: '%0' }
+ - { reg: '$x0', virtual-reg: '%0' }
body: |
bb.0.entry:
- liveins: %x0
+ liveins: $x0
; CHECK-LABEL: swp
; CHECK: {{[0-9]+}}:gpr32 = SWPW killed %1, %0 :: (volatile load store monotonic 4 on %ir.addr)
- %0:gpr64common = COPY %x0
+ %0:gpr64common = COPY $x0
%1:gpr32 = MOVi32imm 1
%2:gpr32 = SWPW killed %1, %0 :: (volatile load store monotonic 4 on %ir.addr)
- %w0 = COPY %2
- RET_ReallyLR implicit %w0
+ $w0 = COPY %2
+ RET_ReallyLR implicit $w0
...
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/target-flags.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/target-flags.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/target-flags.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/target-flags.mir Wed Jan 31 14:04:26 2018
@@ -21,19 +21,19 @@
name: sub_small
body: |
bb.0.entry:
- ; CHECK: %x8 = ADRP target-flags(aarch64-page) @var_i32
- ; CHECK-NEXT: %x9 = ADRP target-flags(aarch64-page) @var_i64
- ; CHECK-NEXT: %w10 = LDRWui %x8, target-flags(aarch64-pageoff, aarch64-nc) @var_i32
- ; CHECK-NEXT: %x11 = LDRXui %x9, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @var_i64
- ; CHECK: STRWui killed %w10, killed %x8, target-flags(aarch64-nc) @var_i32
- ; CHECK: STRXui killed %x11, killed %x9, target-flags(aarch64-pageoff, aarch64-nc) @var_i64
- %x8 = ADRP target-flags(aarch64-page) @var_i32
- %x9 = ADRP target-flags(aarch64-page) @var_i64
- %w10 = LDRWui %x8, target-flags(aarch64-pageoff, aarch64-nc) @var_i32
- %x11 = LDRXui %x9, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @var_i64
- %w10 = SUBWri killed %w10, 4095, 0
- %x11 = SUBXri killed %x11, 52, 0
- STRWui killed %w10, killed %x8, target-flags(aarch64-nc) @var_i32
- STRXui killed %x11, killed %x9, target-flags(aarch64-pageoff, aarch64-nc) @var_i64
+ ; CHECK: $x8 = ADRP target-flags(aarch64-page) @var_i32
+ ; CHECK-NEXT: $x9 = ADRP target-flags(aarch64-page) @var_i64
+ ; CHECK-NEXT: $w10 = LDRWui $x8, target-flags(aarch64-pageoff, aarch64-nc) @var_i32
+ ; CHECK-NEXT: $x11 = LDRXui $x9, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @var_i64
+ ; CHECK: STRWui killed $w10, killed $x8, target-flags(aarch64-nc) @var_i32
+ ; CHECK: STRXui killed $x11, killed $x9, target-flags(aarch64-pageoff, aarch64-nc) @var_i64
+ $x8 = ADRP target-flags(aarch64-page) @var_i32
+ $x9 = ADRP target-flags(aarch64-page) @var_i64
+ $w10 = LDRWui $x8, target-flags(aarch64-pageoff, aarch64-nc) @var_i32
+ $x11 = LDRXui $x9, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @var_i64
+ $w10 = SUBWri killed $w10, 4095, 0
+ $x11 = SUBXri killed $x11, 52, 0
+ STRWui killed $w10, killed $x8, target-flags(aarch64-nc) @var_i32
+ STRXui killed $x11, killed $x9, target-flags(aarch64-pageoff, aarch64-nc) @var_i64
RET_ReallyLR
...
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/target-memoperands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/target-memoperands.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/target-memoperands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/target-memoperands.mir Wed Jan 31 14:04:26 2018
@@ -14,13 +14,13 @@ body: |
bb.0:
; CHECK-LABEL: name: target_memoperands
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: ("aarch64-suppress-pair" load 8)
; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: ("aarch64-strided-access" load 4)
; CHECK: G_STORE [[LOAD]](s64), [[COPY]](p0) :: ("aarch64-suppress-pair" store 8)
; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p0) :: ("aarch64-strided-access" store 4)
; CHECK: RET_ReallyLR
- %0:_(p0) = COPY %x0
+ %0:_(p0) = COPY $x0
%1:_(s64) = G_LOAD %0(p0) :: ("aarch64-suppress-pair" load 8)
%2:_(s32) = G_LOAD %0(p0) :: ("aarch64-strided-access" load 4)
G_STORE %1(s64), %0(p0) :: ("aarch64-suppress-pair" store 8)
Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir Wed Jan 31 14:04:26 2018
@@ -20,30 +20,30 @@
---
name: float
liveins:
- - { reg: '%sgpr0_sgpr1' }
+ - { reg: '$sgpr0_sgpr1' }
frameInfo:
maxAlignment: 8
body: |
bb.0.entry:
- liveins: %sgpr0_sgpr1
+ liveins: $sgpr0_sgpr1
- %sgpr2_sgpr3 = S_GETPC_B64
+ $sgpr2_sgpr3 = S_GETPC_B64
; CHECK: [[@LINE+1]]:45: expected the name of the target index
- %sgpr2 = S_ADD_U32 %sgpr2, target-index(0), implicit-def %scc, implicit-def %scc
- %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
- %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
- %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11
- %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
- %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
- %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
- %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
- %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
- %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
- %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0
- %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9
- %sgpr7 = S_MOV_B32 61440
- %sgpr6 = S_MOV_B32 -1
- %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec
- BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec
+ $sgpr2 = S_ADD_U32 $sgpr2, target-index(0), implicit-def $scc, implicit-def $scc
+ $sgpr3 = S_ADDC_U32 $sgpr3, 0, implicit-def $scc, implicit $scc, implicit-def $scc, implicit $scc
+ $sgpr4_sgpr5 = S_LSHR_B64 $sgpr2_sgpr3, 32, implicit-def dead $scc
+ $sgpr6 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 11
+ $sgpr7 = S_ASHR_I32 $sgpr6, 31, implicit-def dead $scc
+ $sgpr6_sgpr7 = S_LSHL_B64 $sgpr6_sgpr7, 2, implicit-def dead $scc
+ $sgpr2 = S_ADD_U32 $sgpr2, @float_gv, implicit-def $scc
+ $sgpr3 = S_ADDC_U32 $sgpr4, 0, implicit-def dead $scc, implicit $scc
+ $sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc
+ $sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc
+ $sgpr2 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 0
+ $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 9
+ $sgpr7 = S_MOV_B32 61440
+ $sgpr6 = S_MOV_B32 -1
+ $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec
+ BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM
...
Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir Wed Jan 31 14:04:26 2018
@@ -20,30 +20,30 @@
---
name: float
liveins:
- - { reg: '%sgpr0_sgpr1' }
+ - { reg: '$sgpr0_sgpr1' }
frameInfo:
maxAlignment: 8
body: |
bb.0.entry:
- liveins: %sgpr0_sgpr1
+ liveins: $sgpr0_sgpr1
- %sgpr2_sgpr3 = S_GETPC_B64
+ $sgpr2_sgpr3 = S_GETPC_B64
; CHECK: [[@LINE+1]]:45: use of undefined target index 'constdata-start'
- %sgpr2 = S_ADD_U32 %sgpr2, target-index(constdata-start), implicit-def %scc, implicit-def %scc
- %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
- %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
- %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11
- %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
- %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
- %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
- %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
- %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
- %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
- %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0
- %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9
- %sgpr7 = S_MOV_B32 61440
- %sgpr6 = S_MOV_B32 -1
- %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec
- BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec
+ $sgpr2 = S_ADD_U32 $sgpr2, target-index(constdata-start), implicit-def $scc, implicit-def $scc
+ $sgpr3 = S_ADDC_U32 $sgpr3, 0, implicit-def $scc, implicit $scc, implicit-def $scc, implicit $scc
+ $sgpr4_sgpr5 = S_LSHR_B64 $sgpr2_sgpr3, 32, implicit-def dead $scc
+ $sgpr6 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 11
+ $sgpr7 = S_ASHR_I32 $sgpr6, 31, implicit-def dead $scc
+ $sgpr6_sgpr7 = S_LSHL_B64 $sgpr6_sgpr7, 2, implicit-def dead $scc
+ $sgpr2 = S_ADD_U32 $sgpr2, @float_gv, implicit-def $scc
+ $sgpr3 = S_ADDC_U32 $sgpr4, 0, implicit-def dead $scc, implicit $scc
+ $sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc
+ $sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc
+ $sgpr2 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 0
+ $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 9
+ $sgpr7 = S_MOV_B32 61440
+ $sgpr6 = S_MOV_B32 -1
+ $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec
+ BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM
...
Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/syncscopes.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/syncscopes.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/syncscopes.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/syncscopes.mir Wed Jan 31 14:04:26 2018
@@ -42,9 +42,9 @@
!0 = !{i32 1}
# GCN-LABEL: name: syncscopes
-# GCN: FLAT_STORE_DWORD killed %vgpr0_vgpr1, killed %vgpr2, 0, -1, 0, implicit %exec, implicit %flat_scr :: (volatile non-temporal store syncscope("agent") seq_cst 4 into %ir.agent_out, addrspace 4)
-# GCN: FLAT_STORE_DWORD killed %vgpr0_vgpr1, killed %vgpr2, 0, -1, 0, implicit %exec, implicit %flat_scr :: (volatile non-temporal store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out, addrspace 4)
-# GCN: FLAT_STORE_DWORD killed %vgpr0_vgpr1, killed %vgpr2, 0, -1, 0, implicit %exec, implicit %flat_scr :: (volatile non-temporal store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out, addrspace 4)
+# GCN: FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("agent") seq_cst 4 into %ir.agent_out, addrspace 4)
+# GCN: FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out, addrspace 4)
+# GCN: FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out, addrspace 4)
...
---
name: syncscopes
@@ -55,7 +55,7 @@ regBankSelected: false
selected: false
tracksRegLiveness: true
liveins:
- - { reg: '%sgpr4_sgpr5' }
+ - { reg: '$sgpr4_sgpr5' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -71,30 +71,30 @@ frameInfo:
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
- liveins: %sgpr4_sgpr5
+ liveins: $sgpr4_sgpr5
S_WAITCNT 0
- %sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM %sgpr4_sgpr5, 8, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
- %sgpr6 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
- %sgpr2_sgpr3 = S_LOAD_DWORDX2_IMM %sgpr4_sgpr5, 24, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
- %sgpr7 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 16, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
- %sgpr8 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 32, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
+ $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr4_sgpr5, 8, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
+ $sgpr6 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
+ $sgpr2_sgpr3 = S_LOAD_DWORDX2_IMM $sgpr4_sgpr5, 24, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
+ $sgpr7 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 16, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
+ $sgpr8 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 32, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
S_WAITCNT 127
- %vgpr0 = V_MOV_B32_e32 %sgpr0, implicit %exec, implicit-def %vgpr0_vgpr1, implicit %sgpr0_sgpr1
- %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr4_sgpr5, 40, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
- %vgpr1 = V_MOV_B32_e32 killed %sgpr1, implicit %exec, implicit killed %sgpr0_sgpr1, implicit %sgpr0_sgpr1, implicit %exec
- %vgpr2 = V_MOV_B32_e32 killed %sgpr6, implicit %exec, implicit %exec
- FLAT_STORE_DWORD killed %vgpr0_vgpr1, killed %vgpr2, 0, -1, 0, implicit %exec, implicit %flat_scr :: (volatile non-temporal store syncscope("agent") seq_cst 4 into %ir.agent_out)
+ $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
+ $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr4_sgpr5, 40, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
+ $vgpr1 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit killed $sgpr0_sgpr1, implicit $sgpr0_sgpr1, implicit $exec
+ $vgpr2 = V_MOV_B32_e32 killed $sgpr6, implicit $exec, implicit $exec
+ FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("agent") seq_cst 4 into %ir.agent_out)
S_WAITCNT 112
- %vgpr0 = V_MOV_B32_e32 %sgpr2, implicit %exec, implicit-def %vgpr0_vgpr1, implicit %sgpr2_sgpr3
- %vgpr1 = V_MOV_B32_e32 killed %sgpr3, implicit %exec, implicit killed %sgpr2_sgpr3, implicit %sgpr2_sgpr3, implicit %exec
- %vgpr2 = V_MOV_B32_e32 killed %sgpr7, implicit %exec, implicit %exec
- FLAT_STORE_DWORD killed %vgpr0_vgpr1, killed %vgpr2, 0, -1, 0, implicit %exec, implicit %flat_scr :: (volatile non-temporal store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out)
+ $vgpr0 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr2_sgpr3
+ $vgpr1 = V_MOV_B32_e32 killed $sgpr3, implicit $exec, implicit killed $sgpr2_sgpr3, implicit $sgpr2_sgpr3, implicit $exec
+ $vgpr2 = V_MOV_B32_e32 killed $sgpr7, implicit $exec, implicit $exec
+ FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out)
S_WAITCNT 112
- %vgpr0 = V_MOV_B32_e32 %sgpr4, implicit %exec, implicit-def %vgpr0_vgpr1, implicit %sgpr4_sgpr5
- %vgpr1 = V_MOV_B32_e32 killed %sgpr5, implicit %exec, implicit killed %sgpr4_sgpr5, implicit %sgpr4_sgpr5, implicit %exec
- %vgpr2 = V_MOV_B32_e32 killed %sgpr8, implicit %exec, implicit %exec
- FLAT_STORE_DWORD killed %vgpr0_vgpr1, killed %vgpr2, 0, -1, 0, implicit %exec, implicit %flat_scr :: (volatile non-temporal store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out)
+ $vgpr0 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr4_sgpr5
+ $vgpr1 = V_MOV_B32_e32 killed $sgpr5, implicit $exec, implicit killed $sgpr4_sgpr5, implicit $sgpr4_sgpr5, implicit $exec
+ $vgpr2 = V_MOV_B32_e32 killed $sgpr8, implicit $exec, implicit $exec
+ FLAT_STORE_DWORD killed $vgpr0_vgpr1, killed $vgpr2, 0, -1, 0, implicit $exec, implicit $flat_scr :: (volatile non-temporal store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out)
S_ENDPGM
...
Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/target-flags.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/target-flags.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/target-flags.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/target-flags.mir Wed Jan 31 14:04:26 2018
@@ -12,7 +12,7 @@
name: flags
liveins:
- - { reg: '%sgpr0_sgpr1' }
+ - { reg: '$sgpr0_sgpr1' }
frameInfo:
maxAlignment: 8
registers:
@@ -20,12 +20,12 @@ registers:
- { id: 1, class: sreg_64, preferred-register: '' }
body: |
bb.0:
- liveins: %sgpr0_sgpr1
+ liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: flags
- ; CHECK: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead %scc
+ ; CHECK: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead $scc
; CHECK: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo
; CHECK: S_ENDPGM
- %0 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead %scc
+ %0 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead $scc
%1 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo
S_ENDPGM
Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir Wed Jan 31 14:04:26 2018
@@ -28,60 +28,60 @@
---
name: float
liveins:
- - { reg: '%sgpr0_sgpr1' }
+ - { reg: '$sgpr0_sgpr1' }
frameInfo:
maxAlignment: 8
body: |
bb.0.entry:
- liveins: %sgpr0_sgpr1
+ liveins: $sgpr0_sgpr1
- %sgpr2_sgpr3 = S_GETPC_B64
- ; CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc
- %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc
- %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
- %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
- %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11, 0
- %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
- %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
- %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
- %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
- %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
- %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
- %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0, 0
- %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9, 0
- %sgpr7 = S_MOV_B32 61440
- %sgpr6 = S_MOV_B32 -1
- %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec
- BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec
+ $sgpr2_sgpr3 = S_GETPC_B64
+ ; CHECK: $sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start), implicit-def $scc, implicit-def $scc
+ $sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start), implicit-def $scc, implicit-def $scc
+ $sgpr3 = S_ADDC_U32 $sgpr3, 0, implicit-def $scc, implicit $scc, implicit-def $scc, implicit $scc
+ $sgpr4_sgpr5 = S_LSHR_B64 $sgpr2_sgpr3, 32, implicit-def dead $scc
+ $sgpr6 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 11, 0
+ $sgpr7 = S_ASHR_I32 $sgpr6, 31, implicit-def dead $scc
+ $sgpr6_sgpr7 = S_LSHL_B64 $sgpr6_sgpr7, 2, implicit-def dead $scc
+ $sgpr2 = S_ADD_U32 $sgpr2, @float_gv, implicit-def $scc
+ $sgpr3 = S_ADDC_U32 $sgpr4, 0, implicit-def dead $scc, implicit $scc
+ $sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc
+ $sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc
+ $sgpr2 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 0, 0
+ $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 9, 0
+ $sgpr7 = S_MOV_B32 61440
+ $sgpr6 = S_MOV_B32 -1
+ $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec
+ BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM
...
---
name: float2
liveins:
- - { reg: '%sgpr0_sgpr1' }
+ - { reg: '$sgpr0_sgpr1' }
frameInfo:
maxAlignment: 8
body: |
bb.0.entry:
- liveins: %sgpr0_sgpr1
+ liveins: $sgpr0_sgpr1
- %sgpr2_sgpr3 = S_GETPC_B64
- ; CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc
- %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc
- %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
- %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
- %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11, 0
- %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
- %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
- %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
- %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
- %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
- %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
- %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0, 0
- %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9, 0
- %sgpr7 = S_MOV_B32 61440
- %sgpr6 = S_MOV_B32 -1
- %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec
- BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec
+ $sgpr2_sgpr3 = S_GETPC_B64
+ ; CHECK: $sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def $scc, implicit-def $scc
+ $sgpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def $scc, implicit-def $scc
+ $sgpr3 = S_ADDC_U32 $sgpr3, 0, implicit-def $scc, implicit $scc, implicit-def $scc, implicit $scc
+ $sgpr4_sgpr5 = S_LSHR_B64 $sgpr2_sgpr3, 32, implicit-def dead $scc
+ $sgpr6 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 11, 0
+ $sgpr7 = S_ASHR_I32 $sgpr6, 31, implicit-def dead $scc
+ $sgpr6_sgpr7 = S_LSHL_B64 $sgpr6_sgpr7, 2, implicit-def dead $scc
+ $sgpr2 = S_ADD_U32 $sgpr2, @float_gv, implicit-def $scc
+ $sgpr3 = S_ADDC_U32 $sgpr4, 0, implicit-def dead $scc, implicit $scc
+ $sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc
+ $sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc
+ $sgpr2 = S_LOAD_DWORD_IMM $sgpr4_sgpr5, 0, 0
+ $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 9, 0
+ $sgpr7 = S_MOV_B32 61440
+ $sgpr6 = S_MOV_B32 -1
+ $vgpr0 = V_MOV_B32_e32 killed $sgpr2, implicit $exec
+ BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec
S_ENDPGM
...
Modified: llvm/trunk/test/CodeGen/MIR/ARM/bundled-instructions.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/ARM/bundled-instructions.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/ARM/bundled-instructions.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/ARM/bundled-instructions.mir Wed Jan 31 14:04:26 2018
@@ -23,53 +23,53 @@
name: test1
tracksRegLiveness: true
liveins:
- - { reg: '%r0' }
+ - { reg: '$r0' }
body: |
bb.0.entry:
- liveins: %r0
+ liveins: $r0
; CHECK-LABEL: name: test1
- ; CHECK: %r1 = t2MOVi 0, 14, %noreg, %noreg
- ; CHECK-NEXT: t2CMNri killed %r0, 78, 14, %noreg, implicit-def %cpsr
- ; CHECK-NEXT: BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr {
- ; CHECK-NEXT: t2IT 12, 8, implicit-def %itstate
- ; CHECK-NEXT: %r1 = t2MOVi 1, 12, killed %cpsr, %noreg, implicit internal killed %itstate
+ ; CHECK: $r1 = t2MOVi 0, 14, $noreg, $noreg
+ ; CHECK-NEXT: t2CMNri killed $r0, 78, 14, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr {
+ ; CHECK-NEXT: t2IT 12, 8, implicit-def $itstate
+ ; CHECK-NEXT: $r1 = t2MOVi 1, 12, killed $cpsr, $noreg, implicit internal killed $itstate
; CHECK-NEXT: }
- ; CHECK-NEXT: %r0 = tMOVr killed %r1, 14, %noreg
- ; CHECK-NEXT: tBX_RET 14, %noreg, implicit killed %r0
- %r1 = t2MOVi 0, 14, _, _
- t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr
- BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr {
- t2IT 12, 8, implicit-def %itstate
- %r1 = t2MOVi 1, 12, killed %cpsr, _, implicit internal killed %itstate
+ ; CHECK-NEXT: $r0 = tMOVr killed $r1, 14, $noreg
+ ; CHECK-NEXT: tBX_RET 14, $noreg, implicit killed $r0
+ $r1 = t2MOVi 0, 14, _, _
+ t2CMNri killed $r0, 78, 14, _, implicit-def $cpsr
+ BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr {
+ t2IT 12, 8, implicit-def $itstate
+ $r1 = t2MOVi 1, 12, killed $cpsr, _, implicit internal killed $itstate
}
- %r0 = tMOVr killed %r1, 14, _
- tBX_RET 14, _, implicit killed %r0
+ $r0 = tMOVr killed $r1, 14, _
+ tBX_RET 14, _, implicit killed $r0
...
---
name: test2
tracksRegLiveness: true
liveins:
- - { reg: '%r0' }
+ - { reg: '$r0' }
body: |
bb.0.entry:
- liveins: %r0
+ liveins: $r0
; Verify that the next machine instruction can be on the same line as
; '{' or '}'.
; CHECK-LABEL: name: test2
- ; CHECK: %r1 = t2MOVi 0, 14, %noreg, %noreg
- ; CHECK-NEXT: t2CMNri killed %r0, 78, 14, %noreg, implicit-def %cpsr
- ; CHECK-NEXT: BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr {
- ; CHECK-NEXT: t2IT 12, 8, implicit-def %itstate
- ; CHECK-NEXT: %r1 = t2MOVi 1, 12, killed %cpsr, %noreg, implicit internal killed %itstate
+ ; CHECK: $r1 = t2MOVi 0, 14, $noreg, $noreg
+ ; CHECK-NEXT: t2CMNri killed $r0, 78, 14, $noreg, implicit-def $cpsr
+ ; CHECK-NEXT: BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr {
+ ; CHECK-NEXT: t2IT 12, 8, implicit-def $itstate
+ ; CHECK-NEXT: $r1 = t2MOVi 1, 12, killed $cpsr, $noreg, implicit internal killed $itstate
; CHECK-NEXT: }
- ; CHECK-NEXT: %r0 = tMOVr killed %r1, 14, %noreg
- ; CHECK-NEXT: tBX_RET 14, %noreg, implicit killed %r0
- %r1 = t2MOVi 0, 14, _, _
- t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr
- BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr { t2IT 12, 8, implicit-def %itstate
- %r1 = t2MOVi 1, 12, killed %cpsr, _, internal implicit killed %itstate
- } %r0 = tMOVr killed %r1, 14, _
- tBX_RET 14, _, implicit killed %r0
+ ; CHECK-NEXT: $r0 = tMOVr killed $r1, 14, $noreg
+ ; CHECK-NEXT: tBX_RET 14, $noreg, implicit killed $r0
+ $r1 = t2MOVi 0, 14, _, _
+ t2CMNri killed $r0, 78, 14, _, implicit-def $cpsr
+ BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr { t2IT 12, 8, implicit-def $itstate
+ $r1 = t2MOVi 1, 12, killed $cpsr, _, internal implicit killed $itstate
+ } $r0 = tMOVr killed $r1, 14, _
+ tBX_RET 14, _, implicit killed $r0
...
Modified: llvm/trunk/test/CodeGen/MIR/ARM/cfi-same-value.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/ARM/cfi-same-value.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/ARM/cfi-same-value.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/ARM/cfi-same-value.mir Wed Jan 31 14:04:26 2018
@@ -23,58 +23,58 @@ frameInfo:
stack:
- { id: 0, name: mem, offset: -48, size: 40, alignment: 4 }
- { id: 1, type: spill-slot, offset: -4, size: 4, alignment: 4,
- callee-saved-register: '%lr' }
+ callee-saved-register: '$lr' }
- { id: 2, type: spill-slot, offset: -8, size: 4, alignment: 4,
- callee-saved-register: '%r11' }
+ callee-saved-register: '$r11' }
body: |
bb.0:
successors: %bb.2, %bb.1
- liveins: %r11, %lr
+ liveins: $r11, $lr
- %sp = STMDB_UPD %sp, 14, _, %r4, %r5
+ $sp = STMDB_UPD $sp, 14, _, $r4, $r5
CFI_INSTRUCTION def_cfa_offset 8
- CFI_INSTRUCTION offset %r5, -4
- CFI_INSTRUCTION offset %r4, -8
- %r5 = MOVr %sp, 14, _, _
- %r4 = MRC 15, 0, 13, 0, 3, 14, _
- %r4 = LDRi12 %r4, 4, 14, _
- CMPrr %r4, %r5, 14, _, implicit-def %cpsr
- Bcc %bb.2, 3, %cpsr
+ CFI_INSTRUCTION offset $r5, -4
+ CFI_INSTRUCTION offset $r4, -8
+ $r5 = MOVr $sp, 14, _, _
+ $r4 = MRC 15, 0, 13, 0, 3, 14, _
+ $r4 = LDRi12 $r4, 4, 14, _
+ CMPrr $r4, $r5, 14, _, implicit-def $cpsr
+ Bcc %bb.2, 3, $cpsr
bb.1:
successors: %bb.2
- liveins: %r11, %lr
+ liveins: $r11, $lr
- %r4 = MOVi 48, 14, _, _
- %r5 = MOVi 0, 14, _, _
- %sp = STMDB_UPD %sp, 14, _, %lr
+ $r4 = MOVi 48, 14, _, _
+ $r5 = MOVi 0, 14, _, _
+ $sp = STMDB_UPD $sp, 14, _, $lr
CFI_INSTRUCTION def_cfa_offset 12
- CFI_INSTRUCTION offset %lr, -12
- BL &__morestack, implicit-def %lr, implicit %sp
- %sp = LDMIA_UPD %sp, 14, _, %lr
- %sp = LDMIA_UPD %sp, 14, _, %r4, %r5
+ CFI_INSTRUCTION offset $lr, -12
+ BL &__morestack, implicit-def $lr, implicit $sp
+ $sp = LDMIA_UPD $sp, 14, _, $lr
+ $sp = LDMIA_UPD $sp, 14, _, $r4, $r5
CFI_INSTRUCTION def_cfa_offset 0
BX_RET 14, _
bb.2:
- liveins: %r11, %lr
+ liveins: $r11, $lr
- %sp = LDMIA_UPD %sp, 14, _, %r4, %r5
+ $sp = LDMIA_UPD $sp, 14, _, $r4, $r5
CFI_INSTRUCTION def_cfa_offset 0
- ; CHECK: CFI_INSTRUCTION same_value %r4
- ; CHECK-NEXT: CFI_INSTRUCTION same_value %r5
- CFI_INSTRUCTION same_value %r4
- CFI_INSTRUCTION same_value %r5
- %sp = frame-setup STMDB_UPD %sp, 14, _, killed %r11, killed %lr
+ ; CHECK: CFI_INSTRUCTION same_value $r4
+ ; CHECK-NEXT: CFI_INSTRUCTION same_value $r5
+ CFI_INSTRUCTION same_value $r4
+ CFI_INSTRUCTION same_value $r5
+ $sp = frame-setup STMDB_UPD $sp, 14, _, killed $r11, killed $lr
frame-setup CFI_INSTRUCTION def_cfa_offset 8
- frame-setup CFI_INSTRUCTION offset %lr, -4
- frame-setup CFI_INSTRUCTION offset %r11, -8
- %sp = frame-setup SUBri killed %sp, 40, 14, _, _
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r11, -8
+ $sp = frame-setup SUBri killed $sp, 40, 14, _, _
frame-setup CFI_INSTRUCTION def_cfa_offset 48
- %r0 = MOVr %sp, 14, _, _
- %r1 = MOVi 10, 14, _, _
- BL @dummy_use, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit killed %r1, implicit-def %sp
- %sp = ADDri killed %sp, 40, 14, _, _
- %sp = LDMIA_UPD %sp, 14, _, %r4, %r5
+ $r0 = MOVr $sp, 14, _, _
+ $r1 = MOVi 10, 14, _, _
+ BL @dummy_use, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit killed $r1, implicit-def $sp
+ $sp = ADDri killed $sp, 40, 14, _, _
+ $sp = LDMIA_UPD $sp, 14, _, $r4, $r5
MOVPCLR 14, _
...
Modified: llvm/trunk/test/CodeGen/MIR/ARM/expected-closing-brace.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/ARM/expected-closing-brace.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/ARM/expected-closing-brace.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/ARM/expected-closing-brace.mir Wed Jan 31 14:04:26 2018
@@ -25,26 +25,26 @@
name: test1
tracksRegLiveness: true
liveins:
- - { reg: '%r0' }
+ - { reg: '$r0' }
body: |
bb.0.entry:
successors: %bb.1.foo
- liveins: %r0
+ liveins: $r0
bb.1.foo:
successors: %bb.2.if.then, %bb.1.foo
- liveins: %r0
+ liveins: $r0
- t2CMNri %r0, 78, 14, _, implicit-def %cpsr
- %r1 = t2MOVi 0, 14, _, _
- BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr {
- t2IT 12, 8, implicit-def %itstate
- %r1 = t2MOVi 1, 12, killed %cpsr, _, implicit killed %itstate
- t2CMNri %r0, 77, 14, _, implicit-def %cpsr
- t2Bcc %bb.1.foo, 11, killed %cpsr
+ t2CMNri $r0, 78, 14, _, implicit-def $cpsr
+ $r1 = t2MOVi 0, 14, _, _
+ BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr {
+ t2IT 12, 8, implicit-def $itstate
+ $r1 = t2MOVi 1, 12, killed $cpsr, _, implicit killed $itstate
+ t2CMNri $r0, 77, 14, _, implicit-def $cpsr
+ t2Bcc %bb.1.foo, 11, killed $cpsr
; CHECK: [[@LINE+1]]:3: expected '}'
bb.2.if.then:
- liveins: %r1
+ liveins: $r1
- %r0 = tMOVr killed %r1, 14, _
- tBX_RET 14, _, implicit killed %r0
+ $r0 = tMOVr killed $r1, 14, _
+ tBX_RET 14, _, implicit killed $r0
...
Modified: llvm/trunk/test/CodeGen/MIR/ARM/extraneous-closing-brace-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/ARM/extraneous-closing-brace-error.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/ARM/extraneous-closing-brace-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/ARM/extraneous-closing-brace-error.mir Wed Jan 31 14:04:26 2018
@@ -10,11 +10,11 @@
name: test1
tracksRegLiveness: true
liveins:
- - { reg: '%r0' }
+ - { reg: '$r0' }
body: |
bb.0.entry:
- liveins: %r0
- tBX_RET 14, _, implicit killed %r0
+ liveins: $r0
+ tBX_RET 14, _, implicit killed $r0
; CHECK: [[@LINE+1]]:5: extraneous closing brace ('}')
}
...
Modified: llvm/trunk/test/CodeGen/MIR/ARM/nested-instruction-bundle-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/ARM/nested-instruction-bundle-error.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/ARM/nested-instruction-bundle-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/ARM/nested-instruction-bundle-error.mir Wed Jan 31 14:04:26 2018
@@ -12,19 +12,19 @@
name: test1
tracksRegLiveness: true
liveins:
- - { reg: '%r0' }
+ - { reg: '$r0' }
body: |
bb.0.entry:
- liveins: %r0
- %r1 = t2MOVi 0, 14, _, _
- t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr
- BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr {
- t2IT 12, 8, implicit-def %itstate
- %r1 = t2MOVi 1, 12, killed %cpsr, _
+ liveins: $r0
+ $r1 = t2MOVi 0, 14, _, _
+ t2CMNri killed $r0, 78, 14, _, implicit-def $cpsr
+ BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr {
+ t2IT 12, 8, implicit-def $itstate
+ $r1 = t2MOVi 1, 12, killed $cpsr, _
; CHECK: [[@LINE+1]]:14: nested instruction bundles are not allowed
BUNDLE {
}
}
- %r0 = tMOVr killed %r1, 14, _
- tBX_RET 14, _, implicit killed %r0
+ $r0 = tMOVr killed $r1, 14, _
+ tBX_RET 14, _, implicit killed $r0
...
Modified: llvm/trunk/test/CodeGen/MIR/Hexagon/parse-lane-masks.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Hexagon/parse-lane-masks.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/Hexagon/parse-lane-masks.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/Hexagon/parse-lane-masks.mir Wed Jan 31 14:04:26 2018
@@ -3,7 +3,7 @@
# CHECK-LABEL: name: foo
# CHECK: bb.0:
-# CHECK: liveins: %d0:0x00000002, %d1, %d2:0x00000010
+# CHECK: liveins: $d0:0x00000002, $d1, $d2:0x00000010
--- |
define void @foo() {
@@ -17,7 +17,7 @@ tracksRegLiveness: true
body: |
bb.0:
- liveins: %d0:0x00002, %d1, %d2:16
+ liveins: $d0:0x00002, $d1, $d2:16
A2_nop
...
Modified: llvm/trunk/test/CodeGen/MIR/Hexagon/target-flags.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Hexagon/target-flags.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/Hexagon/target-flags.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/Hexagon/target-flags.mir Wed Jan 31 14:04:26 2018
@@ -6,31 +6,31 @@ body: |
bb.0:
; CHECK: target-flags(hexagon-pcrel)
- %r0 = A2_tfrsi target-flags (hexagon-pcrel) 0
+ $r0 = A2_tfrsi target-flags (hexagon-pcrel) 0
; CHECK: target-flags(hexagon-got)
- %r0 = A2_tfrsi target-flags (hexagon-got) 0
+ $r0 = A2_tfrsi target-flags (hexagon-got) 0
; CHECK: target-flags(hexagon-lo16)
- %r0 = A2_tfrsi target-flags (hexagon-lo16) 0
+ $r0 = A2_tfrsi target-flags (hexagon-lo16) 0
; CHECK: target-flags(hexagon-hi16)
- %r0 = A2_tfrsi target-flags (hexagon-hi16) 0
+ $r0 = A2_tfrsi target-flags (hexagon-hi16) 0
; CHECK: target-flags(hexagon-gprel)
- %r0 = A2_tfrsi target-flags (hexagon-gprel) 0
+ $r0 = A2_tfrsi target-flags (hexagon-gprel) 0
; CHECK: target-flags(hexagon-gdgot)
- %r0 = A2_tfrsi target-flags (hexagon-gdgot) 0
+ $r0 = A2_tfrsi target-flags (hexagon-gdgot) 0
; CHECK: target-flags(hexagon-gdplt)
- %r0 = A2_tfrsi target-flags (hexagon-gdplt) 0
+ $r0 = A2_tfrsi target-flags (hexagon-gdplt) 0
; CHECK: target-flags(hexagon-ie)
- %r0 = A2_tfrsi target-flags (hexagon-ie) 0
+ $r0 = A2_tfrsi target-flags (hexagon-ie) 0
; CHECK: target-flags(hexagon-iegot)
- %r0 = A2_tfrsi target-flags (hexagon-iegot) 0
+ $r0 = A2_tfrsi target-flags (hexagon-iegot) 0
; CHECK: target-flags(hexagon-tprel)
- %r0 = A2_tfrsi target-flags (hexagon-tprel) 0
+ $r0 = A2_tfrsi target-flags (hexagon-tprel) 0
; CHECK: target-flags(hexagon-ext)
- %r0 = A2_tfrsi target-flags (hexagon-ext) 0
+ $r0 = A2_tfrsi target-flags (hexagon-ext) 0
; CHECK: target-flags(hexagon-pcrel, hexagon-ext)
- %r0 = A2_tfrsi target-flags (hexagon-pcrel,hexagon-ext) 0
+ $r0 = A2_tfrsi target-flags (hexagon-pcrel,hexagon-ext) 0
; CHECK: target-flags(hexagon-ie, hexagon-ext)
- %r0 = A2_tfrsi target-flags (hexagon-ie,hexagon-ext) 0
+ $r0 = A2_tfrsi target-flags (hexagon-ie,hexagon-ext) 0
...
Modified: llvm/trunk/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir Wed Jan 31 14:04:26 2018
@@ -12,7 +12,7 @@
name: test
tracksRegLiveness: true
liveins:
- - { reg: '%a0' }
+ - { reg: '$a0' }
frameInfo:
stackSize: 24
maxAlignment: 4
@@ -21,21 +21,21 @@ frameInfo:
maxCallFrameSize: 16
stack:
- { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4,
- callee-saved-register: '%ra' }
+ callee-saved-register: '$ra' }
body: |
bb.0.entry:
- liveins: %a0, %ra
+ liveins: $a0, $ra
- Save16 %ra, 24, implicit-def %sp, implicit %sp
- %v0, %v1 = GotPrologue16 &_gp_disp, &_gp_disp
- %v0 = SllX16 killed %v0, 16
- %v0 = AdduRxRyRz16 killed %v1, killed %v0
+ Save16 $ra, 24, implicit-def $sp, implicit $sp
+ $v0, $v1 = GotPrologue16 &_gp_disp, &_gp_disp
+ $v0 = SllX16 killed $v0, 16
+ $v0 = AdduRxRyRz16 killed $v1, killed $v0
; CHECK: [[@LINE+1]]:67: expected a global value or an external symbol after 'call-entry'
- %v1 = LwRxRyOffMemX16 %v0, @foo, 0 :: (load 4 from call-entry foo)
- %t9 = COPY %v1
- %gp = COPY killed %v0
- JumpLinkReg16 killed %v1, csr_o32, implicit-def %ra, implicit killed %t9, implicit %a0, implicit killed %gp, implicit-def %sp, implicit-def dead %v0
- %v0 = LiRxImmX16 0
- %ra = Restore16 24, implicit-def %sp, implicit %sp
- RetRA16 implicit %v0
+ $v1 = LwRxRyOffMemX16 $v0, @foo, 0 :: (load 4 from call-entry foo)
+ $t9 = COPY $v1
+ $gp = COPY killed $v0
+ JumpLinkReg16 killed $v1, csr_o32, implicit-def $ra, implicit killed $t9, implicit $a0, implicit killed $gp, implicit-def $sp, implicit-def dead $v0
+ $v0 = LiRxImmX16 0
+ $ra = Restore16 24, implicit-def $sp, implicit $sp
+ RetRA16 implicit $v0
...
Modified: llvm/trunk/test/CodeGen/MIR/Mips/memory-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Mips/memory-operands.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/Mips/memory-operands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/Mips/memory-operands.mir Wed Jan 31 14:04:26 2018
@@ -29,7 +29,7 @@
name: test
tracksRegLiveness: true
liveins:
- - { reg: '%a0' }
+ - { reg: '$a0' }
frameInfo:
stackSize: 24
maxAlignment: 4
@@ -38,26 +38,26 @@ frameInfo:
maxCallFrameSize: 16
stack:
- { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4,
- callee-saved-register: '%ra' }
+ callee-saved-register: '$ra' }
body: |
bb.0.entry:
- liveins: %a0, %ra
+ liveins: $a0, $ra
- Save16 %ra, 24, implicit-def %sp, implicit %sp
+ Save16 $ra, 24, implicit-def $sp, implicit $sp
CFI_INSTRUCTION def_cfa_offset 24
- CFI_INSTRUCTION offset %ra_64, -4
- %v0, %v1 = GotPrologue16 &_gp_disp, &_gp_disp
- %v0 = SllX16 killed %v0, 16
- %v0 = AdduRxRyRz16 killed %v1, killed %v0
+ CFI_INSTRUCTION offset $ra_64, -4
+ $v0, $v1 = GotPrologue16 &_gp_disp, &_gp_disp
+ $v0 = SllX16 killed $v0, 16
+ $v0 = AdduRxRyRz16 killed $v1, killed $v0
; CHECK-LABEL: name: test
- ; CHECK: %v1 = LwRxRyOffMemX16 %v0, @foo :: (load 4 from call-entry @foo)
- %v1 = LwRxRyOffMemX16 %v0, @foo :: (load 4 from call-entry @foo)
- %t9 = COPY %v1
- %gp = COPY killed %v0
- JumpLinkReg16 killed %v1, csr_o32, implicit-def %ra, implicit killed %t9, implicit %a0, implicit killed %gp, implicit-def %sp, implicit-def dead %v0
- %v0 = LiRxImmX16 0
- %ra = Restore16 24, implicit-def %sp, implicit %sp
- RetRA16 implicit %v0
+ ; CHECK: $v1 = LwRxRyOffMemX16 $v0, @foo :: (load 4 from call-entry @foo)
+ $v1 = LwRxRyOffMemX16 $v0, @foo :: (load 4 from call-entry @foo)
+ $t9 = COPY $v1
+ $gp = COPY killed $v0
+ JumpLinkReg16 killed $v1, csr_o32, implicit-def $ra, implicit killed $t9, implicit $a0, implicit killed $gp, implicit-def $sp, implicit-def dead $v0
+ $v0 = LiRxImmX16 0
+ $ra = Restore16 24, implicit-def $sp, implicit $sp
+ RetRA16 implicit $v0
...
---
name: test2
@@ -70,33 +70,33 @@ frameInfo:
maxCallFrameSize: 16
stack:
- { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4,
- callee-saved-register: '%ra' }
+ callee-saved-register: '$ra' }
- { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4,
- callee-saved-register: '%s2' }
+ callee-saved-register: '$s2' }
- { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4,
- callee-saved-register: '%s0' }
+ callee-saved-register: '$s0' }
body: |
bb.0.entry:
- liveins: %ra, %s2, %s0, %ra, %s2, %s0
+ liveins: $ra, $s2, $s0, $ra, $s2, $s0
- SaveX16 %s0, %ra, %s2, 32, implicit-def %sp, implicit %sp
+ SaveX16 $s0, $ra, $s2, 32, implicit-def $sp, implicit $sp
CFI_INSTRUCTION def_cfa_offset 32
- CFI_INSTRUCTION offset %ra_64, -4
- CFI_INSTRUCTION offset %s2_64, -8
- CFI_INSTRUCTION offset %s0_64, -12
- %v0, %v1 = GotPrologue16 &_gp_disp, &_gp_disp
- %v0 = SllX16 killed %v0, 16
- %s0 = AdduRxRyRz16 killed %v1, killed %v0
- %v0 = LwRxRyOffMemX16 %s0, @g :: (load 4 from call-entry @g)
+ CFI_INSTRUCTION offset $ra_64, -4
+ CFI_INSTRUCTION offset $s2_64, -8
+ CFI_INSTRUCTION offset $s0_64, -12
+ $v0, $v1 = GotPrologue16 &_gp_disp, &_gp_disp
+ $v0 = SllX16 killed $v0, 16
+ $s0 = AdduRxRyRz16 killed $v1, killed $v0
+ $v0 = LwRxRyOffMemX16 $s0, @g :: (load 4 from call-entry @g)
; CHECK-LABEL: test2
- ; CHECK: %v1 = LwRxRyOffMemX16 %s0, &__mips16_call_stub_sf_0 :: (load 4 from call-entry &__mips16_call_stub_sf_0)
- %v1 = LwRxRyOffMemX16 %s0, &__mips16_call_stub_sf_0 :: (load 4 from call-entry &__mips16_call_stub_sf_0)
- %gp = COPY %s0
- JumpLinkReg16 killed %v1, csr_o32, implicit-def %ra, implicit %v0, implicit killed %gp, implicit-def %sp, implicit-def %v0
- %v1 = LwRxRyOffMemX16 %s0, @__mips16_ret_sf :: (load 4 from call-entry @__mips16_ret_sf)
- %t9 = COPY %v1
- %gp = COPY killed %s0
- JumpLinkReg16 killed %v1, csr_mips16rethelper, implicit-def %ra, implicit killed %t9, implicit %v0, implicit killed %gp, implicit-def %sp
- %s0, %ra, %s2 = RestoreX16 32, implicit-def %sp, implicit %sp
- RetRA16 implicit %v0
+ ; CHECK: $v1 = LwRxRyOffMemX16 $s0, &__mips16_call_stub_sf_0 :: (load 4 from call-entry &__mips16_call_stub_sf_0)
+ $v1 = LwRxRyOffMemX16 $s0, &__mips16_call_stub_sf_0 :: (load 4 from call-entry &__mips16_call_stub_sf_0)
+ $gp = COPY $s0
+ JumpLinkReg16 killed $v1, csr_o32, implicit-def $ra, implicit $v0, implicit killed $gp, implicit-def $sp, implicit-def $v0
+ $v1 = LwRxRyOffMemX16 $s0, @__mips16_ret_sf :: (load 4 from call-entry @__mips16_ret_sf)
+ $t9 = COPY $v1
+ $gp = COPY killed $s0
+ JumpLinkReg16 killed $v1, csr_mips16rethelper, implicit-def $ra, implicit killed $t9, implicit $v0, implicit killed $gp, implicit-def $sp
+ $s0, $ra, $s2 = RestoreX16 32, implicit-def $sp, implicit $sp
+ RetRA16 implicit $v0
...
Modified: llvm/trunk/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir Wed Jan 31 14:04:26 2018
@@ -28,17 +28,17 @@ registers:
- { id: 3, class: gprc }
- { id: 4, class: g8rc }
liveins:
- - { reg: '%x3', virtual-reg: '%0' }
+ - { reg: '$x3', virtual-reg: '%0' }
body: |
bb.0.entry:
- liveins: %x3
+ liveins: $x3
- %0 = COPY %x3
+ %0 = COPY $x3
%1 = LWZ 0, %0 :: (load 4 from %ir.p)
%2 = LI 0
%3 = RLWIMI %2, killed %1, 0, 0, 31
%4 = EXTSW_32_64 killed %3
- %x3 = COPY %4
- ; CHECK: BLR8 implicit %lr8, implicit %rm, implicit %x3
- BLR8 implicit %lr8, implicit %rm, implicit %x3
+ $x3 = COPY %4
+ ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3
+ BLR8 implicit $lr8, implicit $rm, implicit $x3
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/auto-successor.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/auto-successor.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/auto-successor.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/auto-successor.mir Wed Jan 31 14:04:26 2018
@@ -4,31 +4,31 @@
# CHECK-LABEL: name: func0
# CHECK: bb.0:
# CHECK-NOT: successors
-# CHECK: JE_1 %bb.1, implicit undef %eflags
+# CHECK: JE_1 %bb.1, implicit undef $eflags
# CHECK: JMP_1 %bb.3
# CHECK: bb.1:
# CHECK-NOT: successors
# CHECK: bb.2:
# CHECK-NOT: successors
-# CHECK: JE_1 %bb.1, implicit undef %eflags
+# CHECK: JE_1 %bb.1, implicit undef $eflags
# CHECK: bb.3:
-# CHECK: RETQ undef %eax
+# CHECK: RETQ undef $eax
name: func0
body: |
bb.0:
- JE_1 %bb.1, implicit undef %eflags
+ JE_1 %bb.1, implicit undef $eflags
JMP_1 %bb.3
bb.1:
bb.2:
- JE_1 %bb.1, implicit undef %eflags
+ JE_1 %bb.1, implicit undef $eflags
bb.3:
- JE_1 %bb.4, implicit undef %eflags ; condjump+fallthrough to same block
+ JE_1 %bb.4, implicit undef $eflags ; condjump+fallthrough to same block
bb.4:
- RETQ undef %eax
+ RETQ undef $eax
...
---
# Some cases that need explicit successors:
@@ -39,23 +39,23 @@ body: |
; CHECK: bb.0:
; CHECK: successors: %bb.3, %bb.1
successors: %bb.3, %bb.1 ; different order than operands
- JE_1 %bb.1, implicit undef %eflags
+ JE_1 %bb.1, implicit undef $eflags
JMP_1 %bb.3
bb.1:
; CHECK: bb.1:
; CHECK: successors: %bb.2, %bb.1
successors: %bb.2, %bb.1 ; different order (fallthrough variant)
- JE_1 %bb.1, implicit undef %eflags
+ JE_1 %bb.1, implicit undef $eflags
bb.2:
; CHECK: bb.2:
; CHECK: successors: %bb.1(0x60000000), %bb.3(0x20000000)
successors: %bb.1(3), %bb.3(1) ; branch probabilities not normalized
- JE_1 %bb.1, implicit undef %eflags
+ JE_1 %bb.1, implicit undef $eflags
bb.3:
; CHECK: bb.3:
- ; CHECK: RETQ undef %eax
- RETQ undef %eax
+ ; CHECK: RETQ undef $eax
+ RETQ undef $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/basic-block-liveins.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/basic-block-liveins.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/basic-block-liveins.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/basic-block-liveins.mir Wed Jan 31 14:04:26 2018
@@ -26,12 +26,12 @@ name: test
tracksRegLiveness: true
body: |
; CHECK-LABEL: bb.0.body:
- ; CHECK-NEXT: liveins: %edi, %esi
+ ; CHECK-NEXT: liveins: $edi, $esi
bb.0.body:
- liveins: %edi, %esi
+ liveins: $edi, $esi
- %eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _
- RETQ %eax
+ $eax = LEA64_32r killed $rdi, 1, killed $rsi, 0, _
+ RETQ $eax
...
---
name: test2
@@ -41,13 +41,13 @@ body: |
; Verify that we can have multiple lists of liveins that will be merged into
; one.
; CHECK: bb.0.body:
- ; CHECK-NEXT: liveins: %edi, %esi
+ ; CHECK-NEXT: liveins: $edi, $esi
bb.0.body:
- liveins: %edi
- liveins: %esi
+ liveins: $edi
+ liveins: $esi
- %eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _
- RETQ %eax
+ $eax = LEA64_32r killed $rdi, 1, killed $rsi, 0, _
+ RETQ $eax
...
---
name: test3
@@ -56,10 +56,10 @@ body: |
; Verify that we can have an empty list of liveins.
; CHECK-LABEL: name: test3
; CHECK: bb.0.body:
- ; CHECK-NEXT: %eax = MOV32r0 implicit-def dead %eflags
+ ; CHECK-NEXT: $eax = MOV32r0 implicit-def dead $eflags
bb.0.body:
liveins:
- %eax = MOV32r0 implicit-def dead %eflags
- RETQ killed %eax
+ $eax = MOV32r0 implicit-def dead $eflags
+ RETQ killed $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir Wed Jan 31 14:04:26 2018
@@ -19,23 +19,23 @@
name: foo
tracksRegLiveness: true
liveins:
- - { reg: '%edi' }
+ - { reg: '$edi' }
body: |
bb.0.entry:
successors: %bb.1.less, %bb.2.exit
- liveins: %edi 44
+ liveins: $edi 44
- CMP32ri8 %edi, 10, implicit-def %eflags
- JG_1 %bb.2.exit, implicit killed %eflags
+ CMP32ri8 $edi, 10, implicit-def $eflags
+ JG_1 %bb.2.exit, implicit killed $eflags
; CHECK: [[@LINE+1]]:8: basic block definition should be located at the start of the line
less bb.1:
- %eax = MOV32r0 implicit-def dead %eflags
- RETQ killed %eax
+ $eax = MOV32r0 implicit-def dead $eflags
+ RETQ killed $eax
bb.2.exit:
- liveins: %edi
+ liveins: $edi
- %eax = COPY killed %edi
- RETQ killed %eax
+ $eax = COPY killed $edi
+ RETQ killed $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/block-address-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/block-address-operands.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/block-address-operands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/block-address-operands.mir Wed Jan 31 14:04:26 2018
@@ -57,10 +57,10 @@ name: test
body: |
bb.0.entry:
successors: %bb.1.block
- ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test, %ir-block.block), %noreg
- %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _
- MOV64mr %rip, 1, _, @addr, _, killed %rax
- JMP64m %rip, 1, _, @addr, _
+ ; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test, %ir-block.block), $noreg
+ $rax = LEA64r $rip, 1, _, blockaddress(@test, %ir-block.block), _
+ MOV64mr $rip, 1, _, @addr, _, killed $rax
+ JMP64m $rip, 1, _, @addr, _
bb.1.block (address-taken):
RETQ
@@ -71,10 +71,10 @@ tracksRegLiveness: true
body: |
bb.0.entry:
successors: %bb.1
- ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test2, %ir-block."quoted block"), %noreg
- %rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _
- MOV64mr %rip, 1, _, @addr, _, killed %rax
- JMP64m %rip, 1, _, @addr, _
+ ; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test2, %ir-block."quoted block"), $noreg
+ $rax = LEA64r $rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _
+ MOV64mr $rip, 1, _, @addr, _, killed $rax
+ JMP64m $rip, 1, _, @addr, _
bb.1 (address-taken):
RETQ
@@ -84,11 +84,11 @@ name: slot_in_other_function
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: %rdi
+ liveins: $rdi
; CHECK-LABEL: name: slot_in_other_function
- ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test3, %ir-block.0), %noreg
- %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
- MOV64mr killed %rdi, 1, _, 0, _, killed %rax
+ ; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test3, %ir-block.0), $noreg
+ $rax = LEA64r $rip, 1, _, blockaddress(@test3, %ir-block.0), _
+ MOV64mr killed $rdi, 1, _, 0, _, killed $rax
RETQ
...
---
@@ -98,10 +98,10 @@ body: |
bb.0.entry:
successors: %bb.1
; CHECK-LABEL: name: test3
- ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test3, %ir-block.0), %noreg
- %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
- MOV64mr %rip, 1, _, @addr, _, killed %rax
- JMP64m %rip, 1, _, @addr, _
+ ; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test3, %ir-block.0), $noreg
+ $rax = LEA64r $rip, 1, _, blockaddress(@test3, %ir-block.0), _
+ MOV64mr $rip, 1, _, @addr, _, killed $rax
+ JMP64m $rip, 1, _, @addr, _
bb.1 (address-taken):
RETQ
@@ -111,10 +111,10 @@ name: test4
body: |
bb.0.entry:
successors: %bb.1.block
- ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test, %ir-block.block) + 2, %noreg
- %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _
- MOV64mr %rip, 1, _, @addr, _, killed %rax
- JMP64m %rip, 1, _, @addr, _
+ ; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test, %ir-block.block) + 2, $noreg
+ $rax = LEA64r $rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _
+ MOV64mr $rip, 1, _, @addr, _, killed $rax
+ JMP64m $rip, 1, _, @addr, _
bb.1.block (address-taken):
RETQ
Modified: llvm/trunk/test/CodeGen/MIR/X86/branch-probabilities.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/branch-probabilities.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/branch-probabilities.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/branch-probabilities.mir Wed Jan 31 14:04:26 2018
@@ -8,11 +8,11 @@ name: test
body: |
bb.0:
successors: %bb.1(4), %bb.2(1)
- JE_1 %bb.2, implicit undef %eflags
+ JE_1 %bb.2, implicit undef $eflags
bb.1:
NOOP
bb.2:
- RETQ undef %eax
+ RETQ undef $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir Wed Jan 31 14:04:26 2018
@@ -36,10 +36,10 @@ name: compute
tracksRegLiveness: true
body: |
bb.0.body:
- liveins: %edi
+ liveins: $edi
- %eax = COPY killed %edi
- RETQ killed %eax
+ $eax = COPY killed $edi
+ RETQ killed $eax
...
---
name: func
@@ -50,47 +50,47 @@ frameInfo:
adjustsStack: true
hasCalls: true
# CHECK: fixedStack:
-# CHECK: callee-saved-register: '%rbx', callee-saved-restored: true }
+# CHECK: callee-saved-register: '$rbx', callee-saved-restored: true }
fixedStack:
- - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%rbx' }
+ - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '$rbx' }
# CHECK: stack:
# CHECK-NEXT: - { id: 0
-# CHECK: callee-saved-register: '%edi', callee-saved-restored: false
+# CHECK: callee-saved-register: '$edi', callee-saved-restored: false
stack:
- { id: 0, name: b, offset: -20, size: 4, alignment: 4 }
- - { id: 1, offset: -24, size: 4, alignment: 4, callee-saved-register: '%edi',
+ - { id: 1, offset: -24, size: 4, alignment: 4, callee-saved-register: '$edi',
callee-saved-restored: false }
body: |
bb.0.entry:
successors: %bb.1.check
- liveins: %edi, %rbx
+ liveins: $edi, $rbx
- frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
- %rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags
- %ebx = COPY %edi
- MOV32mr %rsp, 1, _, 12, _, %ebx
+ frame-setup PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp
+ $rsp = frame-setup SUB64ri8 $rsp, 16, implicit-def dead $eflags
+ $ebx = COPY $edi
+ MOV32mr $rsp, 1, _, 12, _, $ebx
bb.1.check:
successors: %bb.2.loop, %bb.3.exit
- liveins: %ebx
+ liveins: $ebx
- CMP32ri8 %ebx, 10, implicit-def %eflags
- JG_1 %bb.3.exit, implicit killed %eflags
+ CMP32ri8 $ebx, 10, implicit-def $eflags
+ JG_1 %bb.3.exit, implicit killed $eflags
JMP_1 %bb.2.loop
bb.2.loop:
successors: %bb.1.check
- liveins: %ebx
+ liveins: $ebx
- %edi = MOV32rm %rsp, 1, _, 12, _
- CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
- %eax = DEC32r killed %eax, implicit-def dead %eflags
- MOV32mr %rsp, 1, _, 12, _, killed %eax
+ $edi = MOV32rm $rsp, 1, _, 12, _
+ CALL64pcrel32 @compute, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax
+ $eax = DEC32r killed $eax, implicit-def dead $eflags
+ MOV32mr $rsp, 1, _, 12, _, killed $eax
JMP_1 %bb.1.check
bb.3.exit:
- %eax = MOV32r0 implicit-def dead %eflags
- %rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags
- %rbx = POP64r implicit-def %rsp, implicit %rsp
- RETQ %eax
+ $eax = MOV32r0 implicit-def dead $eflags
+ $rsp = ADD64ri8 $rsp, 16, implicit-def dead $eflags
+ $rbx = POP64r implicit-def $rsp, implicit $rsp
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir Wed Jan 31 14:04:26 2018
@@ -20,10 +20,10 @@ stack:
- { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 }
body: |
bb.0.entry:
- %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags
+ $rsp = SUB64ri32 $rsp, 4040, implicit-def dead $eflags
; CHECK: CFI_INSTRUCTION def_cfa_offset 4048
CFI_INSTRUCTION def_cfa_offset 4048
- %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags
+ $rsp = ADD64ri32 $rsp, 4040, implicit-def dead $eflags
RETQ
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir Wed Jan 31 14:04:26 2018
@@ -21,12 +21,12 @@ fixedStack:
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
body: |
bb.0.entry:
- liveins: %rbp
+ liveins: $rbp
- PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp
+ PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 16
- CFI_INSTRUCTION offset %rbp, -16
- %rbp = MOV64rr %rsp
- ; CHECK: CFI_INSTRUCTION def_cfa_register %rbp
- CFI_INSTRUCTION def_cfa_register %rbp
+ CFI_INSTRUCTION offset $rbp, -16
+ $rbp = MOV64rr $rsp
+ ; CHECK: CFI_INSTRUCTION def_cfa_register $rbp
+ CFI_INSTRUCTION def_cfa_register $rbp
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/cfi-offset.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/cfi-offset.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/cfi-offset.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/cfi-offset.mir Wed Jan 31 14:04:26 2018
@@ -28,20 +28,20 @@ fixedStack:
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
body: |
bb.0.entry:
- liveins: %ecx, %edi, %edx, %esi, %rbx
+ liveins: $ecx, $edi, $edx, $esi, $rbx
- PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
+ PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 16
- ; CHECK: CFI_INSTRUCTION offset %rbx, -16
- CFI_INSTRUCTION offset %rbx, -16
- %ebx = COPY %edi, implicit-def %rbx
- %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags
- %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags
- %ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags
- %edi = COPY %ebx
- CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp
- %eax = LEA64_32r killed %rbx, 1, %rbx, 0, _
- %rbx = POP64r implicit-def %rsp, implicit %rsp
- RETQ %eax
+ ; CHECK: CFI_INSTRUCTION offset $rbx, -16
+ CFI_INSTRUCTION offset $rbx, -16
+ $ebx = COPY $edi, implicit-def $rbx
+ $ebx = ADD32rr $ebx, killed $esi, implicit-def dead $eflags
+ $ebx = ADD32rr $ebx, killed $edx, implicit-def dead $eflags
+ $ebx = ADD32rr $ebx, killed $ecx, implicit-def dead $eflags
+ $edi = COPY $ebx
+ CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp
+ $eax = LEA64_32r killed $rbx, 1, $rbx, 0, _
+ $rbx = POP64r implicit-def $rsp, implicit $rsp
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/constant-pool.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/constant-pool.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/constant-pool.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/constant-pool.mir Wed Jan 31 14:04:26 2018
@@ -61,13 +61,13 @@ constants:
alignment: 4
body: |
bb.0.entry:
- ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.0, %noreg
- ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, %noreg, %const.1, %noreg
- %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
- %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
- %xmm1 = CVTSS2SDrr killed %xmm1
- %xmm0 = MULSDrr killed %xmm0, killed %xmm1
- RETQ %xmm0
+ ; CHECK: $xmm0 = ADDSDrm killed $xmm0, $rip, 1, $noreg, %const.0, $noreg
+ ; CHECK-NEXT: $xmm1 = ADDSSrm killed $xmm1, $rip, 1, $noreg, %const.1, $noreg
+ $xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.0, _
+ $xmm1 = ADDSSrm killed $xmm1, $rip, 1, _, %const.1, _
+ $xmm1 = CVTSS2SDrr killed $xmm1
+ $xmm0 = MULSDrr killed $xmm0, killed $xmm1
+ RETQ $xmm0
...
---
# Verify that alignment can be inferred:
@@ -89,11 +89,11 @@ constants:
value: 'float 6.250000e+00'
body: |
bb.0.entry:
- %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
- %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
- %xmm1 = CVTSS2SDrr killed %xmm1
- %xmm0 = MULSDrr killed %xmm0, killed %xmm1
- RETQ %xmm0
+ $xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.0, _
+ $xmm1 = ADDSSrm killed $xmm1, $rip, 1, _, %const.1, _
+ $xmm1 = CVTSS2SDrr killed $xmm1
+ $xmm0 = MULSDrr killed $xmm0, killed $xmm1
+ RETQ $xmm0
...
---
# Verify that the non-standard alignments are respected:
@@ -117,13 +117,13 @@ constants:
alignment: 1
body: |
bb.0.entry:
- ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.0, %noreg
- ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, %noreg, %const.1, %noreg
- %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
- %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
- %xmm1 = CVTSS2SDrr killed %xmm1
- %xmm0 = MULSDrr killed %xmm0, killed %xmm1
- RETQ %xmm0
+ ; CHECK: $xmm0 = ADDSDrm killed $xmm0, $rip, 1, $noreg, %const.0, $noreg
+ ; CHECK-NEXT: $xmm1 = ADDSSrm killed $xmm1, $rip, 1, $noreg, %const.1, $noreg
+ $xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.0, _
+ $xmm1 = ADDSSrm killed $xmm1, $rip, 1, _, %const.1, _
+ $xmm1 = CVTSS2SDrr killed $xmm1
+ $xmm0 = MULSDrr killed $xmm0, killed $xmm1
+ RETQ $xmm0
...
---
# CHECK: name: test4
@@ -135,11 +135,11 @@ constants:
value: 'float 6.250000e+00'
body: |
bb.0.entry:
- ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.1 - 12, %noreg
- ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, %noreg, %const.0 + 8, %noreg
- %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _
- %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _
- %xmm1 = CVTSS2SDrr killed %xmm1
- %xmm0 = MULSDrr killed %xmm0, killed %xmm1
- RETQ %xmm0
+ ; CHECK: $xmm0 = ADDSDrm killed $xmm0, $rip, 1, $noreg, %const.1 - 12, $noreg
+ ; CHECK-NEXT: $xmm1 = ADDSSrm killed $xmm1, $rip, 1, $noreg, %const.0 + 8, $noreg
+ $xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.1 - 12, _
+ $xmm1 = ADDSSrm killed $xmm1, $rip, 1, _, %const.0 + 8, _
+ $xmm1 = CVTSS2SDrr killed $xmm1
+ $xmm0 = MULSDrr killed $xmm0, killed $xmm1
+ RETQ $xmm0
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/dead-register-flag.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/dead-register-flag.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/dead-register-flag.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/dead-register-flag.mir Wed Jan 31 14:04:26 2018
@@ -18,7 +18,7 @@ name: foo
body: |
; CHECK: bb.0.body:
bb.0.body:
- ; CHECK: %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags
- %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags
- RETQ %eax
+ ; CHECK: $eax = IMUL32rri8 $edi, 11, implicit-def dead $eflags
+ $eax = IMUL32rri8 $edi, 11, implicit-def dead $eflags
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/def-register-already-tied-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/def-register-already-tied-error.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/def-register-already-tied-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/def-register-already-tied-error.mir Wed Jan 31 14:04:26 2018
@@ -12,13 +12,13 @@
name: test
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry:
- liveins: %rdi
+ liveins: $rdi
; CHECK: [[@LINE+1]]:83: the tied-def operand #3 is already tied with another register operand
- INLINEASM &"$foo", 1, 2818058, def %rdi, 2147483657, killed %rdi(tied-def 3), killed %rdi(tied-def 3)
- %rax = COPY killed %rdi
- RETQ killed %rax
+ INLINEASM &"$foo", 1, 2818058, def $rdi, 2147483657, killed $rdi(tied-def 3), killed $rdi(tied-def 3)
+ $rax = COPY killed $rdi
+ RETQ killed $rax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/diexpr-win32.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/diexpr-win32.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/diexpr-win32.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/diexpr-win32.mir Wed Jan 31 14:04:26 2018
@@ -179,7 +179,7 @@ frameInfo:
restorePoint: ''
fixedStack:
- { id: 0, type: spill-slot, offset: -8, size: 4, alignment: 4, stack-id: 0,
- callee-saved-register: '%esi' }
+ callee-saved-register: '$esi' }
- { id: 1, type: default, offset: 4, size: 4, alignment: 4, stack-id: 0,
isImmutable: true, isAliased: false, callee-saved-register: '' }
- { id: 2, type: default, offset: 0, size: 4, alignment: 4, stack-id: 0,
@@ -188,24 +188,24 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %esi
+ liveins: $esi
- frame-setup PUSH32r killed %esi, implicit-def %esp, implicit %esp
+ frame-setup PUSH32r killed $esi, implicit-def $esp, implicit $esp
CFI_INSTRUCTION def_cfa_offset 8
- CFI_INSTRUCTION offset %esi, -8
- %esi = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.2)
- DBG_VALUE %esp, 0, !26, !10, debug-location !25
- DBG_VALUE %esp, 0, !23, !DIExpression(DW_OP_plus_uconst, 8, DW_OP_deref), debug-location !25
- CALLpcrel32 @getString, csr_32, implicit %esp, implicit-def %esp, implicit-def %eax, debug-location !29
- %ecx = MOV32rm %eax, 1, _, 0, _, debug-location !29 :: (dereferenceable load 4 from %ir.1)
- %edx = MOV32rm %eax, 1, _, 4, _, debug-location !29 :: (dereferenceable load 4 from %ir.1 + 4)
- MOV32mr %esi, 1, _, 0, _, killed %ecx, debug-location !29 :: (store 4 into %ir.0)
- MOV32mr %esi, 1, _, 4, _, killed %edx, debug-location !29 :: (store 4 into %ir.0 + 4)
- %eax = MOV32rm killed %eax, 1, _, 8, _, debug-location !29 :: (dereferenceable load 4 from %ir.1 + 8)
- MOV32mr %esi, 1, _, 8, _, killed %eax, debug-location !29 :: (store 4 into %ir.0 + 8)
- %eax = COPY killed %esi, debug-location !30
- %esi = POP32r implicit-def %esp, implicit %esp, debug-location !30
- RET 0, %eax, debug-location !30
+ CFI_INSTRUCTION offset $esi, -8
+ $esi = MOV32rm $esp, 1, _, 8, _ :: (load 4 from %fixed-stack.2)
+ DBG_VALUE $esp, 0, !26, !10, debug-location !25
+ DBG_VALUE $esp, 0, !23, !DIExpression(DW_OP_plus_uconst, 8, DW_OP_deref), debug-location !25
+ CALLpcrel32 @getString, csr_32, implicit $esp, implicit-def $esp, implicit-def $eax, debug-location !29
+ $ecx = MOV32rm $eax, 1, _, 0, _, debug-location !29 :: (dereferenceable load 4 from %ir.1)
+ $edx = MOV32rm $eax, 1, _, 4, _, debug-location !29 :: (dereferenceable load 4 from %ir.1 + 4)
+ MOV32mr $esi, 1, _, 0, _, killed $ecx, debug-location !29 :: (store 4 into %ir.0)
+ MOV32mr $esi, 1, _, 4, _, killed $edx, debug-location !29 :: (store 4 into %ir.0 + 4)
+ $eax = MOV32rm killed $eax, 1, _, 8, _, debug-location !29 :: (dereferenceable load 4 from %ir.1 + 8)
+ MOV32mr $esi, 1, _, 8, _, killed $eax, debug-location !29 :: (store 4 into %ir.0 + 8)
+ $eax = COPY killed $esi, debug-location !30
+ $esi = POP32r implicit-def $esp, implicit $esp, debug-location !30
+ RET 0, $eax, debug-location !30
...
---
@@ -244,10 +244,10 @@ stack:
constants:
body: |
bb.0.entry:
- %eax = MOV32rm %esp, 1, _, 4, _ :: (load 4 from %fixed-stack.1)
- %eax = MOV32rm killed %eax, 1, _, 0, _, debug-location !34 :: (load 4 from %ir.0)
- DBG_VALUE debug-use %eax, 0, !35, !DIExpression(DW_OP_constu, 4, DW_OP_minus), debug-location !34
- %eax = ADD32rm killed %eax, %esp, 1, _, 8, _, implicit-def dead %eflags, debug-location !36 :: (load 4 from %fixed-stack.0)
- RET 0, %eax, debug-location !36
+ $eax = MOV32rm $esp, 1, _, 4, _ :: (load 4 from %fixed-stack.1)
+ $eax = MOV32rm killed $eax, 1, _, 0, _, debug-location !34 :: (load 4 from %ir.0)
+ DBG_VALUE debug-use $eax, 0, !35, !DIExpression(DW_OP_constu, 4, DW_OP_minus), debug-location !34
+ $eax = ADD32rm killed $eax, $esp, 1, _, 8, _, implicit-def dead $eflags, debug-location !36 :: (load 4 from %fixed-stack.0)
+ RET 0, $eax, debug-location !36
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir Wed Jan 31 14:04:26 2018
@@ -15,13 +15,13 @@
name: volatile_inc
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry:
- liveins: %rdi
+ liveins: $rdi
; CHECK: [[@LINE+1]]:50: duplicate 'volatile' memory operand flag
- %eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile volatile load 4 from %ir.x)
- %eax = INC32r killed %eax, implicit-def dead %eflags
- MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x)
- RETQ %eax
+ $eax = MOV32rm $rdi, 1, _, 0, _ :: (volatile volatile load 4 from %ir.x)
+ $eax = INC32r killed $eax, implicit-def dead $eflags
+ MOV32mr killed $rdi, 1, _, 0, _, $eax :: (volatile store 4 into %ir.x)
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir Wed Jan 31 14:04:26 2018
@@ -21,15 +21,15 @@ body: |
bb.0.entry:
successors: %bb.1.less, %bb.2.exit
- CMP32ri8 %edi, 10, implicit-def %eflags
+ CMP32ri8 $edi, 10, implicit-def $eflags
; CHECK: [[@LINE+1]]:31: duplicate 'implicit' register flag
- JG_1 %bb.2.exit, implicit implicit %eflags
+ JG_1 %bb.2.exit, implicit implicit $eflags
bb.1.less:
- %eax = MOV32r0 implicit-def %eflags
- RETQ %eax
+ $eax = MOV32r0 implicit-def $eflags
+ RETQ $eax
bb.2.exit:
- %eax = COPY %edi
- RETQ %eax
+ $eax = COPY $edi
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/early-clobber-register-flag.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/early-clobber-register-flag.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/early-clobber-register-flag.mir Wed Jan 31 14:04:26 2018
@@ -21,24 +21,24 @@
name: test
tracksRegLiveness: true
liveins:
- - { reg: '%edi' }
- - { reg: '%esi' }
+ - { reg: '$edi' }
+ - { reg: '$esi' }
frameInfo:
stackSize: 8
adjustsStack: true
hasCalls: true
body: |
bb.0.entry:
- liveins: %edi, %esi
+ liveins: $edi, $esi
- frame-setup PUSH64r undef %rax, implicit-def %rsp, implicit %rsp
+ frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 16
- %ecx = COPY %edi
- %ecx = ADD32rr killed %ecx, killed %esi, implicit-def dead %eflags
- ; CHECK: INLINEASM &nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di
- INLINEASM &nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di
- %edi = COPY killed %ecx
- CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp
- %rax = POP64r implicit-def %rsp, implicit %rsp
+ $ecx = COPY $edi
+ $ecx = ADD32rr killed $ecx, killed $esi, implicit-def dead $eflags
+ ; CHECK: INLINEASM &nop, 1, 12, implicit-def dead early-clobber $ax, 12, implicit-def dead early-clobber $di
+ INLINEASM &nop, 1, 12, implicit-def dead early-clobber $ax, 12, implicit-def dead early-clobber $di
+ $edi = COPY killed $ecx
+ CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp
+ $rax = POP64r implicit-def $rsp, implicit $rsp
RETQ
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir Wed Jan 31 14:04:26 2018
@@ -15,16 +15,16 @@
name: memory_alignment
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry:
- liveins: %rdi
+ liveins: $rdi
; CHECK: [[@LINE+1]]:65: expected 'align'
- %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, 32)
- %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
- %xmm2 = FsFLD0SS
- %xmm1 = MOVSSrr killed %xmm1, killed %xmm2
- MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)
- MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)
+ $xmm0 = MOVAPSrm $rdi, 1, _, 0, _ :: (load 16 from %ir.vec, 32)
+ $xmm1 = MOVAPSrm $rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
+ $xmm2 = FsFLD0SS
+ $xmm1 = MOVSSrr killed $xmm1, killed $xmm2
+ MOVAPSmr $rdi, 1, _, 0, _, killed $xmm0 :: (store 16 into %ir.vec, align 32)
+ MOVAPSmr killed $rdi, 1, _, 16, _, killed $xmm1 :: (store 16 into %ir.vec + 16, align 32)
RETQ
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir Wed Jan 31 14:04:26 2018
@@ -15,16 +15,16 @@
name: memory_alignment
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry:
- liveins: %rdi
+ liveins: $rdi
; CHECK: [[@LINE+1]]:70: expected an integer literal after 'align'
- %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align)
- %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
- %xmm2 = FsFLD0SS
- %xmm1 = MOVSSrr killed %xmm1, killed %xmm2
- MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)
- MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)
+ $xmm0 = MOVAPSrm $rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align)
+ $xmm1 = MOVAPSrm $rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
+ $xmm2 = FsFLD0SS
+ $xmm1 = MOVSSrr killed $xmm1, killed $xmm2
+ MOVAPSmr $rdi, 1, _, 0, _, killed $xmm0 :: (store 16 into %ir.vec, align 32)
+ MOVAPSmr killed $rdi, 1, _, 16, _, killed $xmm1 :: (store 16 into %ir.vec + 16, align 32)
RETQ
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir Wed Jan 31 14:04:26 2018
@@ -19,22 +19,22 @@
name: foo
tracksRegLiveness: true
liveins:
- - { reg: '%edi' }
+ - { reg: '$edi' }
body: |
; CHECK: [[@LINE+1]]:3: expected a basic block definition before instructions
successors: %bb.1.less, %bb.2.exit
- liveins: %edi 44
+ liveins: $edi 44
- CMP32ri8 %edi, 10, implicit-def %eflags
- JG_1 %bb.2.exit, implicit killed %eflags
+ CMP32ri8 $edi, 10, implicit-def $eflags
+ JG_1 %bb.2.exit, implicit killed $eflags
bb.1.less:
- %eax = MOV32r0 implicit-def dead %eflags
- RETQ killed %eax
+ $eax = MOV32r0 implicit-def dead $eflags
+ RETQ killed $eax
bb.2.exit:
- liveins: %edi
+ liveins: $edi
- %eax = COPY killed %edi
- RETQ killed %eax
+ $eax = COPY killed $edi
+ RETQ killed $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir Wed Jan 31 14:04:26 2018
@@ -21,9 +21,9 @@ body: |
bb.0.entry:
successors: %bb.1.block
; CHECK: [[@LINE+1]]:51: expected an IR block reference
- %rax = LEA64r %rip, 1, _, blockaddress(@test, _), _
- MOV64mr %rip, 1, _, @addr, _, killed %rax
- JMP64m %rip, 1, _, @addr, _
+ $rax = LEA64r $rip, 1, _, blockaddress(@test, _), _
+ MOV64mr $rip, 1, _, @addr, _, killed $rax
+ JMP64m $rip, 1, _, @addr, _
bb.1.block (address-taken):
RETQ
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir Wed Jan 31 14:04:26 2018
@@ -26,17 +26,17 @@ fixedStack:
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
body: |
bb.0.entry:
- PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
+ PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 16
; CHECK: [[@LINE+1]]:33: expected ','
- CFI_INSTRUCTION offset %rbx -16
- %ebx = COPY %edi, implicit-def %rbx
- %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags
- %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags
- %ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags
- %edi = COPY %ebx
- CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp
- %eax = LEA64_32r killed %rbx, 1, %rbx, 0, _
- %rbx = POP64r implicit-def %rsp, implicit %rsp
- RETQ %eax
+ CFI_INSTRUCTION offset $rbx -16
+ $ebx = COPY $edi, implicit-def $rbx
+ $ebx = ADD32rr $ebx, killed $esi, implicit-def dead $eflags
+ $ebx = ADD32rr $ebx, killed $edx, implicit-def dead $eflags
+ $ebx = ADD32rr $ebx, killed $ecx, implicit-def dead $eflags
+ $edi = COPY $ebx
+ CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp
+ $eax = LEA64_32r killed $rbx, 1, $rbx, 0, _
+ $rbx = POP64r implicit-def $rsp, implicit $rsp
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir Wed Jan 31 14:04:26 2018
@@ -15,11 +15,11 @@
name: test
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry2:
- liveins: %rdi
+ liveins: $rdi
; CHECK: [[@LINE+1]]:87: expected ',' before the next machine memory operand
- INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir.a) (load 4 from %ir.a)
+ INC32m killed $rdi, 1, _, 0, _, implicit-def dead $eflags :: (store 4 into %ir.a) (load 4 from %ir.a)
RETQ
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir Wed Jan 31 14:04:26 2018
@@ -21,14 +21,14 @@
name: foo
body: |
bb.0.entry:
- %eax = MOV32rm %rdi, 1, _, 0, _
- CMP32ri8 %eax, 10, implicit-def %eflags
+ $eax = MOV32rm $rdi, 1, _, 0, _
+ CMP32ri8 $eax, 10, implicit-def $eflags
; CHECK: [[@LINE+1]]:35: missing implicit register operand 'implicit %eflags'
- JG_1 %bb.2.exit, implicit %eax
+ JG_1 %bb.2.exit, implicit $eax
bb.1.less:
- %eax = MOV32r0 implicit-def %eflags
+ $eax = MOV32r0 implicit-def $eflags
bb.2.exit:
- RETQ %eax
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir Wed Jan 31 14:04:26 2018
@@ -21,14 +21,14 @@
name: foo
body: |
bb.0.entry:
- %eax = MOV32rm %rdi, 1, _, 0, _
- CMP32ri8 %eax, 10, implicit-def %eflags
+ $eax = MOV32rm $rdi, 1, _, 0, _
+ CMP32ri8 $eax, 10, implicit-def $eflags
; CHECK: [[@LINE+1]]:42: missing implicit register operand 'implicit %eflags'
- JG_1 %bb.2.exit, implicit-def %eflags
+ JG_1 %bb.2.exit, implicit-def $eflags
bb.1.less:
- %eax = MOV32r0 implicit-def %eflags
+ $eax = MOV32r0 implicit-def $eflags
bb.2.exit:
- RETQ %eax
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir Wed Jan 31 14:04:26 2018
@@ -21,9 +21,9 @@ body: |
bb.0.entry:
successors: %bb.1.block
; CHECK: [[@LINE+1]]:44: expected an IR function reference
- %rax = LEA64r %rip, 1, _, blockaddress(@addr, %ir-block.block), _
- MOV64mr %rip, 1, _, @addr, _, killed %rax
- JMP64m %rip, 1, _, @addr, _
+ $rax = LEA64r $rip, 1, _, blockaddress(@addr, %ir-block.block), _
+ MOV64mr $rip, 1, _, @addr, _, killed $rax
+ JMP64m $rip, 1, _, @addr, _
bb.1.block (address-taken):
RETQ
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir Wed Jan 31 14:04:26 2018
@@ -21,9 +21,9 @@ body: |
bb.0.entry:
successors: %bb.1.block
; CHECK: [[@LINE+1]]:44: expected a global value
- %rax = LEA64r %rip, 1, _, blockaddress(0, %ir-block.block), _
- MOV64mr %rip, 1, _, @addr, _, killed %rax
- JMP64m %rip, 1, _, @addr, _
+ $rax = LEA64r $rip, 1, _, blockaddress(0, %ir-block.block), _
+ MOV64mr $rip, 1, _, @addr, _, killed $rax
+ JMP64m $rip, 1, _, @addr, _
bb.1.block (address-taken):
RETQ
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir Wed Jan 31 14:04:26 2018
@@ -17,8 +17,8 @@ name: inc
body: |
bb.0.entry:
; CHECK: [[@LINE+1]]:37: expected an integer literal after '+'
- %rax = MOV64rm %rip, 1, _, @G + , _
- %eax = MOV32rm %rax, 1, _, 0, _
- %eax = INC32r %eax, implicit-def %eflags
- RETQ %eax
+ $rax = MOV64rm $rip, 1, _, @G + , _
+ $eax = MOV32rm $rax, 1, _, 0, _
+ $eax = INC32r $eax, implicit-def $eflags
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir Wed Jan 31 14:04:26 2018
@@ -12,13 +12,13 @@
name: test
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry:
- liveins: %rdi
+ liveins: $rdi
; CHECK: [[@LINE+1]]:78: expected tied-def or low-level type after '('
- INLINEASM &"$foo", 1, 2818058, def %rdi, 2147483657, killed %rdi(tied-def)
- %rax = COPY killed %rdi
- RETQ killed %rax
+ INLINEASM &"$foo", 1, 2818058, def $rdi, 2147483657, killed $rdi(tied-def)
+ $rax = COPY killed $rdi
+ RETQ killed $rax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir Wed Jan 31 14:04:26 2018
@@ -21,18 +21,18 @@ body: |
bb.0.entry:
; CHECK: [[@LINE+1]]:29: expected an integer literal after '('
successors: %bb.1.less (_), %bb.2.exit(32)
- liveins: %edi
+ liveins: $edi
- CMP32ri8 %edi, 10, implicit-def %eflags
- JG_1 %bb.2.exit, implicit killed %eflags
+ CMP32ri8 $edi, 10, implicit-def $eflags
+ JG_1 %bb.2.exit, implicit killed $eflags
bb.1.less:
- %eax = MOV32r0 implicit-def dead %eflags
- RETQ killed %eax
+ $eax = MOV32r0 implicit-def dead $eflags
+ RETQ killed $eax
bb.2.exit:
- liveins: %edi
+ liveins: $edi
- %eax = COPY killed %edi
- RETQ killed %eax
+ $eax = COPY killed $edi
+ RETQ killed $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir Wed Jan 31 14:04:26 2018
@@ -13,11 +13,11 @@
name: test
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry:
- liveins: %rdi
+ liveins: $rdi
; CHECK: [[@LINE+1]]:48: expected 'load' or 'store' memory operation
- %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (4 from %ir.a)
- RETQ %eax
+ $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (4 from %ir.a)
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-machine-operand.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-machine-operand.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-machine-operand.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-machine-operand.mir Wed Jan 31 14:04:26 2018
@@ -13,7 +13,7 @@ name: foo
body: |
bb.0.entry:
; CHECK: [[@LINE+1]]:20: expected a machine operand
- %eax = XOR32rr =
- RETQ %eax
+ $eax = XOR32rr =
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir Wed Jan 31 14:04:26 2018
@@ -48,10 +48,10 @@ stack:
- { id: 0, name: x.addr, size: 4, alignment: 4 }
body: |
bb.0.entry:
- %0 = COPY %edi
+ %0 = COPY $edi
; CHECK: [[@LINE+1]]:46: expected a metadata node after 'debug-location'
DBG_VALUE _, 0, !12, !13, debug-location 14
- MOV32mr %stack.x.addr, 1, _, 0, _, %0
- %eax = COPY %0
- RETQ %eax
+ MOV32mr $stack.x.addr, 1, _, 0, _, %0
+ $eax = COPY %0
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir Wed Jan 31 14:04:26 2018
@@ -48,10 +48,10 @@ stack:
- { id: 0, name: x.addr, size: 4, alignment: 4 }
body: |
bb.0.entry:
- %0 = COPY %edi
+ %0 = COPY $edi
; CHECK: [[@LINE+1]]:28: expected metadata id after '!'
DBG_VALUE _, 0, !12, ! _
MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
- %eax = COPY %0
- RETQ %eax
+ $eax = COPY %0
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir Wed Jan 31 14:04:26 2018
@@ -11,15 +11,15 @@
---
name: test
liveins:
- - { reg: '%edi' }
+ - { reg: '$edi' }
stack:
# CHECK: [[@LINE+1]]:74: expected a metadata node
- { id: 0, name: xa, offset: -12, size: 4, alignment: 4, di-variable: '0' }
body: |
bb.0.entry:
- liveins: %edi
+ liveins: $edi
- MOV32mr %rsp, 1, _, -4, _, %edi :: (store 4 into %ir.xa)
- %eax = COPY killed %edi
- RETQ killed %eax
+ MOV32mr $rsp, 1, _, -4, _, $edi :: (store 4 into %ir.xa)
+ $eax = COPY killed $edi
+ RETQ killed $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir Wed Jan 31 14:04:26 2018
@@ -15,16 +15,16 @@ tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
# CHECK: - { id: 1, class: gr32, preferred-register: '%0' }
- # CHECK: - { id: 2, class: gr32, preferred-register: '%edi' }
+ # CHECK: - { id: 2, class: gr32, preferred-register: '$edi' }
- { id: 1, class: gr32, preferred-register: '%0' }
- - { id: 2, class: gr32, preferred-register: '%edi' }
+ - { id: 2, class: gr32, preferred-register: '$edi' }
body: |
bb.0.body:
- liveins: %edi, %esi
+ liveins: $edi, $esi
- %1 = COPY %esi
- %2 = COPY %edi
- %2 = IMUL32rr %2, %1, implicit-def dead %eflags
- %eax = COPY %2
- RETQ killed %eax
+ %1 = COPY $esi
+ %2 = COPY $edi
+ %2 = IMUL32rr %2, %1, implicit-def dead $eflags
+ $eax = COPY %2
+ RETQ killed $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir Wed Jan 31 14:04:26 2018
@@ -34,10 +34,10 @@ name: compute
tracksRegLiveness: true
body: |
bb.0.body:
- liveins: %edi
+ liveins: $edi
- %eax = COPY killed %edi
- RETQ killed %eax
+ $eax = COPY killed $edi
+ RETQ killed $eax
...
---
name: func
@@ -55,34 +55,34 @@ stack:
body: |
bb.0.entry:
successors: %bb.1.check
- liveins: %edi, %rbx
+ liveins: $edi, $rbx
- frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
- %rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags
- %ebx = COPY %edi
- MOV32mr %rsp, 1, _, 12, _, %ebx
+ frame-setup PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp
+ $rsp = frame-setup SUB64ri8 $rsp, 16, implicit-def dead $eflags
+ $ebx = COPY $edi
+ MOV32mr $rsp, 1, _, 12, _, $ebx
bb.1.check:
successors: %bb.2.loop, %bb.3.exit
- liveins: %ebx
+ liveins: $ebx
- CMP32ri8 %ebx, 10, implicit-def %eflags
- JG_1 %bb.3.exit, implicit killed %eflags
+ CMP32ri8 $ebx, 10, implicit-def $eflags
+ JG_1 %bb.3.exit, implicit killed $eflags
JMP_1 %bb.2.loop
bb.2.loop:
successors: %bb.1.check
- liveins: %ebx
+ liveins: $ebx
- %edi = MOV32rm %rsp, 1, _, 12, _
- CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
- %eax = DEC32r killed %eax, implicit-def dead %eflags
- MOV32mr %rsp, 1, _, 12, _, killed %eax
+ $edi = MOV32rm $rsp, 1, _, 12, _
+ CALL64pcrel32 @compute, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax
+ $eax = DEC32r killed $eax, implicit-def dead $eflags
+ MOV32mr $rsp, 1, _, 12, _, killed $eax
JMP_1 %bb.1.check
bb.3.exit:
- %eax = MOV32r0 implicit-def dead %eflags
- %rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags
- %rbx = POP64r implicit-def %rsp, implicit %rsp
- RETQ %eax
+ $eax = MOV32r0 implicit-def dead $eflags
+ $rsp = ADD64ri8 $rsp, 16, implicit-def dead $eflags
+ $rbx = POP64r implicit-def $rsp, implicit $rsp
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-livein.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-livein.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-livein.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-livein.mir Wed Jan 31 14:04:26 2018
@@ -15,6 +15,6 @@ body: |
; CHECK: [[@LINE+1]]:14: expected a named register
liveins: %0
- %eax = COPY %edi
- RETQ %eax
+ $eax = COPY $edi
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir Wed Jan 31 14:04:26 2018
@@ -19,23 +19,23 @@
name: foo
tracksRegLiveness: true
liveins:
- - { reg: '%edi' }
+ - { reg: '$edi' }
body: |
bb.0.entry:
successors: %bb.1.less, %bb.2.exit
; CHECK: [[@LINE+1]]:19: expected line break at the end of a list
- liveins: %edi 44
+ liveins: $edi 44
- CMP32ri8 %edi, 10, implicit-def %eflags
- JG_1 %bb.2.exit, implicit killed %eflags
+ CMP32ri8 $edi, 10, implicit-def $eflags
+ JG_1 %bb.2.exit, implicit killed $eflags
bb.1.less:
- %eax = MOV32r0 implicit-def dead %eflags
- RETQ killed %eax
+ $eax = MOV32r0 implicit-def dead $eflags
+ RETQ killed $eax
bb.2.exit:
- liveins: %edi
+ liveins: $edi
- %eax = COPY killed %edi
- RETQ killed %eax
+ $eax = COPY killed $edi
+ RETQ killed $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-number-after-bb.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-number-after-bb.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-number-after-bb.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-number-after-bb.mir Wed Jan 31 14:04:26 2018
@@ -20,14 +20,14 @@
name: foo
body: |
bb.0.entry:
- %eax = MOV32rm %rdi, 1, _, 0, _
- CMP32ri8 %eax, 10, implicit-def %eflags
+ $eax = MOV32rm $rdi, 1, _, 0, _
+ CMP32ri8 $eax, 10, implicit-def $eflags
; CHECK: [[@LINE+1]]:14: expected a number after '%bb.'
- JG_1 %bb.nah, implicit %eflags
+ JG_1 %bb.nah, implicit $eflags
bb.1.true:
- %eax = MOV32r0 implicit-def %eflags
+ $eax = MOV32r0 implicit-def $eflags
bb.2.nah:
- RETQ %eax
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir Wed Jan 31 14:04:26 2018
@@ -18,10 +18,10 @@ stack:
- { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 }
body: |
bb.0.entry:
- %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags
+ $rsp = SUB64ri32 $rsp, 4040, implicit-def dead $eflags
; CHECK: [[@LINE+1]]:36: expected a cfi offset
CFI_INSTRUCTION def_cfa_offset _
- %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags
+ $rsp = ADD64ri32 $rsp, 4040, implicit-def dead $eflags
RETQ
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir Wed Jan 31 14:04:26 2018
@@ -13,12 +13,12 @@
name: test
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry:
- liveins: %rdi
+ liveins: $rdi
; CHECK: [[@LINE+1]]:60: expected a pointer IR value
- %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.b)
- RETQ %eax
+ $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load 4 from %ir.b)
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir Wed Jan 31 14:04:26 2018
@@ -15,16 +15,16 @@
name: memory_alignment
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry:
- liveins: %rdi
+ liveins: $rdi
; CHECK: [[@LINE+1]]:71: expected an integer literal after 'align'
- %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align -32)
- %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
- %xmm2 = FsFLD0SS
- %xmm1 = MOVSSrr killed %xmm1, killed %xmm2
- MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)
- MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)
+ $xmm0 = MOVAPSrm $rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align -32)
+ $xmm1 = MOVAPSrm $rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
+ $xmm2 = FsFLD0SS
+ $xmm1 = MOVSSrr killed $xmm1, killed $xmm2
+ MOVAPSmr $rdi, 1, _, 0, _, killed $xmm0 :: (store 16 into %ir.vec, align 32)
+ MOVAPSmr killed $rdi, 1, _, 16, _, killed $xmm1 :: (store 16 into %ir.vec + 16, align 32)
RETQ
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir Wed Jan 31 14:04:26 2018
@@ -26,17 +26,17 @@ fixedStack:
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
body: |
bb.0.entry:
- PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
+ PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 16
; CHECK: [[@LINE+1]]:28: expected a cfi register
CFI_INSTRUCTION offset %0, -16
- %ebx = COPY %edi, implicit-def %rbx
- %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags
- %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags
- %ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags
- %edi = COPY %ebx
- CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp
- %eax = LEA64_32r killed %rbx, 1, %rbx, 0, _
- %rbx = POP64r implicit-def %rsp, implicit %rsp
- RETQ %eax
+ $ebx = COPY $edi, implicit-def $rbx
+ $ebx = ADD32rr $ebx, killed $esi, implicit-def dead $eflags
+ $ebx = ADD32rr $ebx, killed $edx, implicit-def dead $eflags
+ $ebx = ADD32rr $ebx, killed $ecx, implicit-def dead $eflags
+ $edi = COPY $ebx
+ CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp
+ $eax = LEA64_32r killed $rbx, 1, $rbx, 0, _
+ $rbx = POP64r implicit-def $rsp, implicit $rsp
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-register-after-flags.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-register-after-flags.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-register-after-flags.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-register-after-flags.mir Wed Jan 31 14:04:26 2018
@@ -15,6 +15,6 @@ name: foo
body: |
bb.0.entry:
; CHECK: [[@LINE+1]]:33: expected a register after register flags
- %eax = MOV32r0 implicit-def 2
- RETQ %eax
+ $eax = MOV32r0 implicit-def 2
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir Wed Jan 31 14:04:26 2018
@@ -13,12 +13,12 @@
name: test
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry:
- liveins: %rdi
+ liveins: $rdi
; CHECK: [[@LINE+1]]:53: expected an atomic scope, ordering or a size integer literal
- %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load from %ir.a)
- RETQ %eax
+ $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load from %ir.a)
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-stack-object.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-stack-object.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-stack-object.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-stack-object.mir Wed Jan 31 14:04:26 2018
@@ -42,26 +42,26 @@ frameInfo:
stackProtector: '0'
fixedStack:
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16,
- callee-saved-register: '%rbx' }
+ callee-saved-register: '$rbx' }
stack:
- { id: 0, name: StackGuardSlot, offset: -24, size: 8, alignment: 8 }
- { id: 1, name: test, offset: -40, size: 8, alignment: 8 }
- { id: 2, name: a, offset: -29, size: 5, alignment: 1 }
body: |
bb.0.entry:
- liveins: %rbx, %rbx
+ liveins: $rbx, $rbx
- frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
- %rsp = frame-setup SUB64ri8 %rsp, 32, implicit-def dead %eflags
- %rbx = LOAD_STACK_GUARD :: (invariant load 8 from %ir.__stack_chk_guard)
- MOV64mr %rsp, 1, _, 24, _, %rbx
- %rsi = LEA64r %rsp, 1, _, 19, _
- MOV64mr %rsp, 1, _, 8, _, %rsi
- %rdi = LEA64r %rip, 1, _, @.str, _
- dead %eax = MOV32r0 implicit-def dead %eflags, implicit-def %al
- CALL64pcrel32 @printf, csr_64, implicit %rsp, implicit %rdi, implicit %rsi, implicit %al, implicit-def %rsp, implicit-def %eax
- CMP64rm killed %rbx, %rsp, 1, _, 24, _, implicit-def %eflags
- %rsp = ADD64ri8 %rsp, 32, implicit-def dead %eflags
- %rbx = POP64r implicit-def %rsp, implicit %rsp
- RETQ %eax
+ frame-setup PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp
+ $rsp = frame-setup SUB64ri8 $rsp, 32, implicit-def dead $eflags
+ $rbx = LOAD_STACK_GUARD :: (invariant load 8 from %ir.__stack_chk_guard)
+ MOV64mr $rsp, 1, _, 24, _, $rbx
+ $rsi = LEA64r $rsp, 1, _, 19, _
+ MOV64mr $rsp, 1, _, 8, _, $rsi
+ $rdi = LEA64r $rip, 1, _, @.str, _
+ dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $al
+ CALL64pcrel32 @printf, csr_64, implicit $rsp, implicit $rdi, implicit $rsi, implicit $al, implicit-def $rsp, implicit-def $eax
+ CMP64rm killed $rbx, $rsp, 1, _, 24, _, implicit-def $eflags
+ $rsp = ADD64ri8 $rsp, 32, implicit-def dead $eflags
+ $rbx = POP64r implicit-def $rsp, implicit $rsp
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir Wed Jan 31 14:04:26 2018
@@ -17,10 +17,10 @@ registers:
- { id: 2, class: gr8 }
body: |
bb.0.entry:
- %0 = COPY %edi
+ %0 = COPY $edi
; CHECK: [[@LINE+1]]:20: expected a subregister index after '.'
%1 = COPY %0 . 42
- %2 = AND8ri %1, 1, implicit-def %eflags
- %al = COPY %2
- RETQ %al
+ %2 = AND8ri %1, 1, implicit-def $eflags
+ $al = COPY %2
+ RETQ $al
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-target-flag-name.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-target-flag-name.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-target-flag-name.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-target-flag-name.mir Wed Jan 31 14:04:26 2018
@@ -17,8 +17,8 @@ name: inc
body: |
bb.0.entry:
; CHECK: [[@LINE+1]]:46: expected the name of the target flag
- %rax = MOV64rm %rip, 1, _, target-flags( ) @G, _
- %eax = MOV32rm killed %rax, 1, _, 0, _
- %eax = INC32r killed %eax, implicit-def dead %eflags
- RETQ %eax
+ $rax = MOV64rm $rip, 1, _, target-flags( ) @G, _
+ $eax = MOV32rm killed $rax, 1, _, 0, _
+ $eax = INC32r killed $eax, implicit-def dead $eflags
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir Wed Jan 31 14:04:26 2018
@@ -12,13 +12,13 @@
name: test
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry:
- liveins: %rdi
+ liveins: $rdi
; CHECK: [[@LINE+1]]:70: expected tied-def or low-level type after '('
- INLINEASM &"$foo", 1, 2818058, def %rdi, 2147483657, killed %rdi(3)
- %rax = COPY killed %rdi
- RETQ killed %rax
+ INLINEASM &"$foo", 1, 2818058, def $rdi, 2147483657, killed $rdi(3)
+ $rax = COPY killed $rdi
+ RETQ killed $rax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir Wed Jan 31 14:04:26 2018
@@ -13,12 +13,12 @@
name: test
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry:
- liveins: %rdi
+ liveins: $rdi
; CHECK: [[@LINE+1]]:60: expected an IR value reference
- %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from a)
- RETQ %eax
+ $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load 4 from a)
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir Wed Jan 31 14:04:26 2018
@@ -15,12 +15,12 @@ registers:
- { id: 0, class: gr32 }
liveins:
# CHECK: [[@LINE+1]]:34: expected a virtual register
- - { reg: '%edi', virtual-reg: '%edi' }
+ - { reg: '$edi', virtual-reg: '$edi' }
body: |
bb.0.body:
- liveins: %edi
+ liveins: $edi
- %0 = COPY %edi
- %eax = COPY %0
- RETQ %eax
+ %0 = COPY $edi
+ $eax = COPY %0
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/external-symbol-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/external-symbol-operands.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/external-symbol-operands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/external-symbol-operands.mir Wed Jan 31 14:04:26 2018
@@ -32,21 +32,21 @@ tracksRegLiveness: true
body: |
bb.0.entry:
successors: %bb.1.entry, %bb.2.entry
- liveins: %edi
+ liveins: $edi
- %rsp = SUB64ri32 %rsp, 520, implicit-def %eflags
- %rcx = LOAD_STACK_GUARD
- MOV64mr %rsp, 1, _, 512, _, %rcx
- %rax = MOVSX64rr32 %edi
- %eax = MOV32rm %rsp, 4, %rax, 0, _
- CMP64rm %rcx, %rsp, 1, _, 512, _, implicit-def %eflags
- JNE_1 %bb.2.entry, implicit %eflags
+ $rsp = SUB64ri32 $rsp, 520, implicit-def $eflags
+ $rcx = LOAD_STACK_GUARD
+ MOV64mr $rsp, 1, _, 512, _, $rcx
+ $rax = MOVSX64rr32 $edi
+ $eax = MOV32rm $rsp, 4, $rax, 0, _
+ CMP64rm $rcx, $rsp, 1, _, 512, _, implicit-def $eflags
+ JNE_1 %bb.2.entry, implicit $eflags
bb.1.entry:
- liveins: %eax
+ liveins: $eax
- %rsp = ADD64ri32 %rsp, 520, implicit-def %eflags
- RETQ %eax
+ $rsp = ADD64ri32 $rsp, 520, implicit-def $eflags
+ RETQ $eax
bb.2.entry:
; CHECK: CALL64pcrel32 &__stack_chk_fail,
@@ -55,10 +55,10 @@ body: |
; CHECK-NEXT: CALL64pcrel32 &"$Quoted \09 External symbol \11 ",
; CHECK-NEXT: CALL64pcrel32 &__stack_chk_fail + 2,
; CHECK-NEXT: CALL64pcrel32 &" check stack - 20" - 20,
- CALL64pcrel32 &__stack_chk_fail, csr_64, implicit %rsp, implicit-def %rsp
- CALL64pcrel32 &__stack_chk_fail.09-_, csr_64, implicit %rsp, implicit-def %rsp
- CALL64pcrel32 &__stack_chk_fail$, csr_64, implicit %rsp, implicit-def %rsp
- CALL64pcrel32 &"$Quoted \09 External symbol \11 ", csr_64, implicit %rsp, implicit-def %rsp
- CALL64pcrel32 &__stack_chk_fail + 2, csr_64, implicit %rsp, implicit-def %rsp
- CALL64pcrel32 &" check stack - 20" - 20, csr_64, implicit %rsp, implicit-def %rsp
+ CALL64pcrel32 &__stack_chk_fail, csr_64, implicit $rsp, implicit-def $rsp
+ CALL64pcrel32 &__stack_chk_fail.09-_, csr_64, implicit $rsp, implicit-def $rsp
+ CALL64pcrel32 &__stack_chk_fail$, csr_64, implicit $rsp, implicit-def $rsp
+ CALL64pcrel32 &"$Quoted \09 External symbol \11 ", csr_64, implicit $rsp, implicit-def $rsp
+ CALL64pcrel32 &__stack_chk_fail + 2, csr_64, implicit $rsp, implicit-def $rsp
+ CALL64pcrel32 &" check stack - 20" - 20, csr_64, implicit $rsp, implicit-def $rsp
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir Wed Jan 31 14:04:26 2018
@@ -28,12 +28,12 @@ stack:
- { id: 0, name: b, offset: -8, size: 4, alignment: 4 }
body: |
bb.0.entry:
- frame-setup PUSH32r undef %eax, implicit-def %esp, implicit %esp
+ frame-setup PUSH32r undef $eax, implicit-def $esp, implicit $esp
CFI_INSTRUCTION def_cfa_offset 8
; CHECK: name: test
- ; CHECK: %eax = MOV32rm %esp, 1, %noreg, 8, %noreg :: (load 4 from %fixed-stack.0, align 16)
- %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)
- MOV32mr %esp, 1, _, 0, _, %eax :: (store 4 into %ir.b)
- %edx = POP32r implicit-def %esp, implicit %esp
- RETL %eax
+ ; CHECK: $eax = MOV32rm $esp, 1, $noreg, 8, $noreg :: (load 4 from %fixed-stack.0, align 16)
+ $eax = MOV32rm $esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)
+ MOV32mr $esp, 1, _, 0, _, $eax :: (store 4 into %ir.b)
+ $edx = POP32r implicit-def $esp, implicit $esp
+ RETL $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir Wed Jan 31 14:04:26 2018
@@ -22,7 +22,7 @@ fixedStack:
- { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
body: |
bb.0.entry:
- %eax = MOV32rm %esp, 1, _, 4, _
- %eax = ADD32rm killed %eax, %esp, 1, _, 8, _, implicit-def dead %eflags
- RETL %eax
+ $eax = MOV32rm $esp, 1, _, 4, _
+ $eax = ADD32rm killed $eax, $esp, 1, _, 8, _, implicit-def dead $eflags
+ RETL $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-objects.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-objects.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-objects.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-objects.mir Wed Jan 31 14:04:26 2018
@@ -28,7 +28,7 @@ stack:
- { id: 0, offset: -8, size: 4, alignment: 4 }
body: |
bb.0.entry:
- %eax = MOV32rm %esp, 1, _, 8, _
- MOV32mr %esp, 1, _, 0, _, %eax
- RETL %eax
+ $eax = MOV32rm $esp, 1, _, 8, _
+ MOV32mr $esp, 1, _, 0, _, $eax
+ RETL $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir Wed Jan 31 14:04:26 2018
@@ -27,8 +27,8 @@
name: foo
tracksRegLiveness: true
liveins:
- - { reg: '%edi' }
- - { reg: '%esi' }
+ - { reg: '$edi' }
+ - { reg: '$esi' }
# CHECK: frameInfo:
# CHECK: savePoint: '%bb.2'
# CHECK-NEXT: restorePoint: '%bb.2'
@@ -43,31 +43,31 @@ stack:
body: |
bb.0:
successors: %bb.2, %bb.1
- liveins: %edi, %esi
+ liveins: $edi, $esi
- %eax = COPY %edi
- CMP32rr %eax, killed %esi, implicit-def %eflags
- JL_1 %bb.2, implicit killed %eflags
+ $eax = COPY $edi
+ CMP32rr $eax, killed $esi, implicit-def $eflags
+ JL_1 %bb.2, implicit killed $eflags
bb.1:
successors: %bb.3
- liveins: %eax
+ liveins: $eax
JMP_1 %bb.3
bb.2.true:
successors: %bb.3
- liveins: %eax
+ liveins: $eax
- MOV32mr %stack.0.tmp, 1, _, 0, _, killed %eax
- ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %ssp, implicit-def dead %eflags, implicit %rsp, implicit %ssp
- %rsi = LEA64r %stack.0.tmp, 1, _, 0, _
- %edi = MOV32r0 implicit-def dead %eflags
- CALL64pcrel32 @doSomething, csr_64, implicit %rsp, implicit %ssp, implicit %edi, implicit %rsi, implicit-def %rsp, implicit-def %ssp, implicit-def %eax
- ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %ssp, implicit-def dead %eflags, implicit %rsp, implicit %ssp
+ MOV32mr %stack.0.tmp, 1, _, 0, _, killed $eax
+ ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $ssp, implicit-def dead $eflags, implicit $rsp, implicit $ssp
+ $rsi = LEA64r %stack.0.tmp, 1, _, 0, _
+ $edi = MOV32r0 implicit-def dead $eflags
+ CALL64pcrel32 @doSomething, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit $rsi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
+ ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $ssp, implicit-def dead $eflags, implicit $rsp, implicit $ssp
bb.3.false:
- liveins: %eax
+ liveins: $eax
- RETQ %eax
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/frame-info-stack-references.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/frame-info-stack-references.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/frame-info-stack-references.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/frame-info-stack-references.mir Wed Jan 31 14:04:26 2018
@@ -45,7 +45,7 @@ frameInfo:
stackProtector: '%stack.0.StackGuardSlot'
fixedStack:
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16,
- callee-saved-register: '%rbx' }
+ callee-saved-register: '$rbx' }
stack:
- { id: 0, name: StackGuardSlot, offset: -24, size: 8, alignment: 8 }
- { id: 1, name: test, offset: -40, size: 8, alignment: 8 }
@@ -53,27 +53,27 @@ stack:
body: |
bb.0.entry:
successors: %bb.1.entry, %bb.2.entry
- liveins: %rbx, %rbx
+ liveins: $rbx, $rbx
- frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
- %rsp = frame-setup SUB64ri8 %rsp, 32, implicit-def dead %eflags
- %rbx = LOAD_STACK_GUARD :: (invariant load 8 from @__stack_chk_guard)
- MOV64mr %rsp, 1, _, 24, _, %rbx
- %rsi = LEA64r %rsp, 1, _, 19, _
- MOV64mr %rsp, 1, _, 8, _, %rsi
- %rdi = LEA64r %rip, 1, _, @.str, _
- dead %eax = MOV32r0 implicit-def dead %eflags, implicit-def %al
- CALL64pcrel32 @printf, csr_64, implicit %rsp, implicit %rdi, implicit %rsi, implicit %al, implicit-def %rsp, implicit-def %eax
- CMP64rm killed %rbx, %rsp, 1, _, 24, _, implicit-def %eflags
- JNE_1 %bb.2.entry, implicit %eflags
+ frame-setup PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp
+ $rsp = frame-setup SUB64ri8 $rsp, 32, implicit-def dead $eflags
+ $rbx = LOAD_STACK_GUARD :: (invariant load 8 from @__stack_chk_guard)
+ MOV64mr $rsp, 1, _, 24, _, $rbx
+ $rsi = LEA64r $rsp, 1, _, 19, _
+ MOV64mr $rsp, 1, _, 8, _, $rsi
+ $rdi = LEA64r $rip, 1, _, @.str, _
+ dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $al
+ CALL64pcrel32 @printf, csr_64, implicit $rsp, implicit $rdi, implicit $rsi, implicit $al, implicit-def $rsp, implicit-def $eax
+ CMP64rm killed $rbx, $rsp, 1, _, 24, _, implicit-def $eflags
+ JNE_1 %bb.2.entry, implicit $eflags
bb.1.entry:
- liveins: %eax
+ liveins: $eax
- %rsp = ADD64ri8 %rsp, 32, implicit-def dead %eflags
- %rbx = POP64r implicit-def %rsp, implicit %rsp
- RETQ %eax
+ $rsp = ADD64ri8 $rsp, 32, implicit-def dead $eflags
+ $rbx = POP64r implicit-def $rsp, implicit $rsp
+ RETQ $eax
bb.2.entry:
- CALL64pcrel32 &__stack_chk_fail, csr_64, implicit %rsp, implicit-def %rsp
+ CALL64pcrel32 &__stack_chk_fail, csr_64, implicit $rsp, implicit-def $rsp
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir Wed Jan 31 14:04:26 2018
@@ -20,17 +20,17 @@
name: compute
body: |
bb.0.body:
- %eax = IMUL32rri8 %edi, 11, implicit-def %eflags
- RETQ %eax
+ $eax = IMUL32rri8 $edi, 11, implicit-def $eflags
+ RETQ $eax
...
---
name: foo
body: |
bb.0.entry:
- ; CHECK: frame-setup PUSH64r %rax
- frame-setup PUSH64r %rax, implicit-def %rsp, implicit %rsp
- CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
- ; CHECK: %rdx = frame-destroy POP64r
- %rdx = frame-destroy POP64r implicit-def %rsp, implicit %rsp
- RETQ %eax
+ ; CHECK: frame-setup PUSH64r $rax
+ frame-setup PUSH64r $rax, implicit-def $rsp, implicit $rsp
+ CALL64pcrel32 @compute, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax
+ ; CHECK: $rdx = frame-destroy POP64r
+ $rdx = frame-destroy POP64r implicit-def $rsp, implicit $rsp
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/function-liveins.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/function-liveins.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/function-liveins.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/function-liveins.mir Wed Jan 31 14:04:26 2018
@@ -19,18 +19,18 @@ registers:
- { id: 1, class: gr32 }
- { id: 2, class: gr32 }
# CHECK: liveins:
-# CHECK-NEXT: - { reg: '%edi', virtual-reg: '%0' }
-# CHECK-NEXT: - { reg: '%esi', virtual-reg: '%1' }
+# CHECK-NEXT: - { reg: '$edi', virtual-reg: '%0' }
+# CHECK-NEXT: - { reg: '$esi', virtual-reg: '%1' }
liveins:
- - { reg: '%edi', virtual-reg: '%0' }
- - { reg: '%esi', virtual-reg: '%1' }
+ - { reg: '$edi', virtual-reg: '%0' }
+ - { reg: '$esi', virtual-reg: '%1' }
body: |
bb.0.body:
- liveins: %edi, %esi
+ liveins: $edi, $esi
- %1 = COPY %esi
- %0 = COPY %edi
- %2 = ADD32rr %0, %1, implicit-def dead %eflags
- %eax = COPY %2
- RETQ %eax
+ %1 = COPY $esi
+ %0 = COPY $edi
+ %2 = ADD32rr %0, %1, implicit-def dead $eflags
+ $eax = COPY %2
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/generic-instr-type.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/generic-instr-type.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/generic-instr-type.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/generic-instr-type.mir Wed Jan 31 14:04:26 2018
@@ -36,11 +36,11 @@ registers:
- { id: 8, class: _ }
body: |
bb.0:
- liveins: %edi, %xmm0
+ liveins: $edi, $xmm0
; CHECK: %1:_(s32) = G_ADD %0
- %0(s32) = COPY %edi
- %6(<4 x s32>) = COPY %xmm0
- %7(s64) = COPY %rdi
+ %0(s32) = COPY $edi
+ %6(<4 x s32>) = COPY $xmm0
+ %7(s64) = COPY $rdi
%1(s32) = G_ADD %0, %0
; CHECK: %2:_(<4 x s32>) = G_ADD %6, %6
Modified: llvm/trunk/test/CodeGen/MIR/X86/global-value-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/global-value-operands.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/global-value-operands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/global-value-operands.mir Wed Jan 31 14:04:26 2018
@@ -64,22 +64,22 @@
name: inc
body: |
bb.0.entry:
- ; CHECK: %rax = MOV64rm %rip, 1, %noreg, @G, %noreg
- %rax = MOV64rm %rip, 1, _, @G, _
- %eax = MOV32rm %rax, 1, _, 0, _
- %eax = INC32r %eax, implicit-def %eflags
- RETQ %eax
+ ; CHECK: $rax = MOV64rm $rip, 1, $noreg, @G, $noreg
+ $rax = MOV64rm $rip, 1, _, @G, _
+ $eax = MOV32rm $rax, 1, _, 0, _
+ $eax = INC32r $eax, implicit-def $eflags
+ RETQ $eax
...
---
# CHECK: name: inc2
name: inc2
body: |
bb.0.entry:
- ; CHECK: %rax = MOV64rm %rip, 1, %noreg, @0, %noreg
- %rax = MOV64rm %rip, 1, _, @0, _
- %eax = MOV32rm %rax, 1, _, 0, _
- %eax = INC32r %eax, implicit-def %eflags
- RETQ %eax
+ ; CHECK: $rax = MOV64rm $rip, 1, $noreg, @0, $noreg
+ $rax = MOV64rm $rip, 1, _, @0, _
+ $eax = MOV32rm $rax, 1, _, 0, _
+ $eax = INC32r $eax, implicit-def $eflags
+ RETQ $eax
...
---
name: test
@@ -89,24 +89,24 @@ body: |
; CHECK: , @-_-,
; CHECK: , @_-_a,
; CHECK: , @"$.-B",
- %rax = MOV64rm %rip, 1, _, @.$0, _
- %eax = MOV32rm killed %rax, 1, _, 0, _
- %rcx = MOV64rm %rip, 1, _, @-_-, _
- MOV32mr killed %rcx, 1, _, 0, _, killed %eax
- %rax = MOV64rm %rip, 1, _, @_-_a, _
- %eax = MOV32rm killed %rax, 1, _, 0, _
- %rcx = MOV64rm %rip, 1, _, @$.-B, _
- MOV32mr killed %rcx, 1, _, 0, _, %eax
- RETQ %eax
+ $rax = MOV64rm $rip, 1, _, @.$0, _
+ $eax = MOV32rm killed $rax, 1, _, 0, _
+ $rcx = MOV64rm $rip, 1, _, @-_-, _
+ MOV32mr killed $rcx, 1, _, 0, _, killed $eax
+ $rax = MOV64rm $rip, 1, _, @_-_a, _
+ $eax = MOV32rm killed $rax, 1, _, 0, _
+ $rcx = MOV64rm $rip, 1, _, @$.-B, _
+ MOV32mr killed $rcx, 1, _, 0, _, $eax
+ RETQ $eax
...
---
name: test2
body: |
bb.0.entry:
; CHECK: , @"\01Hello@$%09 \5C World,",
- %rax = MOV64rm %rip, 1, _, @"\01Hello@$%09 \\ World,", _
- %eax = MOV32rm killed %rax, 1, _, 0, _
- RETQ %eax
+ $rax = MOV64rm $rip, 1, _, @"\01Hello@$%09 \\ World,", _
+ $eax = MOV32rm killed $rax, 1, _, 0, _
+ RETQ $eax
...
---
# CHECK: name: test3
@@ -117,24 +117,24 @@ body: |
; CHECK: , @-_-,
; CHECK: , @_-_a + 4,
; CHECK: , @"$.-B" - 8,
- %rax = MOV64rm %rip, 1, _, @.$0 + 0, _
- %eax = MOV32rm killed %rax, 1, _, 0, _
- %rcx = MOV64rm %rip, 1, _, @-_- - 0, _
- MOV32mr killed %rcx, 1, _, 0, _, killed %eax
- %rax = MOV64rm %rip, 1, _, @_-_a + 4, _
- %eax = MOV32rm killed %rax, 1, _, 0, _
- %rcx = MOV64rm %rip, 1, _, @$.-B - 8, _
- MOV32mr killed %rcx, 1, _, 0, _, %eax
- RETQ %eax
+ $rax = MOV64rm $rip, 1, _, @.$0 + 0, _
+ $eax = MOV32rm killed $rax, 1, _, 0, _
+ $rcx = MOV64rm $rip, 1, _, @-_- - 0, _
+ MOV32mr killed $rcx, 1, _, 0, _, killed $eax
+ $rax = MOV64rm $rip, 1, _, @_-_a + 4, _
+ $eax = MOV32rm killed $rax, 1, _, 0, _
+ $rcx = MOV64rm $rip, 1, _, @$.-B - 8, _
+ MOV32mr killed $rcx, 1, _, 0, _, $eax
+ RETQ $eax
...
---
# CHECK: name: tf
name: tf
body: |
bb.0.entry:
- ; CHECK: %rax = MOV64rm %rip, 1, %noreg, target-flags(x86-gotpcrel) @G, %noreg
- %rax = MOV64rm %rip, 1, _, target-flags(x86-gotpcrel) @G, _
- %eax = MOV32rm %rax, 1, _, 0, _
- %eax = INC32r %eax, implicit-def %eflags
- RETQ %eax
+ ; CHECK: $rax = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @G, $noreg
+ $rax = MOV64rm $rip, 1, _, target-flags(x86-gotpcrel) @G, _
+ $eax = MOV32rm $rax, 1, _, 0, _
+ $eax = INC32r $eax, implicit-def $eflags
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/immediate-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/immediate-operands.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/immediate-operands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/immediate-operands.mir Wed Jan 31 14:04:26 2018
@@ -19,18 +19,18 @@
name: foo
body: |
bb.0.entry:
- ; CHECK: %eax = MOV32ri 42
- ; CHECK-NEXT: RETQ %eax
- %eax = MOV32ri 42
- RETQ %eax
+ ; CHECK: $eax = MOV32ri 42
+ ; CHECK-NEXT: RETQ $eax
+ $eax = MOV32ri 42
+ RETQ $eax
...
---
# CHECK: name: bar
name: bar
body: |
bb.0.entry:
- ; CHECK: %eax = MOV32ri -11
- ; CHECK-NEXT: RETQ %eax
- %eax = MOV32ri -11
- RETQ %eax
+ ; CHECK: $eax = MOV32ri -11
+ ; CHECK-NEXT: RETQ $eax
+ $eax = MOV32ri -11
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/implicit-register-flag.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/implicit-register-flag.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/implicit-register-flag.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/implicit-register-flag.mir Wed Jan 31 14:04:26 2018
@@ -32,19 +32,19 @@ name: foo
body: |
bb.0.entry:
successors: %bb.1, %bb.2
- ; CHECK: CMP32ri8 %edi, 10, implicit-def %eflags
- ; CHECK-NEXT: JG_1 %bb.2, implicit %eflags
- CMP32ri8 %edi, 10, implicit-def %eflags
- JG_1 %bb.2, implicit %eflags
+ ; CHECK: CMP32ri8 $edi, 10, implicit-def $eflags
+ ; CHECK-NEXT: JG_1 %bb.2, implicit $eflags
+ CMP32ri8 $edi, 10, implicit-def $eflags
+ JG_1 %bb.2, implicit $eflags
bb.1.less:
- ; CHECK: %eax = MOV32r0 implicit-def %eflags
- %eax = MOV32r0 implicit-def %eflags
- RETQ %eax
+ ; CHECK: $eax = MOV32r0 implicit-def $eflags
+ $eax = MOV32r0 implicit-def $eflags
+ RETQ $eax
bb.2.exit:
- %eax = COPY %edi
- RETQ %eax
+ $eax = COPY $edi
+ RETQ $eax
...
---
name: implicit_subregister1
@@ -53,16 +53,16 @@ body: |
; Verify that the implicit register verifier won't report an error on implicit
; subregisters.
; CHECK-LABEL: name: implicit_subregister1
- ; CHECK: dead %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags, implicit-def %al
- dead %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags, implicit-def %al
- RETQ killed %al
+ ; CHECK: dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al
+ dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al
+ RETQ killed $al
...
---
name: implicit_subregister2
body: |
bb.0.entry:
; CHECK-LABEL: name: implicit_subregister2
- ; CHECK: dead %r15 = XOR64rr undef %r15, undef %r15, implicit-def dead %eflags, implicit-def %r15w
- dead %r15 = XOR64rr undef %r15, undef %r15, implicit-def dead %eflags, implicit-def %r15w
- RETQ killed %r15w
+ ; CHECK: dead $r15 = XOR64rr undef $r15, undef $r15, implicit-def dead $eflags, implicit-def $r15w
+ dead $r15 = XOR64rr undef $r15, undef $r15, implicit-def dead $eflags, implicit-def $r15w
+ RETQ killed $r15w
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/inline-asm-registers.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/inline-asm-registers.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/inline-asm-registers.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/inline-asm-registers.mir Wed Jan 31 14:04:26 2018
@@ -21,32 +21,32 @@
name: test
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
- - { reg: '%rsi' }
+ - { reg: '$rdi' }
+ - { reg: '$rsi' }
body: |
bb.0.entry:
- liveins: %rdi, %rsi
+ liveins: $rdi, $rsi
; CHECK-LABEL: name: test
- ; CHECK: INLINEASM &foo, 0, 2818058, def %rsi, 2818058, def dead %rdi,
- INLINEASM &foo, 0, 2818058, def %rsi, 2818058, def dead %rdi, 2147549193, killed %rdi, 2147483657, killed %rsi, 12, implicit-def dead early-clobber %eflags
- %rax = MOV64rr killed %rsi
- RETQ killed %rax
+ ; CHECK: INLINEASM &foo, 0, 2818058, def $rsi, 2818058, def dead $rdi,
+ INLINEASM &foo, 0, 2818058, def $rsi, 2818058, def dead $rdi, 2147549193, killed $rdi, 2147483657, killed $rsi, 12, implicit-def dead early-clobber $eflags
+ $rax = MOV64rr killed $rsi
+ RETQ killed $rax
...
---
name: test2
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
- - { reg: '%rsi' }
+ - { reg: '$rdi' }
+ - { reg: '$rsi' }
body: |
bb.0.entry:
- liveins: %rdi, %rsi
+ liveins: $rdi, $rsi
; Verify that the register ties are preserved.
; CHECK-LABEL: name: test2
- ; CHECK: INLINEASM &foo, 0, 2818058, def %rsi, 2818058, def dead %rdi, 2147549193, killed %rdi(tied-def 5), 2147483657, killed %rsi(tied-def 3), 12, implicit-def dead early-clobber %eflags
- INLINEASM &foo, 0, 2818058, def %rsi, 2818058, def dead %rdi, 2147549193, killed %rdi(tied-def 5), 2147483657, killed %rsi(tied-def 3), 12, implicit-def dead early-clobber %eflags
- %rax = MOV64rr killed %rsi
- RETQ killed %rax
+ ; CHECK: INLINEASM &foo, 0, 2818058, def $rsi, 2818058, def dead $rdi, 2147549193, killed $rdi(tied-def 5), 2147483657, killed $rsi(tied-def 3), 12, implicit-def dead early-clobber $eflags
+ INLINEASM &foo, 0, 2818058, def $rsi, 2818058, def dead $rdi, 2147549193, killed $rdi(tied-def 5), 2147483657, killed $rsi(tied-def 3), 12, implicit-def dead early-clobber $eflags
+ $rax = MOV64rr killed $rsi
+ RETQ killed $rax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/instructions-debug-location.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/instructions-debug-location.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/instructions-debug-location.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/instructions-debug-location.mir Wed Jan 31 14:04:26 2018
@@ -58,15 +58,15 @@ stack:
- { id: 0, name: x.addr, size: 4, alignment: 4 }
body: |
bb.0.entry:
- liveins: %edi
- ; CHECK: DBG_VALUE debug-use %noreg, 0, !11, !DIExpression(), debug-location !12
- ; CHECK: %eax = COPY %0, debug-location !13
- ; CHECK: RETQ %eax, debug-location !13
- %0 = COPY %edi
+ liveins: $edi
+ ; CHECK: DBG_VALUE debug-use $noreg, 0, !11, !DIExpression(), debug-location !12
+ ; CHECK: $eax = COPY %0, debug-location !13
+ ; CHECK: RETQ $eax, debug-location !13
+ %0 = COPY $edi
DBG_VALUE debug-use _, 0, !12, !DIExpression(), debug-location !13
MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
- %eax = COPY %0, debug-location !14
- RETQ %eax, debug-location !14
+ $eax = COPY %0, debug-location !14
+ RETQ $eax, debug-location !14
...
---
name: test_typed_immediates
@@ -79,16 +79,16 @@ stack:
- { id: 0, name: x.addr, size: 4, alignment: 4 }
body: |
bb.0.entry:
- liveins: %edi
+ liveins: $edi
- %0 = COPY %edi
- ; CHECK: DBG_VALUE %noreg, i32 0, !DIExpression(), !12
- ; CHECK-NEXT: DBG_VALUE %noreg, i64 -22, !DIExpression(), !12
- ; CHECK-NEXT: DBG_VALUE %noreg, i128 123492148938512984928424384934328985928, !DIExpression(), !12
+ %0 = COPY $edi
+ ; CHECK: DBG_VALUE $noreg, i32 0, !DIExpression(), !12
+ ; CHECK-NEXT: DBG_VALUE $noreg, i64 -22, !DIExpression(), !12
+ ; CHECK-NEXT: DBG_VALUE $noreg, i128 123492148938512984928424384934328985928, !DIExpression(), !12
DBG_VALUE _, i32 0, !DIExpression(), !13
DBG_VALUE _, i64 -22, !DIExpression(), !13
DBG_VALUE _, i128 123492148938512984928424384934328985928, !DIExpression(), !13
MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
- %eax = COPY %0
- RETQ %eax
+ $eax = COPY %0
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir Wed Jan 31 14:04:26 2018
@@ -19,7 +19,7 @@ constants:
body: |
bb.0.entry:
; CHECK: [[@LINE+1]]:47: use of undefined constant '%const.10'
- %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.10, _
- RETQ %xmm0
+ $xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.10, _
+ RETQ $xmm0
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/invalid-target-flag-name.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/invalid-target-flag-name.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/invalid-target-flag-name.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/invalid-target-flag-name.mir Wed Jan 31 14:04:26 2018
@@ -17,8 +17,8 @@ name: inc
body: |
bb.0.entry:
; CHECK: [[@LINE+1]]:45: use of undefined target flag 'x86-test'
- %rax = MOV64rm %rip, 1, _, target-flags(x86-test) @G, _
- %eax = MOV32rm killed %rax, 1, _, 0, _
- %eax = INC32r killed %eax, implicit-def dead %eflags
- RETQ %eax
+ $rax = MOV64rm $rip, 1, _, target-flags(x86-test) @G, _
+ $eax = MOV32rm killed $rax, 1, _, 0, _
+ $eax = INC32r killed $eax, implicit-def dead $eflags
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir Wed Jan 31 14:04:26 2018
@@ -12,13 +12,13 @@
name: test
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry:
- liveins: %rdi
+ liveins: $rdi
; CHECK: [[@LINE+1]]:58: use of invalid tied-def operand index '300'; instruction has only 6 operands
- INLINEASM &"$foo", 1, 2818058, def %rdi, 2147483657, killed %rdi(tied-def 300)
- %rax = COPY killed %rdi
- RETQ killed %rax
+ INLINEASM &"$foo", 1, 2818058, def $rdi, 2147483657, killed $rdi(tied-def 300)
+ $rax = COPY killed $rdi
+ RETQ killed $rax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/jump-table-info.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/jump-table-info.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/jump-table-info.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/jump-table-info.mir Wed Jan 31 14:04:26 2018
@@ -72,37 +72,37 @@ body: |
bb.0.entry:
successors: %bb.2, %bb.1
- %eax = MOV32rr %edi, implicit-def %rax
- CMP32ri8 %edi, 3, implicit-def %eflags
- JA_1 %bb.2, implicit %eflags
+ $eax = MOV32rr $edi, implicit-def $rax
+ CMP32ri8 $edi, 3, implicit-def $eflags
+ JA_1 %bb.2, implicit $eflags
bb.1.entry:
successors: %bb.3, %bb.4, %bb.5, %bb.6
- ; CHECK: %rcx = LEA64r %rip, 1, %noreg, %jump-table.0, %noreg
- %rcx = LEA64r %rip, 1, _, %jump-table.0, _
- %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _
- %rax = ADD64rr %rax, %rcx, implicit-def %eflags
- JMP64r %rax
+ ; CHECK: $rcx = LEA64r $rip, 1, $noreg, %jump-table.0, $noreg
+ $rcx = LEA64r $rip, 1, _, %jump-table.0, _
+ $rax = MOVSX64rm32 $rcx, 4, $rax, 0, _
+ $rax = ADD64rr $rax, $rcx, implicit-def $eflags
+ JMP64r $rax
bb.2.def:
- %eax = MOV32r0 implicit-def %eflags
- RETQ %eax
+ $eax = MOV32r0 implicit-def $eflags
+ RETQ $eax
bb.3.lbl1:
- %eax = MOV32ri 1
- RETQ %eax
+ $eax = MOV32ri 1
+ RETQ $eax
bb.4.lbl2:
- %eax = MOV32ri 2
- RETQ %eax
+ $eax = MOV32ri 2
+ RETQ $eax
bb.5.lbl3:
- %eax = MOV32ri 4
- RETQ %eax
+ $eax = MOV32ri 4
+ RETQ $eax
bb.6.lbl4:
- %eax = MOV32ri 8
- RETQ %eax
+ $eax = MOV32ri 8
+ RETQ $eax
...
---
name: test_jumptable2
@@ -115,36 +115,36 @@ body: |
bb.0.entry:
successors: %bb.2, %bb.1
- %eax = MOV32rr %edi, implicit-def %rax
- CMP32ri8 %edi, 3, implicit-def %eflags
- JA_1 %bb.2, implicit %eflags
+ $eax = MOV32rr $edi, implicit-def $rax
+ CMP32ri8 $edi, 3, implicit-def $eflags
+ JA_1 %bb.2, implicit $eflags
bb.1.entry:
successors: %bb.3, %bb.4, %bb.5, %bb.6
; Verify that the printer will use an id of 0 for this jump table:
- ; CHECK: %rcx = LEA64r %rip, 1, %noreg, %jump-table.0, %noreg
- %rcx = LEA64r %rip, 1, _, %jump-table.1, _
- %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _
- %rax = ADD64rr %rax, %rcx, implicit-def %eflags
- JMP64r %rax
+ ; CHECK: $rcx = LEA64r $rip, 1, $noreg, %jump-table.0, $noreg
+ $rcx = LEA64r $rip, 1, _, %jump-table.1, _
+ $rax = MOVSX64rm32 $rcx, 4, $rax, 0, _
+ $rax = ADD64rr $rax, $rcx, implicit-def $eflags
+ JMP64r $rax
bb.2.def:
- %eax = MOV32r0 implicit-def %eflags
- RETQ %eax
+ $eax = MOV32r0 implicit-def $eflags
+ RETQ $eax
bb.3.lbl1:
- %eax = MOV32ri 1
- RETQ %eax
+ $eax = MOV32ri 1
+ RETQ $eax
bb.4.lbl2:
- %eax = MOV32ri 2
- RETQ %eax
+ $eax = MOV32ri 2
+ RETQ $eax
bb.5.lbl3:
- %eax = MOV32ri 4
- RETQ %eax
+ $eax = MOV32ri 4
+ RETQ $eax
bb.6.lbl4:
- %eax = MOV32ri 8
- RETQ %eax
+ $eax = MOV32ri 8
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir Wed Jan 31 14:04:26 2018
@@ -42,35 +42,35 @@ body: |
bb.0.entry:
successors: %bb.2.def, %bb.1.entry
- %eax = MOV32rr %edi, implicit-def %rax
- CMP32ri8 %edi, 3, implicit-def %eflags
- JA_1 %bb.2.def, implicit %eflags
+ $eax = MOV32rr $edi, implicit-def $rax
+ CMP32ri8 $edi, 3, implicit-def $eflags
+ JA_1 %bb.2.def, implicit $eflags
bb.1.entry:
successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
- %rcx = LEA64r %rip, 1, _, %jump-table.0, _
- %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _
- %rax = ADD64rr %rax, %rcx, implicit-def %eflags
- JMP64r %rax
+ $rcx = LEA64r $rip, 1, _, %jump-table.0, _
+ $rax = MOVSX64rm32 $rcx, 4, $rax, 0, _
+ $rax = ADD64rr $rax, $rcx, implicit-def $eflags
+ JMP64r $rax
bb.2.def:
- %eax = MOV32r0 implicit-def %eflags
- RETQ %eax
+ $eax = MOV32r0 implicit-def $eflags
+ RETQ $eax
bb.3.lbl1:
- %eax = MOV32ri 1
- RETQ %eax
+ $eax = MOV32ri 1
+ RETQ $eax
bb.4.lbl2:
- %eax = MOV32ri 2
- RETQ %eax
+ $eax = MOV32ri 2
+ RETQ $eax
bb.5.lbl3:
- %eax = MOV32ri 4
- RETQ %eax
+ $eax = MOV32ri 4
+ RETQ $eax
bb.6.lbl4:
- %eax = MOV32ri 8
- RETQ %eax
+ $eax = MOV32ri 8
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/killed-register-flag.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/killed-register-flag.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/killed-register-flag.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/killed-register-flag.mir Wed Jan 31 14:04:26 2018
@@ -23,18 +23,18 @@ body: |
bb.0.entry:
successors: %bb.1.less, %bb.2.exit
- CMP32ri8 %edi, 10, implicit-def %eflags
- JG_1 %bb.2.exit, implicit %eflags
+ CMP32ri8 $edi, 10, implicit-def $eflags
+ JG_1 %bb.2.exit, implicit $eflags
bb.1.less:
- ; CHECK: %eax = MOV32r0
- ; CHECK-NEXT: RETQ killed %eax
- %eax = MOV32r0 implicit-def %eflags
- RETQ killed %eax
+ ; CHECK: $eax = MOV32r0
+ ; CHECK-NEXT: RETQ killed $eax
+ $eax = MOV32r0 implicit-def $eflags
+ RETQ killed $eax
bb.2.exit:
- ; CHECK: %eax = COPY killed %edi
- ; CHECK-NEXT: RETQ killed %eax
- %eax = COPY killed %edi
- RETQ killed %eax
+ ; CHECK: $eax = COPY killed $edi
+ ; CHECK-NEXT: RETQ killed $eax
+ $eax = COPY killed $edi
+ RETQ killed $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir Wed Jan 31 14:04:26 2018
@@ -18,10 +18,10 @@ stack:
- { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 }
body: |
bb.0.entry:
- %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags
+ $rsp = SUB64ri32 $rsp, 4040, implicit-def dead $eflags
; CHECK: [[@LINE+1]]:36: expected a 32 bit integer (the cfi offset is too large)
CFI_INSTRUCTION def_cfa_offset 123456789123456
- %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags
+ $rsp = ADD64ri32 $rsp, 4040, implicit-def dead $eflags
RETQ
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/large-immediate-operand-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/large-immediate-operand-error.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/large-immediate-operand-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/large-immediate-operand-error.mir Wed Jan 31 14:04:26 2018
@@ -13,6 +13,6 @@ name: foo
body: |
bb.0.entry:
; CHECK: [[@LINE+1]]:20: integer literal is too large to be an immediate operand
- %eax = MOV32ri 12346127502983478823754212949184914
- RETQ %eax
+ $eax = MOV32ri 12346127502983478823754212949184914
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/large-index-number-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/large-index-number-error.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/large-index-number-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/large-index-number-error.mir Wed Jan 31 14:04:26 2018
@@ -20,14 +20,14 @@
name: foo
body: |
bb.0.entry:
- %eax = MOV32rm %rdi, 1, _, 0, _
- CMP32ri8 %eax, 10, implicit-def %eflags
+ $eax = MOV32rm $rdi, 1, _, 0, _
+ CMP32ri8 $eax, 10, implicit-def $eflags
; CHECK: [[@LINE+1]]:10: expected 32-bit integer (too large)
- JG_1 %bb.123456789123456, implicit %eflags
+ JG_1 %bb.123456789123456, implicit $eflags
bb.1:
- %eax = MOV32r0 implicit-def %eflags
+ $eax = MOV32r0 implicit-def $eflags
bb.2:
- RETQ %eax
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/large-offset-number-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/large-offset-number-error.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/large-offset-number-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/large-offset-number-error.mir Wed Jan 31 14:04:26 2018
@@ -17,8 +17,8 @@ name: inc
body: |
bb.0.entry:
; CHECK: [[@LINE+1]]:37: expected 64-bit integer (too large)
- %rax = MOV64rm %rip, 1, _, @G + 123456789123456789123456789, _
- %eax = MOV32rm %rax, 1, _, 0, _
- %eax = INC32r %eax implicit-def %eflags
- RETQ %eax
+ $rax = MOV64rm $rip, 1, _, @G + 123456789123456789123456789, _
+ $eax = MOV32rm $rax, 1, _, 0, _
+ $eax = INC32r $eax implicit-def $eflags
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir Wed Jan 31 14:04:26 2018
@@ -13,12 +13,12 @@
name: test
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry:
- liveins: %rdi
+ liveins: $rdi
; CHECK: [[@LINE+1]]:53: expected 64-bit integer (too large)
- %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 12345678912345678924218574857 from %ir.a)
- RETQ %eax
+ $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load 12345678912345678924218574857 from %ir.a)
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/liveout-register-mask.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/liveout-register-mask.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/liveout-register-mask.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/liveout-register-mask.mir Wed Jan 31 14:04:26 2018
@@ -17,8 +17,8 @@
name: small_patchpoint_codegen
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
- - { reg: '%rsi' }
+ - { reg: '$rdi' }
+ - { reg: '$rsi' }
frameInfo:
hasPatchPoint: true
stackSize: 8
@@ -28,15 +28,15 @@ fixedStack:
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
body: |
bb.0.entry:
- liveins: %rdi, %rsi, %rbp
+ liveins: $rdi, $rsi, $rbp
- frame-setup PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp
+ frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 16
- CFI_INSTRUCTION offset %rbp, -16
- %rbp = frame-setup MOV64rr %rsp
- CFI_INSTRUCTION def_cfa_register %rbp
- ; CHECK: PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, liveout(%esp, %rsp, %sp, %spl),
- PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, liveout(%esp, %rsp, %sp, %spl), implicit-def dead early-clobber %r11, implicit-def %rsp, implicit-def dead %rax
- %rbp = POP64r implicit-def %rsp, implicit %rsp
+ CFI_INSTRUCTION offset $rbp, -16
+ $rbp = frame-setup MOV64rr $rsp
+ CFI_INSTRUCTION def_cfa_register $rbp
+ ; CHECK: PATCHPOINT 5, 5, 0, 2, 0, $rdi, $rsi, csr_64, liveout($esp, $rsp, $sp, $spl),
+ PATCHPOINT 5, 5, 0, 2, 0, $rdi, $rsi, csr_64, liveout($esp, $rsp, $sp, $spl), implicit-def dead early-clobber $r11, implicit-def $rsp, implicit-def dead $rax
+ $rbp = POP64r implicit-def $rsp, implicit $rsp
RETQ
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/machine-basic-block-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/machine-basic-block-operands.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/machine-basic-block-operands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/machine-basic-block-operands.mir Wed Jan 31 14:04:26 2018
@@ -38,18 +38,18 @@ body: |
bb.0.entry:
successors: %bb.1, %bb.2
- %eax = MOV32rm %rdi, 1, _, 0, _
- ; CHECK: CMP32ri8 %eax, 10
+ $eax = MOV32rm $rdi, 1, _, 0, _
+ ; CHECK: CMP32ri8 $eax, 10
; CHECK-NEXT: JG_1 %bb.2
- CMP32ri8 %eax, 10, implicit-def %eflags
- JG_1 %bb.2, implicit %eflags
+ CMP32ri8 $eax, 10, implicit-def $eflags
+ JG_1 %bb.2, implicit $eflags
; CHECK: bb.1.less:
bb.1.less:
- %eax = MOV32r0 implicit-def %eflags
+ $eax = MOV32r0 implicit-def $eflags
bb.2.exit:
- RETQ %eax
+ RETQ $eax
...
---
# CHECK: name: bar
@@ -59,15 +59,15 @@ body: |
bb.0.entry:
successors: %bb.1, %bb.3
- %eax = MOV32rm %rdi, 1, _, 0, _
- ; CHECK: CMP32ri8 %eax, 10
+ $eax = MOV32rm $rdi, 1, _, 0, _
+ ; CHECK: CMP32ri8 $eax, 10
; CHECK-NEXT: JG_1 %bb.2
- CMP32ri8 %eax, 10, implicit-def %eflags
- JG_1 %bb.3, implicit %eflags
+ CMP32ri8 $eax, 10, implicit-def $eflags
+ JG_1 %bb.3, implicit $eflags
bb.1:
- %eax = MOV32r0 implicit-def %eflags
+ $eax = MOV32r0 implicit-def $eflags
bb.3:
- RETQ %eax
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/machine-instructions.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/machine-instructions.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/machine-instructions.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/machine-instructions.mir Wed Jan 31 14:04:26 2018
@@ -18,6 +18,6 @@ body: |
bb.0.entry:
; CHECK: MOV32rr
; CHECK-NEXT: RETQ
- %eax = MOV32rr %eax
- RETQ %eax
+ $eax = MOV32rr $eax
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/machine-verifier.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/machine-verifier.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/machine-verifier.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/machine-verifier.mir Wed Jan 31 14:04:26 2018
@@ -14,7 +14,7 @@ name: inc
tracksRegLiveness: true
body: |
bb.0.entry:
- liveins: %edi
+ liveins: $edi
; CHECK: *** Bad machine code: Too few operands ***
; CHECK: instruction: COPY
; CHECK: 2 operands expected, but 0 given.
Modified: llvm/trunk/test/CodeGen/MIR/X86/memory-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/memory-operands.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/memory-operands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/memory-operands.mir Wed Jan 31 14:04:26 2018
@@ -194,151 +194,151 @@
name: test
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry:
- liveins: %rdi
- ; CHECK: %eax = MOV32rm %rdi, 1, %noreg, 0, %noreg :: (load 4 from %ir.a)
- ; CHECK-NEXT: MOV32mi killed %rdi, 1, %noreg, 0, %noreg, 42 :: (store 4 into %ir.a)
- %eax = MOV32rm %rdi, 1, _, 0, _ :: (load 4 from %ir.a)
- MOV32mi killed %rdi, 1, _, 0, _, 42 :: (store 4 into %ir.a)
- RETQ %eax
+ liveins: $rdi
+ ; CHECK: $eax = MOV32rm $rdi, 1, $noreg, 0, $noreg :: (load 4 from %ir.a)
+ ; CHECK-NEXT: MOV32mi killed $rdi, 1, $noreg, 0, $noreg, 42 :: (store 4 into %ir.a)
+ $eax = MOV32rm $rdi, 1, _, 0, _ :: (load 4 from %ir.a)
+ MOV32mi killed $rdi, 1, _, 0, _, 42 :: (store 4 into %ir.a)
+ RETQ $eax
...
---
name: test2
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry2:
- liveins: %rdi
- ; CHECK: INC32m killed %rdi, 1, %noreg, 0, %noreg, implicit-def dead %eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value")
- INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value")
+ liveins: $rdi
+ ; CHECK: INC32m killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value")
+ INC32m killed $rdi, 1, _, 0, _, implicit-def dead $eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value")
RETQ
...
---
name: test3
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
frameInfo:
maxAlignment: 4
stack:
- { id: 0, offset: -12, size: 4, alignment: 4 }
body: |
bb.0.entry3:
- liveins: %rdi
+ liveins: $rdi
; Verify that the unnamed local values can be serialized.
; CHECK-LABEL: name: test3
- ; CHECK: %eax = MOV32rm killed %rdi, 1, %noreg, 0, %noreg :: (load 4 from %ir.0)
- ; CHECK: MOV32mr %rsp, 1, %noreg, -4, %noreg, killed %eax :: (store 4 into %ir.1)
- %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.0)
- %eax = INC32r killed %eax, implicit-def dead %eflags
- MOV32mr %rsp, 1, _, -4, _, killed %eax :: (store 4 into %ir.1)
+ ; CHECK: $eax = MOV32rm killed $rdi, 1, $noreg, 0, $noreg :: (load 4 from %ir.0)
+ ; CHECK: MOV32mr $rsp, 1, $noreg, -4, $noreg, killed $eax :: (store 4 into %ir.1)
+ $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load 4 from %ir.0)
+ $eax = INC32r killed $eax, implicit-def dead $eflags
+ MOV32mr $rsp, 1, _, -4, _, killed $eax :: (store 4 into %ir.1)
RETQ
...
---
name: volatile_inc
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry:
- liveins: %rdi
+ liveins: $rdi
; CHECK: name: volatile_inc
- ; CHECK: %eax = MOV32rm %rdi, 1, %noreg, 0, %noreg :: (volatile load 4 from %ir.x)
- ; CHECK: MOV32mr killed %rdi, 1, %noreg, 0, %noreg, %eax :: (volatile store 4 into %ir.x)
- %eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile load 4 from %ir.x)
- %eax = INC32r killed %eax, implicit-def dead %eflags
- MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x)
- RETQ %eax
+ ; CHECK: $eax = MOV32rm $rdi, 1, $noreg, 0, $noreg :: (volatile load 4 from %ir.x)
+ ; CHECK: MOV32mr killed $rdi, 1, $noreg, 0, $noreg, $eax :: (volatile store 4 into %ir.x)
+ $eax = MOV32rm $rdi, 1, _, 0, _ :: (volatile load 4 from %ir.x)
+ $eax = INC32r killed $eax, implicit-def dead $eflags
+ MOV32mr killed $rdi, 1, _, 0, _, $eax :: (volatile store 4 into %ir.x)
+ RETQ $eax
...
---
name: non_temporal_store
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
- - { reg: '%esi' }
+ - { reg: '$rdi' }
+ - { reg: '$esi' }
body: |
bb.0.entry:
- liveins: %esi, %rdi
+ liveins: $esi, $rdi
; CHECK: name: non_temporal_store
- ; CHECK: MOVNTImr killed %rdi, 1, %noreg, 0, %noreg, killed %esi :: (non-temporal store 4 into %ir.a)
- MOVNTImr killed %rdi, 1, _, 0, _, killed %esi :: (non-temporal store 4 into %ir.a)
+ ; CHECK: MOVNTImr killed $rdi, 1, $noreg, 0, $noreg, killed $esi :: (non-temporal store 4 into %ir.a)
+ MOVNTImr killed $rdi, 1, _, 0, _, killed $esi :: (non-temporal store 4 into %ir.a)
RETQ
...
---
name: invariant_load
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry:
- liveins: %rdi
+ liveins: $rdi
; CHECK: name: invariant_load
- ; CHECK: %eax = MOV32rm killed %rdi, 1, %noreg, 0, %noreg :: (invariant load 4 from %ir.x)
- %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (invariant load 4 from %ir.x)
- RETQ %eax
+ ; CHECK: $eax = MOV32rm killed $rdi, 1, $noreg, 0, $noreg :: (invariant load 4 from %ir.x)
+ $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (invariant load 4 from %ir.x)
+ RETQ $eax
...
---
name: memory_offset
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry:
- liveins: %rdi
+ liveins: $rdi
; CHECK: name: memory_offset
- ; CHECK: %xmm0 = MOVAPSrm %rdi, 1, %noreg, 0, %noreg :: (load 16 from %ir.vec)
- ; CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, %noreg, 16, %noreg :: (load 16 from %ir.vec + 16)
- ; CHECK: MOVAPSmr %rdi, 1, %noreg, 0, %noreg, killed %xmm0 :: (store 16 into %ir.vec)
- ; CHECK-NEXT: MOVAPSmr killed %rdi, 1, %noreg, 16, %noreg, killed %xmm1 :: (store 16 into %ir.vec + 16)
- %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec)
- %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16)
- %xmm2 = FsFLD0SS
- %xmm1 = MOVSSrr killed %xmm1, killed %xmm2
- MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec)
- MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16)
+ ; CHECK: $xmm0 = MOVAPSrm $rdi, 1, $noreg, 0, $noreg :: (load 16 from %ir.vec)
+ ; CHECK-NEXT: $xmm1 = MOVAPSrm $rdi, 1, $noreg, 16, $noreg :: (load 16 from %ir.vec + 16)
+ ; CHECK: MOVAPSmr $rdi, 1, $noreg, 0, $noreg, killed $xmm0 :: (store 16 into %ir.vec)
+ ; CHECK-NEXT: MOVAPSmr killed $rdi, 1, $noreg, 16, $noreg, killed $xmm1 :: (store 16 into %ir.vec + 16)
+ $xmm0 = MOVAPSrm $rdi, 1, _, 0, _ :: (load 16 from %ir.vec)
+ $xmm1 = MOVAPSrm $rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16)
+ $xmm2 = FsFLD0SS
+ $xmm1 = MOVSSrr killed $xmm1, killed $xmm2
+ MOVAPSmr $rdi, 1, _, 0, _, killed $xmm0 :: (store 16 into %ir.vec)
+ MOVAPSmr killed $rdi, 1, _, 16, _, killed $xmm1 :: (store 16 into %ir.vec + 16)
RETQ
...
---
name: memory_alignment
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry:
- liveins: %rdi
+ liveins: $rdi
; CHECK: name: memory_alignment
- ; CHECK: %xmm0 = MOVAPSrm %rdi, 1, %noreg, 0, %noreg :: (load 16 from %ir.vec, align 32)
- ; CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, %noreg, 16, %noreg :: (load 16 from %ir.vec + 16, align 32)
- ; CHECK: MOVAPSmr %rdi, 1, %noreg, 0, %noreg, killed %xmm0 :: (store 16 into %ir.vec, align 32)
- ; CHECK-NEXT: MOVAPSmr killed %rdi, 1, %noreg, 16, %noreg, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)
- %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align 32)
- %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
- %xmm2 = FsFLD0SS
- %xmm1 = MOVSSrr killed %xmm1, killed %xmm2
- MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)
- MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)
+ ; CHECK: $xmm0 = MOVAPSrm $rdi, 1, $noreg, 0, $noreg :: (load 16 from %ir.vec, align 32)
+ ; CHECK-NEXT: $xmm1 = MOVAPSrm $rdi, 1, $noreg, 16, $noreg :: (load 16 from %ir.vec + 16, align 32)
+ ; CHECK: MOVAPSmr $rdi, 1, $noreg, 0, $noreg, killed $xmm0 :: (store 16 into %ir.vec, align 32)
+ ; CHECK-NEXT: MOVAPSmr killed $rdi, 1, $noreg, 16, $noreg, killed $xmm1 :: (store 16 into %ir.vec + 16, align 32)
+ $xmm0 = MOVAPSrm $rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align 32)
+ $xmm1 = MOVAPSrm $rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
+ $xmm2 = FsFLD0SS
+ $xmm1 = MOVSSrr killed $xmm1, killed $xmm2
+ MOVAPSmr $rdi, 1, _, 0, _, killed $xmm0 :: (store 16 into %ir.vec, align 32)
+ MOVAPSmr killed $rdi, 1, _, 16, _, killed $xmm1 :: (store 16 into %ir.vec + 16, align 32)
RETQ
...
---
name: constant_pool_psv
tracksRegLiveness: true
liveins:
- - { reg: '%xmm0' }
+ - { reg: '$xmm0' }
constants:
- id: 0
value: 'double 3.250000e+00'
body: |
bb.0.entry:
- liveins: %xmm0
+ liveins: $xmm0
; CHECK: name: constant_pool_psv
- ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.0, %noreg :: (load 8 from constant-pool)
- ; CHECK-NEXT: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.0, %noreg :: (load 8 from constant-pool + 8)
- %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool)
- %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool + 8)
- RETQ %xmm0
+ ; CHECK: $xmm0 = ADDSDrm killed $xmm0, $rip, 1, $noreg, %const.0, $noreg :: (load 8 from constant-pool)
+ ; CHECK-NEXT: $xmm0 = ADDSDrm killed $xmm0, $rip, 1, $noreg, %const.0, $noreg :: (load 8 from constant-pool + 8)
+ $xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.0, _ :: (load 8 from constant-pool)
+ $xmm0 = ADDSDrm killed $xmm0, $rip, 1, _, %const.0, _ :: (load 8 from constant-pool + 8)
+ RETQ $xmm0
...
---
name: stack_psv
@@ -353,14 +353,14 @@ fixedStack:
- { id: 0, offset: 0, size: 10, alignment: 16, isImmutable: true, isAliased: false }
body: |
bb.0.entry:
- %rsp = frame-setup SUB64ri8 %rsp, 24, implicit-def dead %eflags
+ $rsp = frame-setup SUB64ri8 $rsp, 24, implicit-def dead $eflags
CFI_INSTRUCTION def_cfa_offset 32
- LD_F80m %rsp, 1, %noreg, 32, %noreg, implicit-def dead %fpsw
+ LD_F80m $rsp, 1, $noreg, 32, $noreg, implicit-def dead $fpsw
; CHECK: name: stack_psv
- ; CHECK: ST_FP80m %rsp, 1, %noreg, 0, %noreg, implicit-def dead %fpsw :: (store 10 into stack, align 16)
- ST_FP80m %rsp, 1, _, 0, _, implicit-def dead %fpsw :: (store 10 into stack, align 16)
- CALL64pcrel32 &cosl, csr_64, implicit %rsp, implicit-def %rsp, implicit-def %fp0
- %rsp = ADD64ri8 %rsp, 24, implicit-def dead %eflags
+ ; CHECK: ST_FP80m $rsp, 1, $noreg, 0, $noreg, implicit-def dead $fpsw :: (store 10 into stack, align 16)
+ ST_FP80m $rsp, 1, _, 0, _, implicit-def dead $fpsw :: (store 10 into stack, align 16)
+ CALL64pcrel32 &cosl, csr_64, implicit $rsp, implicit-def $rsp, implicit-def $fp0
+ $rsp = ADD64ri8 $rsp, 24, implicit-def dead $eflags
RETQ
...
---
@@ -369,32 +369,32 @@ tracksRegLiveness: true
body: |
bb.0.entry:
; CHECK: name: got_psv
- ; CHECK: %rax = MOV64rm %rip, 1, %noreg, @G, %noreg :: (load 8 from got)
- %rax = MOV64rm %rip, 1, _, @G, _ :: (load 8 from got)
- %eax = MOV32rm killed %rax, 1, _, 0, _
- %eax = INC32r killed %eax, implicit-def dead %eflags
- RETQ %eax
+ ; CHECK: $rax = MOV64rm $rip, 1, $noreg, @G, $noreg :: (load 8 from got)
+ $rax = MOV64rm $rip, 1, _, @G, _ :: (load 8 from got)
+ $eax = MOV32rm killed $rax, 1, _, 0, _
+ $eax = INC32r killed $eax, implicit-def dead $eflags
+ RETQ $eax
...
---
name: global_value
tracksRegLiveness: true
body: |
bb.0.entry:
- %rax = MOV64rm %rip, 1, _, @G, _
+ $rax = MOV64rm $rip, 1, _, @G, _
; CHECK-LABEL: name: global_value
- ; CHECK: %eax = MOV32rm killed %rax, 1, %noreg, 0, %noreg, implicit-def %rax :: (load 4 from @G)
- ; CHECK: %ecx = MOV32rm killed %rcx, 1, %noreg, 0, %noreg, implicit-def %rcx :: (load 4 from @0)
- %eax = MOV32rm killed %rax, 1, _, 0, _, implicit-def %rax :: (load 4 from @G)
- %rcx = MOV64rm %rip, 1, _, @0, _
- %ecx = MOV32rm killed %rcx, 1, _, 0, _, implicit-def %rcx :: (load 4 from @0)
- %eax = LEA64_32r killed %rax, 1, killed %rcx, 1, _
- RETQ %eax
+ ; CHECK: $eax = MOV32rm killed $rax, 1, $noreg, 0, $noreg, implicit-def $rax :: (load 4 from @G)
+ ; CHECK: $ecx = MOV32rm killed $rcx, 1, $noreg, 0, $noreg, implicit-def $rcx :: (load 4 from @0)
+ $eax = MOV32rm killed $rax, 1, _, 0, _, implicit-def $rax :: (load 4 from @G)
+ $rcx = MOV64rm $rip, 1, _, @0, _
+ $ecx = MOV32rm killed $rcx, 1, _, 0, _, implicit-def $rcx :: (load 4 from @0)
+ $eax = LEA64_32r killed $rax, 1, killed $rcx, 1, _
+ RETQ $eax
...
---
name: jumptable_psv
tracksRegLiveness: true
liveins:
- - { reg: '%edi' }
+ - { reg: '$edi' }
jumpTable:
kind: label-difference32
entries:
@@ -403,100 +403,100 @@ jumpTable:
body: |
bb.0.entry:
successors: %bb.2.def, %bb.1.entry
- liveins: %edi
+ liveins: $edi
- %eax = MOV32rr %edi, implicit-def %rax
- CMP32ri8 killed %edi, 3, implicit-def %eflags
- JA_1 %bb.2.def, implicit killed %eflags
+ $eax = MOV32rr $edi, implicit-def $rax
+ CMP32ri8 killed $edi, 3, implicit-def $eflags
+ JA_1 %bb.2.def, implicit killed $eflags
bb.1.entry:
successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
- liveins: %rax
+ liveins: $rax
- %rcx = LEA64r %rip, 1, _, %jump-table.0, _
+ $rcx = LEA64r $rip, 1, _, %jump-table.0, _
; CHECK: name: jumptable_psv
- ; CHECK: %rax = MOVSX64rm32 %rcx, 4, killed %rax, 0, %noreg :: (load 4 from jump-table, align 8)
- %rax = MOVSX64rm32 %rcx, 4, killed %rax, 0, _ :: (load 4 from jump-table, align 8)
- %rax = ADD64rr killed %rax, killed %rcx, implicit-def dead %eflags
- JMP64r killed %rax
+ ; CHECK: $rax = MOVSX64rm32 $rcx, 4, killed $rax, 0, $noreg :: (load 4 from jump-table, align 8)
+ $rax = MOVSX64rm32 $rcx, 4, killed $rax, 0, _ :: (load 4 from jump-table, align 8)
+ $rax = ADD64rr killed $rax, killed $rcx, implicit-def dead $eflags
+ JMP64r killed $rax
bb.2.def:
- %eax = MOV32r0 implicit-def dead %eflags
- RETQ %eax
+ $eax = MOV32r0 implicit-def dead $eflags
+ RETQ $eax
bb.3.lbl1:
- %eax = MOV32ri 1
- RETQ %eax
+ $eax = MOV32ri 1
+ RETQ $eax
bb.4.lbl2:
- %eax = MOV32ri 2
- RETQ %eax
+ $eax = MOV32ri 2
+ RETQ $eax
bb.5.lbl3:
- %eax = MOV32ri 4
- RETQ %eax
+ $eax = MOV32ri 4
+ RETQ $eax
bb.6.lbl4:
- %eax = MOV32ri 8
- RETQ %eax
+ $eax = MOV32ri 8
+ RETQ $eax
...
---
name: tbaa_metadata
tracksRegLiveness: true
body: |
bb.0.entry:
- %rax = MOV64rm %rip, 1, _, @a, _ :: (load 8 from got)
+ $rax = MOV64rm $rip, 1, _, @a, _ :: (load 8 from got)
; CHECK-LABEL: name: tbaa_metadata
- ; CHECK: %eax = MOV32rm killed %rax, 1, %noreg, 0, %noreg, implicit-def %rax :: (load 4 from @a, !tbaa !2)
- ; CHECK-NEXT: %eax = MOV32rm killed %rax, 1, %noreg, 0, %noreg :: (load 4 from %ir.total_len2, !tbaa !6)
- %eax = MOV32rm killed %rax, 1, _, 0, _, implicit-def %rax :: (load 4 from @a, !tbaa !2)
- %eax = MOV32rm killed %rax, 1, _, 0, _ :: (load 4 from %ir.total_len2, !tbaa !6)
- RETQ %eax
+ ; CHECK: $eax = MOV32rm killed $rax, 1, $noreg, 0, $noreg, implicit-def $rax :: (load 4 from @a, !tbaa !2)
+ ; CHECK-NEXT: $eax = MOV32rm killed $rax, 1, $noreg, 0, $noreg :: (load 4 from %ir.total_len2, !tbaa !6)
+ $eax = MOV32rm killed $rax, 1, _, 0, _, implicit-def $rax :: (load 4 from @a, !tbaa !2)
+ $eax = MOV32rm killed $rax, 1, _, 0, _ :: (load 4 from %ir.total_len2, !tbaa !6)
+ RETQ $eax
...
---
name: aa_scope
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
- - { reg: '%rsi' }
+ - { reg: '$rdi' }
+ - { reg: '$rsi' }
body: |
bb.0.entry:
- liveins: %rdi, %rsi
+ liveins: $rdi, $rsi
; CHECK-LABEL: name: aa_scope
- ; CHECK: %xmm0 = MOVSSrm %rsi, 1, %noreg, 0, %noreg :: (load 4 from %ir.c, !alias.scope !9)
- %xmm0 = MOVSSrm %rsi, 1, _, 0, _ :: (load 4 from %ir.c, !alias.scope !9)
- ; CHECK-NEXT: MOVSSmr %rdi, 1, %noreg, 20, %noreg, killed %xmm0 :: (store 4 into %ir.arrayidx.i, !noalias !9)
- MOVSSmr %rdi, 1, _, 20, _, killed %xmm0 :: (store 4 into %ir.arrayidx.i, !noalias !9)
- %xmm0 = MOVSSrm killed %rsi, 1, _, 0, _ :: (load 4 from %ir.c)
- MOVSSmr killed %rdi, 1, _, 28, _, killed %xmm0 :: (store 4 into %ir.arrayidx)
+ ; CHECK: $xmm0 = MOVSSrm $rsi, 1, $noreg, 0, $noreg :: (load 4 from %ir.c, !alias.scope !9)
+ $xmm0 = MOVSSrm $rsi, 1, _, 0, _ :: (load 4 from %ir.c, !alias.scope !9)
+ ; CHECK-NEXT: MOVSSmr $rdi, 1, $noreg, 20, $noreg, killed $xmm0 :: (store 4 into %ir.arrayidx.i, !noalias !9)
+ MOVSSmr $rdi, 1, _, 20, _, killed $xmm0 :: (store 4 into %ir.arrayidx.i, !noalias !9)
+ $xmm0 = MOVSSrm killed $rsi, 1, _, 0, _ :: (load 4 from %ir.c)
+ MOVSSmr killed $rdi, 1, _, 28, _, killed $xmm0 :: (store 4 into %ir.arrayidx)
RETQ
...
---
name: range_metadata
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry:
- liveins: %rdi
+ liveins: $rdi
; CHECK-LABEL: name: range_metadata
- ; CHECK: %al = MOV8rm killed %rdi, 1, %noreg, 0, %noreg :: (load 1 from %ir.x, !range !11)
- %al = MOV8rm killed %rdi, 1, _, 0, _ :: (load 1 from %ir.x, !range !11)
- RETQ %al
+ ; CHECK: $al = MOV8rm killed $rdi, 1, $noreg, 0, $noreg :: (load 1 from %ir.x, !range !11)
+ $al = MOV8rm killed $rdi, 1, _, 0, _ :: (load 1 from %ir.x, !range !11)
+ RETQ $al
...
---
name: gep_value
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry:
- liveins: %rdi
+ liveins: $rdi
- %rax = MOV64rm %rip, 1, _, @values, _ :: (load 8 from got)
+ $rax = MOV64rm $rip, 1, _, @values, _ :: (load 8 from got)
; CHECK-LABEL: gep_value
- ; CHECK: MOV32mr killed %rax, 1, %noreg, 0, %noreg, %edi, implicit killed %rdi :: (store 4 into `i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0)`, align 16)
- MOV32mr killed %rax, 1, _, 0, _, %edi, implicit killed %rdi :: (store 4 into `i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0)`, align 16)
+ ; CHECK: MOV32mr killed $rax, 1, $noreg, 0, $noreg, $edi, implicit killed $rdi :: (store 4 into `i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0)`, align 16)
+ MOV32mr killed $rax, 1, _, 0, _, $edi, implicit killed $rdi :: (store 4 into `i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0)`, align 16)
RETQ
...
---
@@ -505,32 +505,32 @@ tracksRegLiveness: true
body: |
bb.0.entry:
; CHECK-LABEL: name: undef_value
- ; CHECK: %rax = MOV64rm undef %rax, 1, %noreg, 0, %noreg :: (load 8 from `i8** undef`)
- %rax = MOV64rm undef %rax, 1, _, 0, _ :: (load 8 from `i8** undef`)
- RETQ %rax
+ ; CHECK: $rax = MOV64rm undef $rax, 1, $noreg, 0, $noreg :: (load 8 from `i8** undef`)
+ $rax = MOV64rm undef $rax, 1, _, 0, _ :: (load 8 from `i8** undef`)
+ RETQ $rax
...
---
# Test memory operand without associated value.
# CHECK-LABEL: name: dummy0
-# CHECK: %rax = MOV64rm undef %rax, 1, %noreg, 0, %noreg :: (load 8)
+# CHECK: $rax = MOV64rm undef $rax, 1, $noreg, 0, $noreg :: (load 8)
name: dummy0
tracksRegLiveness: true
body: |
bb.0:
- %rax = MOV64rm undef %rax, 1, _, 0, _ :: (load 8)
- RETQ %rax
+ $rax = MOV64rm undef $rax, 1, _, 0, _ :: (load 8)
+ RETQ $rax
...
---
# Test parsing of stack references in machine memory operands.
# CHECK-LABEL: name: dummy1
-# CHECK: %rax = MOV64rm %rsp, 1, %noreg, 0, %noreg :: (load 8 from %stack.0)
+# CHECK: $rax = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)
name: dummy1
tracksRegLiveness: true
stack:
- { id: 0, size: 4, alignment: 4 }
body: |
bb.0:
- %rax = MOV64rm %rsp, 1, _, 0, _ :: (load 8 from %stack.0)
- RETQ %rax
+ $rax = MOV64rm $rsp, 1, _, 0, _ :: (load 8 from %stack.0)
+ RETQ $rax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/metadata-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/metadata-operands.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/metadata-operands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/metadata-operands.mir Wed Jan 31 14:04:26 2018
@@ -49,12 +49,12 @@ stack:
- { id: 0, name: x.addr, size: 4, alignment: 4 }
body: |
bb.0.entry:
- liveins: %edi
- ; CHECK: %0:gr32 = COPY %edi
- ; CHECK-NEXT: DBG_VALUE %noreg, 0, !11, !DIExpression()
- %0 = COPY %edi
+ liveins: $edi
+ ; CHECK: %0:gr32 = COPY $edi
+ ; CHECK-NEXT: DBG_VALUE $noreg, 0, !11, !DIExpression()
+ %0 = COPY $edi
DBG_VALUE _, 0, !12, !DIExpression()
MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
- %eax = COPY %0
- RETQ %eax
+ $eax = COPY %0
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/missing-closing-quote.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/missing-closing-quote.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/missing-closing-quote.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/missing-closing-quote.mir Wed Jan 31 14:04:26 2018
@@ -16,7 +16,7 @@ name: test
body: |
bb.0.entry:
; CHECK: [[@LINE+1]]:48: end of machine instruction reached before the closing '"'
- %rax = MOV64rm %rip, 1, _, @"quoted name, _
- %eax = MOV32rm killed %rax, 1, _, 0, _
- RETQ %eax
+ $rax = MOV64rm $rip, 1, _, @"quoted name, _
+ $eax = MOV32rm killed $rax, 1, _, 0, _
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/missing-comma.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/missing-comma.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/missing-comma.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/missing-comma.mir Wed Jan 31 14:04:26 2018
@@ -13,7 +13,7 @@ name: foo
body: |
bb.0.entry:
; CHECK: [[@LINE+1]]:25: expected ',' before the next machine operand
- %eax = XOR32rr %eax %eflags
- RETQ %eax
+ $eax = XOR32rr $eax $eflags
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/missing-implicit-operand.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/missing-implicit-operand.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/missing-implicit-operand.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/missing-implicit-operand.mir Wed Jan 31 14:04:26 2018
@@ -25,14 +25,14 @@ body: |
bb.0.entry:
successors: %bb.1.less, %bb.2.exit
- %eax = MOV32rm %rdi, 1, _, 0, _
- CMP32ri8 %eax, 10, implicit-def %eflags
+ $eax = MOV32rm $rdi, 1, _, 0, _
+ CMP32ri8 $eax, 10, implicit-def $eflags
; CHECK: [[@LINE+1]]:20: missing implicit register operand 'implicit %eflags'
JG_1 %bb.2.exit
bb.1.less:
- %eax = MOV32r0 implicit-def %eflags
+ $eax = MOV32r0 implicit-def $eflags
bb.2.exit:
- RETQ %eax
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/named-registers.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/named-registers.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/named-registers.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/named-registers.mir Wed Jan 31 14:04:26 2018
@@ -14,8 +14,8 @@
name: foo
body: |
bb.0.entry:
- ; CHECK: %eax = MOV32r0
- ; CHECK-NEXT: RETQ %eax
- %eax = MOV32r0 implicit-def %eflags
- RETQ %eax
+ ; CHECK: $eax = MOV32r0
+ ; CHECK-NEXT: RETQ $eax
+ $eax = MOV32r0 implicit-def $eflags
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/newline-handling.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/newline-handling.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/newline-handling.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/newline-handling.mir Wed Jan 31 14:04:26 2018
@@ -31,79 +31,79 @@
name: foo
tracksRegLiveness: true
liveins:
- - { reg: '%edi' }
+ - { reg: '$edi' }
# CHECK-LABEL: name: foo
# CHECK: body: |
# CHECK-NEXT: bb.0.entry:
# CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
-# CHECK-NEXT: liveins: %edi
-# CHECK: CMP32ri8 %edi, 10, implicit-def %eflags
-# CHECK-NEXT: JG_1 %bb.2, implicit killed %eflags
+# CHECK-NEXT: liveins: $edi
+# CHECK: CMP32ri8 $edi, 10, implicit-def $eflags
+# CHECK-NEXT: JG_1 %bb.2, implicit killed $eflags
# CHECK: bb.1.less:
-# CHECK-NEXT: %eax = MOV32r0 implicit-def dead %eflags
-# CHECK-NEXT: RETQ killed %eax
+# CHECK-NEXT: $eax = MOV32r0 implicit-def dead $eflags
+# CHECK-NEXT: RETQ killed $eax
# CHECK: bb.2.exit:
-# CHECK-NEXT: liveins: %edi
-# CHECK: %eax = COPY killed %edi
-# CHECK-NEXT: RETQ killed %eax
+# CHECK-NEXT: liveins: $edi
+# CHECK: $eax = COPY killed $edi
+# CHECK-NEXT: RETQ killed $eax
body: |
bb.0.entry:
successors: %bb.1, %bb.2
- liveins: %edi
+ liveins: $edi
- CMP32ri8 %edi, 10, implicit-def %eflags
+ CMP32ri8 $edi, 10, implicit-def $eflags
- JG_1 %bb.2, implicit killed %eflags
+ JG_1 %bb.2, implicit killed $eflags
bb.1.less:
- %eax = MOV32r0 implicit-def dead %eflags
- RETQ killed %eax
+ $eax = MOV32r0 implicit-def dead $eflags
+ RETQ killed $eax
bb.2.exit:
- liveins: %edi
- %eax = COPY killed %edi
- RETQ killed %eax
+ liveins: $edi
+ $eax = COPY killed $edi
+ RETQ killed $eax
...
---
name: bar
tracksRegLiveness: true
liveins:
- - { reg: '%edi' }
+ - { reg: '$edi' }
# CHECK-LABEL: name: bar
# CHECK: body: |
# CHECK-NEXT: bb.0.entry:
# CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
-# CHECK-NEXT: liveins: %edi
-# CHECK: CMP32ri8 %edi, 10, implicit-def %eflags
-# CHECK-NEXT: JG_1 %bb.2, implicit killed %eflags
+# CHECK-NEXT: liveins: $edi
+# CHECK: CMP32ri8 $edi, 10, implicit-def $eflags
+# CHECK-NEXT: JG_1 %bb.2, implicit killed $eflags
# CHECK: bb.1.less:
-# CHECK-NEXT: %eax = MOV32r0 implicit-def dead %eflags
-# CHECK-NEXT: RETQ killed %eax
+# CHECK-NEXT: $eax = MOV32r0 implicit-def dead $eflags
+# CHECK-NEXT: RETQ killed $eax
# CHECK: bb.2.exit:
-# CHECK-NEXT: liveins: %edi
-# CHECK: %eax = COPY killed %edi
-# CHECK-NEXT: RETQ killed %eax
+# CHECK-NEXT: liveins: $edi
+# CHECK: $eax = COPY killed $edi
+# CHECK-NEXT: RETQ killed $eax
body: |
bb.0.entry:
successors: %bb.1, %bb.2
- liveins: %edi
- CMP32ri8 %edi, 10, implicit-def %eflags
- JG_1 %bb.2, implicit killed %eflags
- bb.1.less: %eax = MOV32r0 implicit-def dead %eflags
- RETQ killed %eax
-
- bb.2.exit: liveins: %edi
- %eax = COPY killed %edi
- RETQ killed %eax
+ liveins: $edi
+ CMP32ri8 $edi, 10, implicit-def $eflags
+ JG_1 %bb.2, implicit killed $eflags
+ bb.1.less: $eax = MOV32r0 implicit-def dead $eflags
+ RETQ killed $eax
+
+ bb.2.exit: liveins: $edi
+ $eax = COPY killed $edi
+ RETQ killed $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/null-register-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/null-register-operands.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/null-register-operands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/null-register-operands.mir Wed Jan 31 14:04:26 2018
@@ -15,8 +15,8 @@
name: deref
body: |
bb.0.entry:
- ; CHECK: %eax = MOV32rm %rdi, 1, %noreg, 0, %noreg
- ; CHECK-NEXT: RETQ %eax
- %eax = MOV32rm %rdi, 1, _, 0, %noreg
- RETQ %eax
+ ; CHECK: $eax = MOV32rm $rdi, 1, $noreg, 0, $noreg
+ ; CHECK-NEXT: RETQ $eax
+ $eax = MOV32rm $rdi, 1, _, 0, $noreg
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/register-mask-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/register-mask-operands.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/register-mask-operands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/register-mask-operands.mir Wed Jan 31 14:04:26 2018
@@ -22,18 +22,18 @@
name: compute
body: |
bb.0.body:
- %eax = IMUL32rri8 %edi, 11, implicit-def %eflags
- RETQ %eax
+ $eax = IMUL32rri8 $edi, 11, implicit-def $eflags
+ RETQ $eax
...
---
# CHECK: name: foo
name: foo
body: |
bb.0.entry:
- ; CHECK: PUSH64r %rax
- ; CHECK-NEXT: CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
- PUSH64r %rax, implicit-def %rsp, implicit %rsp
- CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
- %rdx = POP64r implicit-def %rsp, implicit %rsp
- RETQ %eax
+ ; CHECK: PUSH64r $rax
+ ; CHECK-NEXT: CALL64pcrel32 @compute, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax
+ PUSH64r $rax, implicit-def $rsp, implicit $rsp
+ CALL64pcrel32 @compute, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax
+ $rdx = POP64r implicit-def $rsp, implicit $rsp
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir Wed Jan 31 14:04:26 2018
@@ -9,5 +9,5 @@ name: t
body: |
bb.0:
; CHECK: [[@LINE+1]]:10: register class specification expects a virtual register
- %eax : gr32 = COPY %rdx
+ $eax : gr32 = COPY $rdx
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/register-operand-class-invalid1.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/register-operand-class-invalid1.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/register-operand-class-invalid1.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/register-operand-class-invalid1.mir Wed Jan 31 14:04:26 2018
@@ -8,7 +8,7 @@
name: t
body: |
bb.0:
- %0 : gr32 = COPY %rdx
+ %0 : gr32 = COPY $rdx
; CHECK: [[@LINE+1]]:24: conflicting register classes, previously: GR32
NOOP implicit %0 : gr32_abcd
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/register-operand-class.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/register-operand-class.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/register-operand-class.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/register-operand-class.mir Wed Jan 31 14:04:26 2018
@@ -14,14 +14,14 @@
name: func
body: |
bb.0:
- %0 : gr32 = COPY %rax
- %1.sub_32bit : gr64 = COPY %eax
- %rdx = COPY %1
- %2 = COPY %ecx
- %ecx = COPY %2 : gr32
+ %0 : gr32 = COPY $rax
+ %1.sub_32bit : gr64 = COPY $eax
+ $rdx = COPY %1
+ %2 = COPY $ecx
+ $ecx = COPY %2 : gr32
- %3 : gr16 = COPY %bx
- %bx = COPY %3 : gr16
+ %3 : gr16 = COPY $bx
+ $bx = COPY %3 : gr16
- %4 : _(s32) = COPY %edx
+ %4 : _(s32) = COPY $edx
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir Wed Jan 31 14:04:26 2018
@@ -17,8 +17,8 @@ name: inc
body: |
bb.0.entry:
; CHECK: [[@LINE+1]]:42: register operands can't have target flags
- %rax = MOV64rm target-flags(x86-got) %rip, 1, _, @G, _
- %eax = MOV32rm killed %rax, 1, _, 0, _
- %eax = INC32r killed %eax, implicit-def dead %eflags
- RETQ %eax
+ $rax = MOV64rm target-flags(x86-got) $rip, 1, _, @G, _
+ $eax = MOV32rm killed $rax, 1, _, 0, _
+ $eax = INC32r killed $eax, implicit-def dead $eflags
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/renamable-register-flag.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/renamable-register-flag.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/renamable-register-flag.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/renamable-register-flag.mir Wed Jan 31 14:04:26 2018
@@ -10,7 +10,7 @@ name: foo
body: |
; CHECK: bb.0:
bb.0:
- ; CHECK: renamable %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags
- renamable %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags
- RETQ %eax
+ ; CHECK: renamable $eax = IMUL32rri8 $edi, 11, implicit-def dead $eflags
+ renamable $eax = IMUL32rri8 $edi, 11, implicit-def dead $eflags
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/roundtrip.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/roundtrip.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/roundtrip.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/roundtrip.mir Wed Jan 31 14:04:26 2018
@@ -6,15 +6,15 @@
# CHECK: - { id: 1, class: gr32, preferred-register: '' }
# CHECK: body: |
# CHECK: bb.0:
-# CHECK: %0:gr32 = MOV32r0 implicit-def %eflags
+# CHECK: %0:gr32 = MOV32r0 implicit-def $eflags
# CHECK: dead %1:gr32 = COPY %0
-# CHECK: MOV32mr undef %rcx, 1, %noreg, 0, %noreg, killed %0 :: (volatile store 4)
-# CHECK: RETQ undef %eax
+# CHECK: MOV32mr undef $rcx, 1, $noreg, 0, $noreg, killed %0 :: (volatile store 4)
+# CHECK: RETQ undef $eax
name: func0
body: |
bb.0:
- %0 : gr32 = MOV32r0 implicit-def %eflags
+ %0 : gr32 = MOV32r0 implicit-def $eflags
dead %1 : gr32 = COPY %0
- MOV32mr undef %rcx, 1, _, 0, _, killed %0 :: (volatile store 4)
- RETQ undef %eax
+ MOV32mr undef $rcx, 1, _, 0, _, killed %0 :: (volatile store 4)
+ RETQ undef $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir Wed Jan 31 14:04:26 2018
@@ -16,19 +16,19 @@ name: test
tracksRegLiveness: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '%esi' }
-# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '%edi' }
+# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '$esi' }
+# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '$edi' }
registers:
- { id: 0, class: gr32 }
- - { id: 1, class: gr32, preferred-register: '%esi' }
- - { id: 2, class: gr32, preferred-register: '%edi' }
+ - { id: 1, class: gr32, preferred-register: '$esi' }
+ - { id: 2, class: gr32, preferred-register: '$edi' }
body: |
bb.0.body:
- liveins: %edi, %esi
+ liveins: $edi, $esi
- %1 = COPY %esi
- %2 = COPY %edi
- %2 = IMUL32rr %2, %1, implicit-def dead %eflags
- %eax = COPY %2
- RETQ killed %eax
+ %1 = COPY $esi
+ %2 = COPY $edi
+ %2 = IMUL32rr %2, %1, implicit-def dead $eflags
+ $eax = COPY %2
+ RETQ killed $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir Wed Jan 31 14:04:26 2018
@@ -27,7 +27,7 @@ stack:
- { id: 0, offset: -12, size: 4, alignment: 4 }
body: |
bb.0.entry:
- MOV32mr %rsp, 1, _, -4, _, %edi
- %eax = COPY %edi
- RETQ %eax
+ MOV32mr $rsp, 1, _, -4, _, $edi
+ $eax = COPY $edi
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/stack-object-invalid-name.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/stack-object-invalid-name.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/stack-object-invalid-name.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/stack-object-invalid-name.mir Wed Jan 31 14:04:26 2018
@@ -22,7 +22,7 @@ stack:
- { id: 0, name: x, offset: -12, size: 4, alignment: 4 }
body: |
bb.0.entry:
- MOV32mr %rsp, 1, _, -4, _, %edi
- %eax = MOV32rm %rsp, 1, _, -4, _
- RETQ %eax
+ MOV32mr $rsp, 1, _, -4, _, $edi
+ $eax = MOV32rm $rsp, 1, _, -4, _
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir Wed Jan 31 14:04:26 2018
@@ -24,9 +24,9 @@ stack:
- { id: 0, name: b, size: 4, alignment: 4 }
body: |
bb.0.entry:
- %0 = COPY %edi
+ %0 = COPY $edi
; CHECK: [[@LINE+1]]:13: the name of the stack object '%stack.0' isn't 'x'
MOV32mr %stack.0.x, 1, _, 0, _, %0
- %eax = COPY %0
- RETQ %eax
+ $eax = COPY %0
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/stack-object-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/stack-object-operands.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/stack-object-operands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/stack-object-operands.mir Wed Jan 31 14:04:26 2018
@@ -32,16 +32,16 @@ stack:
body: |
bb.0.entry:
; CHECK-LABEL: name: test
- ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, %noreg, 0, %noreg
- ; CHECK: MOV32mr %stack.0.b, 1, %noreg, 0, %noreg, [[MOV32rm]]
- ; CHECK: MOV32mi %stack.1, 1, %noreg, 0, %noreg, 2
- ; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %stack.0.b, 1, %noreg, 0, %noreg
- ; CHECK: %eax = COPY [[MOV32rm1]]
- ; CHECK: RETL %eax
+ ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg
+ ; CHECK: MOV32mr %stack.0.b, 1, $noreg, 0, $noreg, [[MOV32rm]]
+ ; CHECK: MOV32mi %stack.1, 1, $noreg, 0, $noreg, 2
+ ; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %stack.0.b, 1, $noreg, 0, $noreg
+ ; CHECK: $eax = COPY [[MOV32rm1]]
+ ; CHECK: RETL $eax
%0 = MOV32rm %fixed-stack.0, 1, _, 0, _
MOV32mr %stack.0.b, 1, _, 0, _, %0
MOV32mi %stack.1, 1, _, 0, _, 2
%1 = MOV32rm %stack.0, 1, _, 0, _
- %eax = COPY %1
- RETL %eax
+ $eax = COPY %1
+ RETL $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir Wed Jan 31 14:04:26 2018
@@ -19,7 +19,7 @@
name: test
tracksRegLiveness: true
liveins:
- - { reg: '%edi' }
+ - { reg: '$edi' }
frameInfo:
maxAlignment: 8
stack:
@@ -28,10 +28,10 @@ stack:
- { id: 0, name: x, offset: -24, size: 8, alignment: 8 }
body: |
bb.0.entry:
- liveins: %edi
+ liveins: $edi
- MOV32mr %rsp, 1, _, -4, _, killed %edi
- MOV64mi32 %rsp, 1, _, -16, _, 2
- %eax = MOV32rm %rsp, 1, _, -4, _
- RETQ %eax
+ MOV32mr $rsp, 1, _, -4, _, killed $edi
+ MOV64mi32 $rsp, 1, _, -16, _, 2
+ $eax = MOV32rm $rsp, 1, _, -4, _
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/stack-objects.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/stack-objects.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/stack-objects.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/stack-objects.mir Wed Jan 31 14:04:26 2018
@@ -36,8 +36,8 @@ stack:
- { id: 2, type: spill-slot, offset: -32, size: 4, alignment: 4 }
body: |
bb.0.entry:
- MOV32mr %rsp, 1, _, -4, _, %edi
- MOV64mi32 %rsp, 1, _, -16, _, 2
- %eax = MOV32rm %rsp, 1, _, -4, _
- RETQ %eax
+ MOV32mr $rsp, 1, _, -4, _, $edi
+ MOV64mi32 $rsp, 1, _, -16, _, 2
+ $eax = MOV32rm $rsp, 1, _, -4, _
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/standalone-register-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/standalone-register-error.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/standalone-register-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/standalone-register-error.mir Wed Jan 31 14:04:26 2018
@@ -12,12 +12,12 @@ registers:
- { id: 0, class: gr32 }
liveins:
# CHECK: [[@LINE+1]]:13: unknown register name 'register'
- - { reg: '%register', virtual-reg: '%0' }
+ - { reg: '$register', virtual-reg: '%0' }
body: |
bb.0.body:
- liveins: %edi
+ liveins: $edi
- %0 = COPY %edi
- %eax = COPY %0
- RETQ %eax
+ %0 = COPY $edi
+ $eax = COPY %0
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/subreg-on-physreg.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/subreg-on-physreg.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/subreg-on-physreg.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/subreg-on-physreg.mir Wed Jan 31 14:04:26 2018
@@ -8,5 +8,5 @@ name: t
body: |
bb.0:
; CHECK: [[@LINE+1]]:19: subregister index expects a virtual register
- %eax.sub_8bit = COPY %bl
+ $eax.sub_8bit = COPY $bl
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/subregister-index-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/subregister-index-operands.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/subregister-index-operands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/subregister-index-operands.mir Wed Jan 31 14:04:26 2018
@@ -19,16 +19,16 @@ registers:
- { id: 1, class: gr8 }
body: |
bb.0.entry:
- liveins: %edi, %eax
+ liveins: $edi, $eax
; CHECK-LABEL: name: t
- ; CHECK: liveins: %edi, %eax
- ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG %edi, %al, %subreg.sub_8bit
- ; CHECK: [[EXTRACT_SUBREG:%[0-9]+]]:gr8 = EXTRACT_SUBREG %eax, %subreg.sub_8bit_hi
- ; CHECK: %ax = REG_SEQUENCE [[EXTRACT_SUBREG]], %subreg.sub_8bit, [[EXTRACT_SUBREG]], %subreg.sub_8bit_hi
- ; CHECK: RETQ %ax
- %0 = INSERT_SUBREG %edi, %al, %subreg.sub_8bit
- %1 = EXTRACT_SUBREG %eax, %subreg.sub_8bit_hi
- %ax = REG_SEQUENCE %1, %subreg.sub_8bit, %1, %subreg.sub_8bit_hi
- RETQ %ax
+ ; CHECK: liveins: $edi, $eax
+ ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG $edi, $al, %subreg.sub_8bit
+ ; CHECK: [[EXTRACT_SUBREG:%[0-9]+]]:gr8 = EXTRACT_SUBREG $eax, %subreg.sub_8bit_hi
+ ; CHECK: $ax = REG_SEQUENCE [[EXTRACT_SUBREG]], %subreg.sub_8bit, [[EXTRACT_SUBREG]], %subreg.sub_8bit_hi
+ ; CHECK: RETQ $ax
+ %0 = INSERT_SUBREG $edi, $al, %subreg.sub_8bit
+ %1 = EXTRACT_SUBREG $eax, %subreg.sub_8bit_hi
+ $ax = REG_SEQUENCE %1, %subreg.sub_8bit, %1, %subreg.sub_8bit_hi
+ RETQ $ax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir Wed Jan 31 14:04:26 2018
@@ -20,18 +20,18 @@ registers:
- { id: 2, class: gr8 }
body: |
bb.0.entry:
- liveins: %edi
+ liveins: $edi
; CHECK-LABEL: name: t
- ; CHECK: liveins: %edi
- ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+ ; CHECK: liveins: $edi
+ ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
- ; CHECK: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY1]], 1, implicit-def %eflags
- ; CHECK: %al = COPY [[AND8ri]]
- ; CHECK: RETQ %al
- %0 = COPY %edi
+ ; CHECK: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY1]], 1, implicit-def $eflags
+ ; CHECK: $al = COPY [[AND8ri]]
+ ; CHECK: RETQ $al
+ %0 = COPY $edi
%1 = COPY %0.sub_8bit
- %2 = AND8ri %1, 1, implicit-def %eflags
- %al = COPY %2
- RETQ %al
+ %2 = AND8ri %1, 1, implicit-def $eflags
+ $al = COPY %2
+ RETQ $al
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir Wed Jan 31 14:04:26 2018
@@ -25,18 +25,18 @@ body: |
; CHECK-LABEL: bb.1.less:
bb.0.entry:
successors: %bb.1 (33), %bb.2(67)
- liveins: %edi
+ liveins: $edi
- CMP32ri8 %edi, 10, implicit-def %eflags
- JG_1 %bb.2, implicit killed %eflags
+ CMP32ri8 $edi, 10, implicit-def $eflags
+ JG_1 %bb.2, implicit killed $eflags
bb.1.less:
- %eax = MOV32r0 implicit-def dead %eflags
- RETQ killed %eax
+ $eax = MOV32r0 implicit-def dead $eflags
+ RETQ killed $eax
bb.2.exit:
- liveins: %edi
+ liveins: $edi
- %eax = COPY killed %edi
- RETQ killed %eax
+ $eax = COPY killed $edi
+ RETQ killed $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks.mir Wed Jan 31 14:04:26 2018
@@ -35,20 +35,20 @@ body: |
; CHECK-LABEL: bb.1.less:
bb.0.entry:
successors: %bb.1.less, %bb.2.exit
- liveins: %edi
+ liveins: $edi
- CMP32ri8 %edi, 10, implicit-def %eflags
- JG_1 %bb.2.exit, implicit killed %eflags
+ CMP32ri8 $edi, 10, implicit-def $eflags
+ JG_1 %bb.2.exit, implicit killed $eflags
bb.1.less:
- %eax = MOV32r0 implicit-def dead %eflags
- RETQ killed %eax
+ $eax = MOV32r0 implicit-def dead $eflags
+ RETQ killed $eax
bb.2.exit:
- liveins: %edi
+ liveins: $edi
- %eax = COPY killed %edi
- RETQ killed %eax
+ $eax = COPY killed $edi
+ RETQ killed $eax
...
---
name: bar
@@ -59,24 +59,24 @@ body: |
; CHECK-LABEL: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000), %bb.2(0x00000000)
bb.0.entry:
- liveins: %edi
+ liveins: $edi
successors: %bb.1
successors: %bb.2
- CMP32ri8 %edi, 10, implicit-def %eflags
- JG_1 %bb.2, implicit killed %eflags
+ CMP32ri8 $edi, 10, implicit-def $eflags
+ JG_1 %bb.2, implicit killed $eflags
; Verify that we can have an empty list of successors.
; CHECK-LABEL: bb.1:
- ; CHECK-NEXT: %eax = MOV32r0 implicit-def dead %eflags
+ ; CHECK-NEXT: $eax = MOV32r0 implicit-def dead $eflags
bb.1:
successors:
- %eax = MOV32r0 implicit-def dead %eflags
- RETQ killed %eax
+ $eax = MOV32r0 implicit-def dead $eflags
+ RETQ killed $eax
bb.2:
- liveins: %edi
+ liveins: $edi
- %eax = COPY killed %edi
- RETQ killed %eax
+ $eax = COPY killed $edi
+ RETQ killed $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir Wed Jan 31 14:04:26 2018
@@ -12,13 +12,13 @@
name: test
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry:
- liveins: %rdi
+ liveins: $rdi
; CHECK: [[@LINE+1]]:58: use of invalid tied-def operand index '0'; the operand #0 isn't a defined register
- INLINEASM &"$foo", 1, 2818058, def %rdi, 2147483657, killed %rdi(tied-def 0)
- %rax = COPY killed %rdi
- RETQ killed %rax
+ INLINEASM &"$foo", 1, 2818058, def $rdi, 2147483657, killed $rdi(tied-def 0)
+ $rax = COPY killed $rdi
+ RETQ killed $rax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/tied-physical-regs-match.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/tied-physical-regs-match.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/tied-physical-regs-match.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/tied-physical-regs-match.mir Wed Jan 31 14:04:26 2018
@@ -14,9 +14,9 @@
name: foo
body: |
bb.0.entry:
- liveins: %rdi
+ liveins: $rdi
; CHECK: Tied physical registers must match.
- %rbx = AND64rm killed %rdx, killed %rdi, 1, _, 0, _, implicit-def dead %eflags
- RETQ %rbx
+ $rbx = AND64rm killed $rdx, killed $rdi, 1, _, 0, _, implicit-def dead $eflags
+ RETQ $rbx
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/undef-register-flag.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undef-register-flag.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/undef-register-flag.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/undef-register-flag.mir Wed Jan 31 14:04:26 2018
@@ -23,16 +23,16 @@
name: compute
body: |
bb.0.body:
- %eax = IMUL32rri8 %edi, 11, implicit-def %eflags
- RETQ %eax
+ $eax = IMUL32rri8 $edi, 11, implicit-def $eflags
+ RETQ $eax
...
---
name: foo
body: |
bb.0.entry:
- ; CHECK: PUSH64r undef %rax
- PUSH64r undef %rax, implicit-def %rsp, implicit %rsp
- CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
- %rdx = POP64r implicit-def %rsp, implicit %rsp
- RETQ %eax
+ ; CHECK: PUSH64r undef $rax
+ PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
+ CALL64pcrel32 @compute, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax
+ $rdx = POP64r implicit-def $rsp, implicit $rsp
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir Wed Jan 31 14:04:26 2018
@@ -32,6 +32,6 @@ body: |
MOV32mr %stack.0, 1, _, 0, _, %0
MOV32mi %stack.1, 1, _, 0, _, 2
%1 = MOV32rm %stack.0, 1, _, 0, _
- %eax = COPY %1
- RETL %eax
+ $eax = COPY %1
+ RETL $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/undefined-global-value.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-global-value.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/undefined-global-value.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/undefined-global-value.mir Wed Jan 31 14:04:26 2018
@@ -19,8 +19,8 @@ name: inc
body: |
bb.0.entry:
; CHECK: [[@LINE+1]]:32: use of undefined global value '@2'
- %rax = MOV64rm %rip, 1, _, @2, _
- %eax = MOV32rm %rax, 1, _, 0, _
- %eax = INC32r %eax
- RETQ %eax
+ $rax = MOV64rm $rip, 1, _, @2, _
+ $eax = MOV32rm $rax, 1, _, 0, _
+ $eax = INC32r $eax
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir Wed Jan 31 14:04:26 2018
@@ -21,9 +21,9 @@ body: |
bb.0.entry:
successors: %bb.1.block
; CHECK: [[@LINE+1]]:51: use of undefined IR block '%ir-block."block "'
- %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block."block "), _
- MOV64mr %rip, 1, _, @addr, _, killed %rax
- JMP64m %rip, 1, _, @addr, _
+ $rax = LEA64r $rip, 1, _, blockaddress(@test, %ir-block."block "), _
+ MOV64mr $rip, 1, _, @addr, _, killed $rax
+ JMP64m $rip, 1, _, @addr, _
bb.1.block (address-taken):
RETQ
Modified: llvm/trunk/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir Wed Jan 31 14:04:26 2018
@@ -20,9 +20,9 @@ body: |
bb.0.entry:
successors: %bb.1
; CHECK: [[@LINE+1]]:51: use of undefined IR block '%ir-block.1'
- %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.1), _
- MOV64mr %rip, 1, _, @addr, _, killed %rax
- JMP64m %rip, 1, _, @addr, _
+ $rax = LEA64r $rip, 1, _, blockaddress(@test, %ir-block.1), _
+ MOV64mr $rip, 1, _, @addr, _, killed $rax
+ JMP64m $rip, 1, _, @addr, _
bb.1 (address-taken):
RETQ
Modified: llvm/trunk/test/CodeGen/MIR/X86/undefined-jump-table-id.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-jump-table-id.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/undefined-jump-table-id.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/undefined-jump-table-id.mir Wed Jan 31 14:04:26 2018
@@ -39,35 +39,35 @@ body: |
bb.0.entry:
successors: %bb.2.def, %bb.1.entry
- %eax = MOV32rr %edi, implicit-def %rax
- CMP32ri8 %edi, 3, implicit-def %eflags
- JA_1 %bb.2.def, implicit %eflags
+ $eax = MOV32rr $edi, implicit-def $rax
+ CMP32ri8 $edi, 3, implicit-def $eflags
+ JA_1 %bb.2.def, implicit $eflags
bb.1.entry:
successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
; CHECK: [[@LINE+1]]:31: use of undefined jump table '%jump-table.2'
- %rcx = LEA64r %rip, 1, _, %jump-table.2, _
- %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _
- %rax = ADD64rr %rax, %rcx, implicit-def %eflags
- JMP64r %rax
+ $rcx = LEA64r $rip, 1, _, %jump-table.2, _
+ $rax = MOVSX64rm32 $rcx, 4, $rax, 0, _
+ $rax = ADD64rr $rax, $rcx, implicit-def $eflags
+ JMP64r $rax
bb.2.def:
- %eax = MOV32r0 implicit-def %eflags
- RETQ %eax
+ $eax = MOV32r0 implicit-def $eflags
+ RETQ $eax
bb.3.lbl1:
- %eax = MOV32ri 1
- RETQ %eax
+ $eax = MOV32ri 1
+ RETQ $eax
bb.4.lbl2:
- %eax = MOV32ri 2
- RETQ %eax
+ $eax = MOV32ri 2
+ RETQ $eax
bb.5.lbl3:
- %eax = MOV32ri 4
- RETQ %eax
+ $eax = MOV32ri 4
+ RETQ $eax
bb.6.lbl4:
- %eax = MOV32ri 8
- RETQ %eax
+ $eax = MOV32ri 8
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/undefined-named-global-value.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-named-global-value.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/undefined-named-global-value.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/undefined-named-global-value.mir Wed Jan 31 14:04:26 2018
@@ -19,8 +19,8 @@ name: inc
body: |
bb.0.entry:
; CHECK: [[@LINE+1]]:32: use of undefined global value '@GG'
- %rax = MOV64rm %rip, 1, _, @GG, _
- %eax = MOV32rm %rax, 1, _, 0, _
- %eax = INC32r %eax
- RETQ %eax
+ $rax = MOV64rm $rip, 1, _, @GG, _
+ $eax = MOV32rm $rax, 1, _, 0, _
+ $eax = INC32r $eax
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/undefined-stack-object.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-stack-object.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/undefined-stack-object.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/undefined-stack-object.mir Wed Jan 31 14:04:26 2018
@@ -21,9 +21,9 @@ stack:
- { id: 0, name: b, size: 4, alignment: 4 }
body: |
bb.0.entry:
- %0 = COPY %edi
+ %0 = COPY $edi
; CHECK: [[@LINE+1]]:13: use of undefined stack object '%stack.2'
MOV32mr %stack.2, 1, _, 0, _, %0
- %eax = COPY %0
- RETQ %eax
+ $eax = COPY %0
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir Wed Jan 31 14:04:26 2018
@@ -13,12 +13,12 @@
name: test
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry:
- liveins: %rdi
+ liveins: $rdi
; CHECK: [[@LINE+1]]:60: use of undefined IR value '%ir.c'
- %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.c)
- RETQ %eax
+ $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load 4 from %ir.c)
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/undefined-virtual-register.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-virtual-register.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/undefined-virtual-register.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/undefined-virtual-register.mir Wed Jan 31 14:04:26 2018
@@ -17,9 +17,9 @@ registers:
- { id: 0, class: gr32 }
body: |
bb.0.entry:
- %0 = COPY %edi
+ %0 = COPY $edi
; CHECK: Cannot determine class/bank of virtual register 1 in function 'test'
- %eax = COPY %1
- RETQ %eax
+ $eax = COPY %1
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/unexpected-type-phys.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unexpected-type-phys.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/unexpected-type-phys.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/unexpected-type-phys.mir Wed Jan 31 14:04:26 2018
@@ -7,7 +7,7 @@ name: test_size_physreg
registers:
body: |
bb.0.entry:
- liveins: %edi
+ liveins: $edi
; CHECK: [[@LINE+1]]:10: unexpected type on physical register
- %edi(s32) = G_ADD i32 %edi, %edi
+ $edi(s32) = G_ADD i32 $edi, $edi
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir Wed Jan 31 14:04:26 2018
@@ -23,14 +23,14 @@
name: foo
body: |
bb.0.entry:
- %eax = MOV32rm %rdi, 1, _, 0, _
- CMP32ri8 %eax, 10, implicit-def %eflags
+ $eax = MOV32rm $rdi, 1, _, 0, _
+ CMP32ri8 $eax, 10, implicit-def $eflags
; CHECK: [[@LINE+1]]:10: use of undefined machine basic block #4
- JG_1 %bb.4, implicit %eflags
+ JG_1 %bb.4, implicit $eflags
bb.1:
- %eax = MOV32r0 implicit-def %eflags
+ $eax = MOV32r0 implicit-def $eflags
bb.2:
- RETQ %eax
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir Wed Jan 31 14:04:26 2018
@@ -13,13 +13,13 @@
name: inc
tracksRegLiveness: true
liveins:
- - { reg: '%rdi' }
+ - { reg: '$rdi' }
body: |
bb.0.entry:
- liveins: %rdi
+ liveins: $rdi
; CHECK: [[@LINE+1]]:60: use of unknown metadata keyword '!tba'
- %eax = MOV32rm %rdi, 1, _, 0, _ :: (load 4 from %ir.x, !tba !0)
- %eax = INC32r killed %eax, implicit-def dead %eflags
- MOV32mr killed %rdi, 1, _, 0, _, %eax :: (store 4 into %ir.x)
- RETQ %eax
+ $eax = MOV32rm $rdi, 1, _, 0, _ :: (load 4 from %ir.x, !tba !0)
+ $eax = INC32r killed $eax, implicit-def dead $eflags
+ MOV32mr killed $rdi, 1, _, 0, _, $eax :: (store 4 into %ir.x)
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/unknown-metadata-node.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-metadata-node.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/unknown-metadata-node.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/unknown-metadata-node.mir Wed Jan 31 14:04:26 2018
@@ -48,10 +48,10 @@ stack:
- { id: 0, name: x.addr, size: 4, alignment: 4 }
body: |
bb.0.entry:
- %0 = COPY %edi
+ %0 = COPY $edi
; CHECK: [[@LINE+1]]:21: use of undefined metadata '!42'
DBG_VALUE _, 0, !42, !13
MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
- %eax = COPY %0
- RETQ %eax
+ $eax = COPY %0
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir Wed Jan 31 14:04:26 2018
@@ -22,14 +22,14 @@
name: foo
body: |
bb.0.entry:
- %eax = MOV32rm %rdi, 1, _, 0, _
- CMP32ri8 %eax, 10, implicit-def %eflags
+ $eax = MOV32rm $rdi, 1, _, 0, _
+ CMP32ri8 $eax, 10, implicit-def $eflags
; CHECK: [[@LINE+1]]:10: the name of machine basic block #2 isn't 'hit'
- JG_1 %bb.2.hit, implicit %eflags
+ JG_1 %bb.2.hit, implicit $eflags
bb.1.less:
- %eax = MOV32r0 implicit-def %eflags
+ $eax = MOV32r0 implicit-def $eflags
bb.2.exit:
- RETQ %eax
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/unknown-register.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-register.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/unknown-register.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/unknown-register.mir Wed Jan 31 14:04:26 2018
@@ -15,6 +15,6 @@ name: foo
body: |
bb.0.entry:
; CHECK: [[@LINE+1]]:5: unknown register name 'xax'
- %xax = MOV32r0
- RETQ %xax
+ $xax = MOV32r0
+ RETQ $xax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir Wed Jan 31 14:04:26 2018
@@ -20,6 +20,6 @@ registers:
body: |
bb.0.entry:
; CHECK: [[@LINE+1]]:35: unknown subregister index 'bit8'
- %0 = INSERT_SUBREG %edi, %al, %subreg.bit8
+ %0 = INSERT_SUBREG $edi, $al, %subreg.bit8
RETQ %0
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir Wed Jan 31 14:04:26 2018
@@ -19,10 +19,10 @@ registers:
- { id: 2, class: gr8 }
body: |
bb.0.entry:
- %0 = COPY %edi
+ %0 = COPY $edi
; CHECK: [[@LINE+1]]:18: use of unknown subregister index 'bit8'
%1 = COPY %0.bit8
- %2 = AND8ri %1, 1, implicit-def %eflags
- %al = COPY %2
- RETQ %al
+ %2 = AND8ri %1, 1, implicit-def $eflags
+ $al = COPY %2
+ RETQ $al
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir Wed Jan 31 14:04:26 2018
@@ -37,8 +37,8 @@ stack:
- { id: 2, name: y, type: variable-sized, offset: -32, alignment: 1 }
body: |
bb.0.entry:
- MOV32mr %rsp, 1, _, -4, _, %edi
- MOV64mi32 %rsp, 1, _, -16, _, 2
- %eax = MOV32rm %rsp, 1, _, -4, _
- RETQ %eax
+ MOV32mr $rsp, 1, _, -4, _, $edi
+ MOV64mi32 $rsp, 1, _, -16, _, 2
+ $eax = MOV32rm $rsp, 1, _, -4, _
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/MIR/X86/virtual-registers.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/virtual-registers.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/virtual-registers.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/virtual-registers.mir Wed Jan 31 14:04:26 2018
@@ -43,24 +43,24 @@ registers:
body: |
bb.0.entry:
successors: %bb.2.exit, %bb.1.less
- liveins: %edi
- ; CHECK: %0:gr32 = COPY %edi
+ liveins: $edi
+ ; CHECK: %0:gr32 = COPY $edi
; CHECK-NEXT: %1:gr32 = SUB32ri8 %0, 10
- %0 = COPY %edi
- %1 = SUB32ri8 %0, 10, implicit-def %eflags
- JG_1 %bb.2.exit, implicit %eflags
+ %0 = COPY $edi
+ %1 = SUB32ri8 %0, 10, implicit-def $eflags
+ JG_1 %bb.2.exit, implicit $eflags
JMP_1 %bb.1.less
bb.1.less:
; CHECK: %2:gr32 = MOV32r0
- ; CHECK-NEXT: %eax = COPY %2
- %2 = MOV32r0 implicit-def %eflags
- %eax = COPY %2
- RETQ %eax
+ ; CHECK-NEXT: $eax = COPY %2
+ %2 = MOV32r0 implicit-def $eflags
+ $eax = COPY %2
+ RETQ $eax
bb.2.exit:
- %eax = COPY %0
- RETQ %eax
+ $eax = COPY %0
+ RETQ $eax
...
---
name: foo
@@ -77,23 +77,23 @@ registers:
body: |
bb.0.entry:
successors: %bb.2.exit, %bb.1.less
- liveins: %edi
- ; CHECK: %0:gr32 = COPY %edi
+ liveins: $edi
+ ; CHECK: %0:gr32 = COPY $edi
; CHECK-NEXT: %1:gr32 = SUB32ri8 %0, 10
- %2 = COPY %edi
- %0 = SUB32ri8 %2, 10, implicit-def %eflags
- JG_1 %bb.2.exit, implicit %eflags
+ %2 = COPY $edi
+ %0 = SUB32ri8 %2, 10, implicit-def $eflags
+ JG_1 %bb.2.exit, implicit $eflags
JMP_1 %bb.1.less
bb.1.less:
; CHECK: %2:gr32 = MOV32r0
- ; CHECK-NEXT: %eax = COPY %2
- %10 = MOV32r0 implicit-def %eflags
- %eax = COPY %10
- RETQ %eax
+ ; CHECK-NEXT: $eax = COPY %2
+ %10 = MOV32r0 implicit-def $eflags
+ $eax = COPY %10
+ RETQ $eax
bb.2.exit:
- ; CHECK: %eax = COPY %0
- %eax = COPY %2
- RETQ %eax
+ ; CHECK: $eax = COPY %0
+ $eax = COPY %2
+ RETQ $eax
...
Modified: llvm/trunk/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir Wed Jan 31 14:04:26 2018
@@ -62,17 +62,17 @@ regBankSelected: false
selected: false
tracksRegLiveness: true
liveins:
- - { reg: '%a0_64' }
- - { reg: '%t9_64' }
-calleeSavedRegisters: [ '%fp', '%gp', '%ra', '%d12', '%d13', '%d14', '%d15',
- '%f24', '%f25', '%f26', '%f27', '%f28', '%f29',
- '%f30', '%f31', '%fp_64', '%f_hi24', '%f_hi25',
- '%f_hi26', '%f_hi27', '%f_hi28', '%f_hi29', '%f_hi30',
- '%f_hi31', '%gp_64', '%ra_64', '%s0', '%s1', '%s2',
- '%s3', '%s4', '%s5', '%s6', '%s7', '%d24_64', '%d25_64',
- '%d26_64', '%d27_64', '%d28_64', '%d29_64', '%d30_64',
- '%d31_64', '%s0_64', '%s1_64', '%s2_64', '%s3_64',
- '%s4_64', '%s5_64', '%s6_64', '%s7_64' ]
+ - { reg: '$a0_64' }
+ - { reg: '$t9_64' }
+calleeSavedRegisters: [ '$fp', '$gp', '$ra', '$d12', '$d13', '$d14', '$d15',
+ '$f24', '$f25', '$f26', '$f27', '$f28', '$f29',
+ '$f30', '$f31', '$fp_64', '$f_hi24', '$f_hi25',
+ '$f_hi26', '$f_hi27', '$f_hi28', '$f_hi29', '$f_hi30',
+ '$f_hi31', '$gp_64', '$ra_64', '$s0', '$s1', '$s2',
+ '$s3', '$s4', '$s5', '$s6', '$s7', '$d24_64', '$d25_64',
+ '$d26_64', '$d27_64', '$d28_64', '$d29_64', '$d30_64',
+ '$d31_64', '$s0_64', '$s1_64', '$s2_64', '$s3_64',
+ '$s4_64', '$s5_64', '$s6_64', '$s7_64' ]
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -90,69 +90,69 @@ frameInfo:
stack:
- { id: 0, name: retval, offset: -28, size: 4, alignment: 4 }
- { id: 1, name: a.addr, offset: -32, size: 4, alignment: 4 }
- - { id: 2, type: spill-slot, offset: -8, size: 8, alignment: 8, callee-saved-register: '%ra_64' }
- - { id: 3, type: spill-slot, offset: -16, size: 8, alignment: 8, callee-saved-register: '%fp_64' }
- - { id: 4, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '%gp_64' }
+ - { id: 2, type: spill-slot, offset: -8, size: 8, alignment: 8, callee-saved-register: '$ra_64' }
+ - { id: 3, type: spill-slot, offset: -16, size: 8, alignment: 8, callee-saved-register: '$fp_64' }
+ - { id: 4, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '$gp_64' }
body: |
bb.0.entry:
successors: %bb.1.if.then(0x40000000), %bb.5.if.else(0x40000000)
- liveins: %a0_64, %t9_64, %ra_64, %fp_64, %gp_64
+ liveins: $a0_64, $t9_64, $ra_64, $fp_64, $gp_64
- %sp_64 = DADDiu %sp_64, -32
+ $sp_64 = DADDiu $sp_64, -32
CFI_INSTRUCTION def_cfa_offset 32
- SD killed %ra_64, %sp_64, 24 :: (store 8 into %stack.2)
- SD killed %fp_64, %sp_64, 16 :: (store 8 into %stack.3)
- SD killed %gp_64, %sp_64, 8 :: (store 8 into %stack.4)
- CFI_INSTRUCTION offset %ra_64, -8
- CFI_INSTRUCTION offset %fp_64, -16
- CFI_INSTRUCTION offset %gp_64, -24
- CFI_INSTRUCTION def_cfa_register %fp_64
- %at_64 = LUi64 @f
- %v0_64 = DADDu killed %at_64, %t9_64
- SW %a0, %sp_64, 0 :: (store 4 into %ir.a.addr)
- BGTZC %a0, %bb.5.if.else, implicit-def %at
+ SD killed $ra_64, $sp_64, 24 :: (store 8 into %stack.2)
+ SD killed $fp_64, $sp_64, 16 :: (store 8 into %stack.3)
+ SD killed $gp_64, $sp_64, 8 :: (store 8 into %stack.4)
+ CFI_INSTRUCTION offset $ra_64, -8
+ CFI_INSTRUCTION offset $fp_64, -16
+ CFI_INSTRUCTION offset $gp_64, -24
+ CFI_INSTRUCTION def_cfa_register $fp_64
+ $at_64 = LUi64 @f
+ $v0_64 = DADDu killed $at_64, $t9_64
+ SW $a0, $sp_64, 0 :: (store 4 into %ir.a.addr)
+ BGTZC $a0, %bb.5.if.else, implicit-def $at
bb.1.if.then:
successors: %bb.6.return(0x40000000), %bb.2.if.then(0x40000000)
- liveins: %a0
+ liveins: $a0
- BLTZC %a0, %bb.6.return, implicit-def %at
+ BLTZC $a0, %bb.6.return, implicit-def $at
bb.2.if.then:
successors: %bb.3.if.else(0x80000000)
- %t8 = IMPLICIT_DEF
+ $t8 = IMPLICIT_DEF
bb.3.if.else:
successors: %bb.6.return(0x40000000), %bb.4.if.else(0x40000000)
- liveins: %t8
+ liveins: $t8
- BLEZC %t8, %bb.6.return, implicit-def %at
+ BLEZC $t8, %bb.6.return, implicit-def $at
bb.4.if.else:
successors: %bb.6.return(0x80000000)
- liveins: %t8
+ liveins: $t8
- %at = LW %sp_64, 0 :: (dereferenceable load 4 from %ir.a.addr)
- %at = ADDu killed %at, %t8
- SW killed %at, %sp_64, 4 :: (store 4 into %ir.retval)
- J %bb.6.return, implicit-def dead %at
+ $at = LW $sp_64, 0 :: (dereferenceable load 4 from %ir.a.addr)
+ $at = ADDu killed $at, $t8
+ SW killed $at, $sp_64, 4 :: (store 4 into %ir.retval)
+ J %bb.6.return, implicit-def dead $at
bb.5.if.else:
successors: %bb.6.return(0x80000000)
- liveins: %v0_64
+ liveins: $v0_64
- %gp_64 = DADDiu killed %v0_64, @f
- %a0_64 = LW64 %sp_64, 0 :: (dereferenceable load 4 from %ir.a.addr)
- %t9_64 = LD %gp_64, @g :: (load 8 from call-entry @g)
- JALR64Pseudo %t9_64, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0
- SW killed %v0, %sp_64, 4 :: (store 4 into %ir.retval)
+ $gp_64 = DADDiu killed $v0_64, @f
+ $a0_64 = LW64 $sp_64, 0 :: (dereferenceable load 4 from %ir.a.addr)
+ $t9_64 = LD $gp_64, @g :: (load 8 from call-entry @g)
+ JALR64Pseudo $t9_64, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0
+ SW killed $v0, $sp_64, 4 :: (store 4 into %ir.retval)
bb.6.return:
- %v0 = LW %sp_64, 4 :: (dereferenceable load 4 from %ir.retval)
- %gp_64 = LD %sp_64, 8 :: (load 8 from %stack.4)
- %fp_64 = LD %sp_64, 16 :: (load 8 from %stack.3)
- %ra_64 = LD %sp_64, 24 :: (load 8 from %stack.2)
- %sp_64 = DADDiu %sp_64, 32
- PseudoReturn64 %ra_64
+ $v0 = LW $sp_64, 4 :: (dereferenceable load 4 from %ir.retval)
+ $gp_64 = LD $sp_64, 8 :: (load 8 from %stack.4)
+ $fp_64 = LD $sp_64, 16 :: (load 8 from %stack.3)
+ $ra_64 = LD $sp_64, 24 :: (load 8 from %stack.2)
+ $sp_64 = DADDiu $sp_64, 32
+ PseudoReturn64 $ra_64
...
Modified: llvm/trunk/test/CodeGen/Mips/compactbranches/empty-block.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/compactbranches/empty-block.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/compactbranches/empty-block.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/compactbranches/empty-block.mir Wed Jan 31 14:04:26 2018
@@ -58,18 +58,18 @@ frameInfo:
hasVAStart: false
hasMustTailInVarArgFunc: false
stack:
- - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%ra' }
+ - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '$ra' }
body: |
bb.0.entry:
successors: %bb.1.if.then(0x50000000), %bb.4.if.end(0x30000000)
- liveins: %ra
+ liveins: $ra
- %sp = ADDiu %sp, -24
+ $sp = ADDiu $sp, -24
CFI_INSTRUCTION def_cfa_offset 24
- SW killed %ra, %sp, 20 :: (store 4 into %stack.0)
- CFI_INSTRUCTION offset %ra_64, -4
- JAL @k, csr_o32_fp64, implicit-def dead %ra, implicit-def %sp, implicit-def %v0
- BLEZ %v0, %bb.4.if.end, implicit-def %at
+ SW killed $ra, $sp, 20 :: (store 4 into %stack.0)
+ CFI_INSTRUCTION offset $ra_64, -4
+ JAL @k, csr_o32_fp64, implicit-def dead $ra, implicit-def $sp, implicit-def $v0
+ BLEZ $v0, %bb.4.if.end, implicit-def $at
bb.1.if.then:
successors: %bb.2.if.then(0x80000000)
@@ -80,12 +80,12 @@ body: |
bb.3.if.then:
successors: %bb.4.if.end(0x80000000)
- %a0 = ADDiu %zero, 2
- JAL @f, csr_o32_fp64, implicit-def dead %ra, implicit killed %a0, implicit-def %sp
+ $a0 = ADDiu $zero, 2
+ JAL @f, csr_o32_fp64, implicit-def dead $ra, implicit killed $a0, implicit-def $sp
bb.4.if.end:
- %ra = LW %sp, 20 :: (load 4 from %stack.0)
- %sp = ADDiu %sp, 24
- PseudoReturn undef %ra
+ $ra = LW $sp, 20 :: (load 4 from %stack.0)
+ $sp = ADDiu $sp, 24
+ PseudoReturn undef $ra
...
Modified: llvm/trunk/test/CodeGen/Mips/instverify/dext-pos.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dext-pos.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dext-pos.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dext-pos.mir Wed Jan 31 14:04:26 2018
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DEXT %0, 55, 10
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
Modified: llvm/trunk/test/CodeGen/Mips/instverify/dext-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dext-size.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dext-size.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dext-size.mir Wed Jan 31 14:04:26 2018
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DEXT %0, 5, 50
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
Modified: llvm/trunk/test/CodeGen/Mips/instverify/dextm-pos-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dextm-pos-size.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dextm-pos-size.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dextm-pos-size.mir Wed Jan 31 14:04:26 2018
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DEXTM %0, 3, 62
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
Modified: llvm/trunk/test/CodeGen/Mips/instverify/dextm-pos.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dextm-pos.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dextm-pos.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dextm-pos.mir Wed Jan 31 14:04:26 2018
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DEXTM %0, 65, 5
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
Modified: llvm/trunk/test/CodeGen/Mips/instverify/dextm-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dextm-size.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dextm-size.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dextm-size.mir Wed Jan 31 14:04:26 2018
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DEXTM %0, 31, 67
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
Modified: llvm/trunk/test/CodeGen/Mips/instverify/dextu-pos-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dextu-pos-size.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dextu-pos-size.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dextu-pos-size.mir Wed Jan 31 14:04:26 2018
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DEXTU %0, 43, 30
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
Modified: llvm/trunk/test/CodeGen/Mips/instverify/dextu-pos.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dextu-pos.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dextu-pos.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dextu-pos.mir Wed Jan 31 14:04:26 2018
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DEXTU %0, 64, 5
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
Modified: llvm/trunk/test/CodeGen/Mips/instverify/dextu-size-valid.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dextu-size-valid.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dextu-size-valid.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dextu-size-valid.mir Wed Jan 31 14:04:26 2018
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DEXTU %0, 63, 1
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
Modified: llvm/trunk/test/CodeGen/Mips/instverify/dextu-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dextu-size.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dextu-size.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dextu-size.mir Wed Jan 31 14:04:26 2018
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DEXTU %0, 33, 67
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
Modified: llvm/trunk/test/CodeGen/Mips/instverify/dins-pos-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dins-pos-size.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dins-pos-size.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dins-pos-size.mir Wed Jan 31 14:04:26 2018
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DINS %0, 17, 17
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
Modified: llvm/trunk/test/CodeGen/Mips/instverify/dins-pos.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dins-pos.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dins-pos.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dins-pos.mir Wed Jan 31 14:04:26 2018
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DINS %0, 55, 10
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
Modified: llvm/trunk/test/CodeGen/Mips/instverify/dins-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dins-size.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dins-size.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dins-size.mir Wed Jan 31 14:04:26 2018
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DINS %0, 5, 50
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
Modified: llvm/trunk/test/CodeGen/Mips/instverify/dinsm-pos-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dinsm-pos-size.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dinsm-pos-size.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dinsm-pos-size.mir Wed Jan 31 14:04:26 2018
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DINSM %0, 20, 50
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
Modified: llvm/trunk/test/CodeGen/Mips/instverify/dinsm-pos.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dinsm-pos.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dinsm-pos.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dinsm-pos.mir Wed Jan 31 14:04:26 2018
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DINSM %0, 65, 5
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
Modified: llvm/trunk/test/CodeGen/Mips/instverify/dinsm-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dinsm-size.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dinsm-size.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dinsm-size.mir Wed Jan 31 14:04:26 2018
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DINSM %0, 31, 67
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
Modified: llvm/trunk/test/CodeGen/Mips/instverify/dinsu-pos-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dinsu-pos-size.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dinsu-pos-size.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dinsu-pos-size.mir Wed Jan 31 14:04:26 2018
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DINSU %0, 50, 20
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
Modified: llvm/trunk/test/CodeGen/Mips/instverify/dinsu-pos.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dinsu-pos.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dinsu-pos.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dinsu-pos.mir Wed Jan 31 14:04:26 2018
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DINSU %0, 65, 5
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
Modified: llvm/trunk/test/CodeGen/Mips/instverify/dinsu-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/dinsu-size.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/dinsu-size.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/instverify/dinsu-size.mir Wed Jan 31 14:04:26 2018
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0_64
+ liveins: $a0_64
- %0 = COPY %a0_64
+ %0 = COPY $a0_64
%1 = DINSU %0, 33, 67
- %v0_64 = COPY %1
- RetRA implicit %v0_64
+ $v0_64 = COPY %1
+ RetRA implicit $v0_64
...
Modified: llvm/trunk/test/CodeGen/Mips/instverify/ext-pos-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/ext-pos-size.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/ext-pos-size.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/instverify/ext-pos-size.mir Wed Jan 31 14:04:26 2018
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr32, preferred-register: '' }
- { id: 1, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '%a0', virtual-reg: '%0' }
+ - { reg: '$a0', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0
+ liveins: $a0
- %0 = COPY %a0
+ %0 = COPY $a0
%1 = EXT %0, 17, 17
- %v0 = COPY %1
- RetRA implicit %v0
+ $v0 = COPY %1
+ RetRA implicit $v0
...
Modified: llvm/trunk/test/CodeGen/Mips/instverify/ext-pos.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/ext-pos.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/ext-pos.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/instverify/ext-pos.mir Wed Jan 31 14:04:26 2018
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr32, preferred-register: '' }
- { id: 1, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '%a0', virtual-reg: '%0' }
+ - { reg: '$a0', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0
+ liveins: $a0
- %0 = COPY %a0
+ %0 = COPY $a0
%1 = EXT %0, 44, 21
- %v0 = COPY %1
- RetRA implicit %v0
+ $v0 = COPY %1
+ RetRA implicit $v0
...
Modified: llvm/trunk/test/CodeGen/Mips/instverify/ext-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/ext-size.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/ext-size.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/instverify/ext-size.mir Wed Jan 31 14:04:26 2018
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gpr32, preferred-register: '' }
- { id: 1, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '%a0', virtual-reg: '%0' }
+ - { reg: '$a0', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -39,11 +39,11 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0
+ liveins: $a0
- %0 = COPY %a0
+ %0 = COPY $a0
%1 = EXT %0, 0, 33
- %v0 = COPY %1
- RetRA implicit %v0
+ $v0 = COPY %1
+ RetRA implicit $v0
...
Modified: llvm/trunk/test/CodeGen/Mips/instverify/ins-pos-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/ins-pos-size.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/ins-pos-size.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/instverify/ins-pos-size.mir Wed Jan 31 14:04:26 2018
@@ -18,8 +18,8 @@ registers:
- { id: 2, class: gpr32, preferred-register: '' }
- { id: 3, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '%a0', virtual-reg: '%0' }
- - { reg: '%a1', virtual-reg: '%1' }
+ - { reg: '$a0', virtual-reg: '%0' }
+ - { reg: '$a1', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -42,13 +42,13 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0, %a1
+ liveins: $a0, $a1
- %1 = COPY %a1
- %0 = COPY %a0
+ %1 = COPY $a1
+ %0 = COPY $a0
%2 = ANDi %1, 15
%3 = INS killed %2, 17, 17, %0
- %v0 = COPY %3
- RetRA implicit %v0
+ $v0 = COPY %3
+ RetRA implicit $v0
...
Modified: llvm/trunk/test/CodeGen/Mips/instverify/ins-pos.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/ins-pos.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/ins-pos.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/instverify/ins-pos.mir Wed Jan 31 14:04:26 2018
@@ -18,8 +18,8 @@ registers:
- { id: 2, class: gpr32, preferred-register: '' }
- { id: 3, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '%a0', virtual-reg: '%0' }
- - { reg: '%a1', virtual-reg: '%1' }
+ - { reg: '$a0', virtual-reg: '%0' }
+ - { reg: '$a1', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -42,13 +42,13 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0, %a1
+ liveins: $a0, $a1
- %1 = COPY %a1
- %0 = COPY %a0
+ %1 = COPY $a1
+ %0 = COPY $a0
%2 = ANDi %1, 15
%3 = INS killed %2, 32, 4, %0
- %v0 = COPY %3
- RetRA implicit %v0
+ $v0 = COPY %3
+ RetRA implicit $v0
...
Modified: llvm/trunk/test/CodeGen/Mips/instverify/ins-size.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/instverify/ins-size.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/instverify/ins-size.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/instverify/ins-size.mir Wed Jan 31 14:04:26 2018
@@ -18,8 +18,8 @@ registers:
- { id: 2, class: gpr32, preferred-register: '' }
- { id: 3, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '%a0', virtual-reg: '%0' }
- - { reg: '%a1', virtual-reg: '%1' }
+ - { reg: '$a0', virtual-reg: '%0' }
+ - { reg: '$a1', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -42,13 +42,13 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0, %a1
+ liveins: $a0, $a1
- %1 = COPY %a1
- %0 = COPY %a0
+ %1 = COPY $a1
+ %0 = COPY $a0
%2 = ANDi %1, 15
%3 = INS killed %2, 0, 40, %0
- %v0 = COPY %3
- RetRA implicit %v0
+ $v0 = COPY %3
+ RetRA implicit $v0
...
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/call.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/call.ll?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/call.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/call.ll Wed Jan 31 14:04:26 2018
@@ -161,8 +161,8 @@ declare hidden void @undef_double(i32 %t
define hidden void @thunk_undef_double(i32 %this, double %volume) unnamed_addr align 2 {
; ALL-LABEL: thunk_undef_double:
-; O32: # implicit-def: %a2
-; O32: # implicit-def: %a3
+; O32: # implicit-def: $a2
+; O32: # implicit-def: $a3
; NOT-R6C: jr $[[TGT]]
; R6C: jrc $[[TGT]]
Modified: llvm/trunk/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir Wed Jan 31 14:04:26 2018
@@ -118,8 +118,8 @@ registers:
- { id: 57, class: gpr64, preferred-register: '' }
- { id: 58, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%5' }
- - { reg: '%t9_64', virtual-reg: '' }
+ - { reg: '$a0_64', virtual-reg: '%5' }
+ - { reg: '$t9_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -143,21 +143,21 @@ constants:
body: |
bb.0.entry:
successors: %bb.1.entry._ZTW1k.exit_crit_edge(0x7fe00000), %bb.2.init.i.i(0x00200000)
- liveins: %a0_64, %t9_64
+ liveins: $a0_64, $t9_64
%57 = LUi64 target-flags(mips-gpoff-hi) @_Z2k1i
- %58 = DADDu %57, %t9_64
+ %58 = DADDu %57, $t9_64
%6 = DADDiu %58, target-flags(mips-gpoff-lo) @_Z2k1i
- %5 = COPY %a0_64
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
+ %5 = COPY $a0_64
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
%7 = LUi64 target-flags(mips-call-hi16) @_Z1gi
%8 = DADDu killed %7, %6
%9 = LD killed %8, target-flags(mips-call-lo16) @_Z1gi :: (load 8 from call-entry @_Z1gi)
- %a0_64 = COPY %5
- %gp_64 = COPY %6
- JALR64Pseudo killed %9, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
- %10 = COPY %v0
+ $a0_64 = COPY %5
+ $gp_64 = COPY %6
+ JALR64Pseudo killed %9, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ %10 = COPY $v0
%11 = COPY %5.sub_32
%12 = ADDu %10, killed %11
%13 = LUi64 target-flags(mips-got-hi16) @v
@@ -165,71 +165,71 @@ body: |
%15 = LD killed %14, target-flags(mips-got-lo16) @v :: (load 8 from got)
%16 = LW killed %15, 0 :: (dereferenceable load 4 from @v)
%0 = ADDu killed %12, killed %16
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
%17 = LUi64 target-flags(mips-call-hi16) &__tls_get_addr
%18 = DADDu killed %17, %6
%19 = LD killed %18, target-flags(mips-call-lo16) &__tls_get_addr :: (load 8 from call-entry &__tls_get_addr)
%20 = DADDiu %6, target-flags(mips-tlsldm) @__tls_guard
- %a0_64 = COPY %20
- %gp_64 = COPY %6
- JALR64Pseudo killed %19, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0_64
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
- %21 = COPY %v0_64
+ $a0_64 = COPY %20
+ $gp_64 = COPY %6
+ JALR64Pseudo killed %19, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0_64
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ %21 = COPY $v0_64
%22 = DADDiu %21, target-flags(mips-dtprel-hi) @__tls_guard
%23 = LBu killed %22, target-flags(mips-dtprel-lo) @__tls_guard :: (dereferenceable load 1 from @__tls_guard)
- BEQ killed %23, %zero, %bb.2.init.i.i, implicit-def dead %at
- B %bb.1.entry._ZTW1k.exit_crit_edge, implicit-def dead %at
+ BEQ killed %23, $zero, %bb.2.init.i.i, implicit-def dead $at
+ B %bb.1.entry._ZTW1k.exit_crit_edge, implicit-def dead $at
bb.1.entry._ZTW1k.exit_crit_edge:
successors: %bb.3._ZTW1k.exit(0x80000000)
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
%39 = LUi64 target-flags(mips-call-hi16) &__tls_get_addr
%40 = DADDu killed %39, %6
%41 = LD killed %40, target-flags(mips-call-lo16) &__tls_get_addr :: (load 8 from call-entry &__tls_get_addr)
%42 = DADDiu %6, target-flags(mips-tlsgd) @k
- %a0_64 = COPY %42
- %gp_64 = COPY %6
- JALR64Pseudo killed %41, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0_64
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
- %43 = COPY %v0_64
+ $a0_64 = COPY %42
+ $gp_64 = COPY %6
+ JALR64Pseudo killed %41, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0_64
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ %43 = COPY $v0_64
%1 = LW %43, 0 :: (dereferenceable load 4 from @k)
- B %bb.3._ZTW1k.exit, implicit-def dead %at
+ B %bb.3._ZTW1k.exit, implicit-def dead $at
bb.2.init.i.i:
successors: %bb.3._ZTW1k.exit(0x80000000)
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
%24 = LUi64 target-flags(mips-call-hi16) &__tls_get_addr
%25 = DADDu killed %24, %6
%26 = LD %25, target-flags(mips-call-lo16) &__tls_get_addr :: (load 8 from call-entry &__tls_get_addr)
%27 = DADDiu %6, target-flags(mips-tlsldm) @__tls_guard
- %a0_64 = COPY %27
- %gp_64 = COPY %6
- JALR64Pseudo killed %26, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0_64
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
- %28 = COPY %v0_64
+ $a0_64 = COPY %27
+ $gp_64 = COPY %6
+ JALR64Pseudo killed %26, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0_64
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ %28 = COPY $v0_64
%29 = DADDiu %28, target-flags(mips-dtprel-hi) @__tls_guard
- %30 = ADDiu %zero, 1
+ %30 = ADDiu $zero, 1
SB killed %30, killed %29, target-flags(mips-dtprel-lo) @__tls_guard :: (store 1 into @__tls_guard)
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
%31 = LUi64 target-flags(mips-call-hi16) @_Z1gi
%32 = DADDu killed %31, %6
- %33 = DADDiu %zero_64, 3
+ %33 = DADDiu $zero_64, 3
%34 = LD killed %32, target-flags(mips-call-lo16) @_Z1gi :: (load 8 from call-entry @_Z1gi)
- %a0_64 = COPY %33
- %gp_64 = COPY %6
- JALR64Pseudo killed %34, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
- %35 = COPY %v0
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
+ $a0_64 = COPY %33
+ $gp_64 = COPY %6
+ JALR64Pseudo killed %34, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ %35 = COPY $v0
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
%36 = LD %25, target-flags(mips-call-lo16) &__tls_get_addr :: (load 8 from call-entry &__tls_get_addr)
%37 = DADDiu %6, target-flags(mips-tlsgd) @k
- %a0_64 = COPY %37
- %gp_64 = COPY %6
- JALR64Pseudo killed %36, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0_64
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
- %38 = COPY %v0_64
+ $a0_64 = COPY %37
+ $gp_64 = COPY %6
+ JALR64Pseudo killed %36, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0_64
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ %38 = COPY $v0_64
SW %35, %38, 0 :: (store 4 into @k)
%2 = COPY %35
@@ -241,35 +241,35 @@ body: |
%44 = LUi64 target-flags(mips-got-hi16) @_ZTH1j
%45 = DADDu killed %44, %6
%46 = LD killed %45, target-flags(mips-got-lo16) @_ZTH1j :: (load 8 from got)
- BEQ64 killed %46, %zero_64, %bb.5._ZTW1j.exit, implicit-def dead %at
- B %bb.4, implicit-def dead %at
+ BEQ64 killed %46, $zero_64, %bb.5._ZTW1j.exit, implicit-def dead $at
+ B %bb.4, implicit-def dead $at
bb.4 (%ir-block.2):
successors: %bb.5._ZTW1j.exit(0x80000000)
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
%47 = LUi64 target-flags(mips-call-hi16) @_ZTH1j
%48 = DADDu killed %47, %6
%49 = LD killed %48, target-flags(mips-call-lo16) @_ZTH1j :: (load 8 from call-entry @_ZTH1j)
- %gp_64 = COPY %6
- JALR64Pseudo killed %49, csr_n64, implicit-def dead %ra, implicit %gp_64, implicit-def %sp
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
+ $gp_64 = COPY %6
+ JALR64Pseudo killed %49, csr_n64, implicit-def dead $ra, implicit $gp_64, implicit-def $sp
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
bb.5._ZTW1j.exit:
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
%50 = LUi64 target-flags(mips-call-hi16) &__tls_get_addr
%51 = DADDu killed %50, %6
%52 = LD killed %51, target-flags(mips-call-lo16) &__tls_get_addr :: (load 8 from call-entry &__tls_get_addr)
%53 = DADDiu %6, target-flags(mips-tlsgd) @j
- %a0_64 = COPY %53
- %gp_64 = COPY %6
- JALR64Pseudo killed %52, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0_64
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
- %54 = COPY %v0_64
+ $a0_64 = COPY %53
+ $gp_64 = COPY %6
+ JALR64Pseudo killed %52, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0_64
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ %54 = COPY $v0_64
%55 = LW %54, 0 :: (dereferenceable load 4 from @j)
%56 = ADDu %4, killed %55
- %v0 = COPY %56
- RetRA implicit %v0
+ $v0 = COPY %56
+ RetRA implicit $v0
...
Modified: llvm/trunk/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir Wed Jan 31 14:04:26 2018
@@ -45,9 +45,9 @@ registers:
- { id: 11, class: gpr32, preferred-register: '' }
- { id: 12, class: gpr32, preferred-register: '' }
liveins:
- - { reg: '%a0', virtual-reg: '%0' }
- - { reg: '%t9', virtual-reg: '' }
- - { reg: '%v0', virtual-reg: '' }
+ - { reg: '$a0', virtual-reg: '%0' }
+ - { reg: '$t9', virtual-reg: '' }
+ - { reg: '$v0', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -70,17 +70,17 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0, %t9, %v0
+ liveins: $a0, $t9, $v0
- %1 = ADDu %v0, %t9
- %0 = COPY %a0
- ADJCALLSTACKDOWN 16, 0, implicit-def dead %sp, implicit %sp
+ %1 = ADDu $v0, $t9
+ %0 = COPY $a0
+ ADJCALLSTACKDOWN 16, 0, implicit-def dead $sp, implicit $sp
%2 = LW %1, target-flags(mips-got-call) @_Z1gi :: (load 4 from call-entry @_Z1gi)
- %a0 = COPY %0
- %gp = COPY %1
- JALRPseudo killed %2, csr_o32_fpxx, implicit-def dead %ra, implicit %a0, implicit %gp, implicit-def %sp, implicit-def %v0
- ADJCALLSTACKUP 16, 0, implicit-def dead %sp, implicit %sp
- %3 = COPY %v0
+ $a0 = COPY %0
+ $gp = COPY %1
+ JALRPseudo killed %2, csr_o32_fpxx, implicit-def dead $ra, implicit $a0, implicit $gp, implicit-def $sp, implicit-def $v0
+ ADJCALLSTACKUP 16, 0, implicit-def dead $sp, implicit $sp
+ %3 = COPY $v0
%4 = ADDu %3, %0
%5 = LW %1, target-flags(mips-got) @v :: (load 4 from got)
%6 = LW killed %5, 0 :: (dereferenceable load 4 from @v)
@@ -88,8 +88,8 @@ body: |
%8 = LW %1, target-flags(mips-got) @j :: (load 4 from got)
%9 = LW killed %8, 0 :: (dereferenceable load 4 from @j)
%10 = ADDu killed %7, killed %9
- %v0 = COPY %10
- RetRA implicit %v0
+ $v0 = COPY %10
+ RetRA implicit $v0
...
Modified: llvm/trunk/test/CodeGen/Mips/mirparser/target-flags-pic.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mirparser/target-flags-pic.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mirparser/target-flags-pic.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/mirparser/target-flags-pic.mir Wed Jan 31 14:04:26 2018
@@ -46,8 +46,8 @@ registers:
- { id: 12, class: gpr64, preferred-register: '' }
- { id: 13, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%0' }
- - { reg: '%t9_64', virtual-reg: '' }
+ - { reg: '$a0_64', virtual-reg: '%0' }
+ - { reg: '$t9_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -70,19 +70,19 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0_64, %t9_64
+ liveins: $a0_64, $t9_64
%12 = LUi64 target-flags(mips-gpoff-hi) @_Z2k1i
- %13 = DADDu %12, %t9_64
+ %13 = DADDu %12, $t9_64
%1 = DADDiu %13, target-flags(mips-gpoff-lo) @_Z2k1i
- %0 = COPY %a0_64
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
+ %0 = COPY $a0_64
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
%2 = LD %1, target-flags(mips-got-call) @_Z1gi :: (load 8 from call-entry @_Z1gi)
- %a0_64 = COPY %0
- %gp_64 = COPY %1
- JALR64Pseudo killed %2, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
- %3 = COPY %v0
+ $a0_64 = COPY %0
+ $gp_64 = COPY %1
+ JALR64Pseudo killed %2, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ %3 = COPY $v0
%4 = COPY %0.sub_32
%5 = ADDu %3, killed %4
%6 = LD %1, target-flags(mips-got-disp) @v :: (load 8 from got)
@@ -91,8 +91,8 @@ body: |
%9 = LD %1, target-flags(mips-got-disp) @j :: (load 8 from got)
%10 = LW killed %9, 0 :: (dereferenceable load 4 from @j)
%11 = ADDu killed %8, killed %10
- %v0 = COPY %11
- RetRA implicit %v0
+ $v0 = COPY %11
+ RetRA implicit $v0
...
Modified: llvm/trunk/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir Wed Jan 31 14:04:26 2018
@@ -110,8 +110,8 @@ registers:
- { id: 50, class: gpr64, preferred-register: '' }
- { id: 51, class: gpr64, preferred-register: '' }
liveins:
- - { reg: '%a0_64', virtual-reg: '%5' }
- - { reg: '%t9_64', virtual-reg: '' }
+ - { reg: '$a0_64', virtual-reg: '%5' }
+ - { reg: '$t9_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -135,18 +135,18 @@ constants:
body: |
bb.0.entry:
successors: %bb.1.entry._ZTW1k.exit_crit_edge(0x7fe00000), %bb.2.init.i.i(0x00200000)
- liveins: %a0_64, %t9_64
+ liveins: $a0_64, $t9_64
%50 = LUi64 target-flags(mips-gpoff-hi) @_Z2k1i
- %51 = DADDu %50, %t9_64
+ %51 = DADDu %50, $t9_64
%43 = DADDiu %51, target-flags(mips-gpoff-lo) @_Z2k1i
- %5 = COPY %a0_64
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
+ %5 = COPY $a0_64
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
%6 = COPY %5.sub_32
- %a0_64 = COPY %5
- JAL @_Z1gi, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit-def %sp, implicit-def %v0
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
- %7 = COPY %v0
+ $a0_64 = COPY %5
+ JAL @_Z1gi, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $v0
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ %7 = COPY $v0
%8 = ADDu %7, killed %6
%9 = LUi64 target-flags(mips-highest) @v
%10 = DADDiu killed %9, target-flags(mips-higher) @v
@@ -157,46 +157,46 @@ body: |
%0 = ADDu killed %8, killed %14
%15 = LUi64 target-flags(mips-tprel-hi) @__tls_guard
%16 = DADDiu killed %15, target-flags(mips-tprel-lo) @__tls_guard
- %17 = RDHWR64 %hwr29
- %v1_64 = COPY %17
- %18 = COPY %v1_64
+ %17 = RDHWR64 $hwr29
+ $v1_64 = COPY %17
+ %18 = COPY $v1_64
%19 = DADDu %18, killed %16
%20 = LBu killed %19, 0 :: (dereferenceable load 1 from @__tls_guard)
- BEQ killed %20, %zero, %bb.2.init.i.i, implicit-def dead %at
- J %bb.1.entry._ZTW1k.exit_crit_edge, implicit-def dead %at
+ BEQ killed %20, $zero, %bb.2.init.i.i, implicit-def dead $at
+ J %bb.1.entry._ZTW1k.exit_crit_edge, implicit-def dead $at
bb.1.entry._ZTW1k.exit_crit_edge:
successors: %bb.3._ZTW1k.exit(0x80000000)
%32 = LUi64 target-flags(mips-tprel-hi) @k
%33 = DADDiu killed %32, target-flags(mips-tprel-lo) @k
- %34 = RDHWR64 %hwr29
- %v1_64 = COPY %34
- %35 = COPY %v1_64
+ %34 = RDHWR64 $hwr29
+ $v1_64 = COPY %34
+ %35 = COPY $v1_64
%36 = DADDu %35, killed %33
%1 = LW killed %36, 0 :: (dereferenceable load 4 from @k)
- J %bb.3._ZTW1k.exit, implicit-def dead %at
+ J %bb.3._ZTW1k.exit, implicit-def dead $at
bb.2.init.i.i:
successors: %bb.3._ZTW1k.exit(0x80000000)
%21 = LUi64 target-flags(mips-tprel-hi) @__tls_guard
%22 = DADDiu killed %21, target-flags(mips-tprel-lo) @__tls_guard
- %23 = RDHWR64 %hwr29
- %v1_64 = COPY %23
- %24 = COPY %v1_64
+ %23 = RDHWR64 $hwr29
+ $v1_64 = COPY %23
+ %24 = COPY $v1_64
%25 = DADDu %24, killed %22
- %26 = ADDiu %zero, 1
+ %26 = ADDiu $zero, 1
SB killed %26, killed %25, 0 :: (store 1 into @__tls_guard)
%27 = LUi64 target-flags(mips-tprel-hi) @k
%28 = DADDiu killed %27, target-flags(mips-tprel-lo) @k
%29 = DADDu %24, killed %28
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
- %30 = DADDiu %zero_64, 3
- %a0_64 = COPY %30
- JAL @_Z1gi, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit-def %sp, implicit-def %v0
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
- %31 = COPY %v0
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ %30 = DADDiu $zero_64, 3
+ $a0_64 = COPY %30
+ JAL @_Z1gi, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $v0
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ %31 = COPY $v0
SW %31, killed %29, 0 :: (store 4 into @k)
%2 = COPY %31
@@ -211,26 +211,26 @@ body: |
%40 = DADDiu killed %39, target-flags(mips-abs-hi) @_ZTH1j
%41 = DSLL killed %40, 16
%42 = DADDiu killed %41, target-flags(mips-abs-lo) @_ZTH1j
- BEQ64 killed %42, %zero_64, %bb.5._ZTW1j.exit, implicit-def dead %at
- J %bb.4, implicit-def dead %at
+ BEQ64 killed %42, $zero_64, %bb.5._ZTW1j.exit, implicit-def dead $at
+ J %bb.4, implicit-def dead $at
bb.4 (%ir-block.2):
successors: %bb.5._ZTW1j.exit(0x80000000)
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
- JAL @_ZTH1j, csr_n64, implicit-def dead %ra, implicit-def %sp
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ JAL @_ZTH1j, csr_n64, implicit-def dead $ra, implicit-def $sp
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
bb.5._ZTW1j.exit:
- %44 = RDHWR64 %hwr29
- %v1_64 = COPY %44
+ %44 = RDHWR64 $hwr29
+ $v1_64 = COPY %44
%45 = LD %43, target-flags(mips-gottprel) @j :: (load 8)
- %46 = COPY %v1_64
+ %46 = COPY $v1_64
%47 = DADDu %46, killed %45
%48 = LW killed %47, 0 :: (dereferenceable load 4 from @j)
%49 = ADDu %4, killed %48
- %v0 = COPY %49
- RetRA implicit %v0
+ $v0 = COPY %49
+ RetRA implicit $v0
...
Modified: llvm/trunk/test/CodeGen/Mips/msa/emergency-spill.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/emergency-spill.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/msa/emergency-spill.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/msa/emergency-spill.mir Wed Jan 31 14:04:26 2018
@@ -77,11 +77,11 @@ selected: false
tracksRegLiveness: true
registers:
liveins:
- - { reg: '%a0_64', virtual-reg: '' }
- - { reg: '%a1_64', virtual-reg: '' }
- - { reg: '%a2_64', virtual-reg: '' }
- - { reg: '%a3_64', virtual-reg: '' }
- - { reg: '%t0_64', virtual-reg: '' }
+ - { reg: '$a0_64', virtual-reg: '' }
+ - { reg: '$a1_64', virtual-reg: '' }
+ - { reg: '$a2_64', virtual-reg: '' }
+ - { reg: '$a3_64', virtual-reg: '' }
+ - { reg: '$t0_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -122,91 +122,91 @@ stack:
constants:
body: |
bb.0.entry:
- liveins: %a0_64, %a1_64, %a2_64, %a3_64, %t0_64
+ liveins: $a0_64, $a1_64, $a2_64, $a3_64, $t0_64
- SD killed %a0_64, %stack.1.a, 0 :: (store 8 into %ir.1, align 16)
- SD killed %a1_64, %stack.1.a, 8 :: (store 8 into %ir.2)
- %w0 = LD_B %stack.1.a, 0 :: (dereferenceable load 16 from %ir.a)
- SD killed %a2_64, %stack.2.b, 0 :: (store 8 into %ir.4, align 16)
- SD killed %a3_64, %stack.2.b, 8 :: (store 8 into %ir.5)
- %w1 = LD_B %stack.2.b, 0 :: (dereferenceable load 16 from %ir.b)
- ST_B killed %w0, %stack.3.a.addr, 0 :: (store 16 into %ir.a.addr)
- ST_B killed %w1, %stack.4.b.addr, 0 :: (store 16 into %ir.b.addr)
- SW %t0, %stack.5.c.addr, 0, implicit killed %t0_64 :: (store 4 into %ir.c.addr)
- %at_64 = LEA_ADDiu64 %stack.8, 0
- SD killed %at_64, %stack.6.g, 0 :: (store 8 into %ir.g)
- %a1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
- %a0_64 = LEA_ADDiu64 %stack.4.b.addr, 0
- JAL @h, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %a1_64, implicit-def %sp
- ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
- %at_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %v0_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %v1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %a0_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %a1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %a2_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %a3_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %t0_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %t1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %t2_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %t3_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %t4_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %t5_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %t6_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %t7_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %s0_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %s1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %s2_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %s3_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %s4_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %s5_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %s6_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %s7_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %t8_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %t9_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %ra_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
- %w0 = LD_B %stack.3.a.addr, 0 :: (dereferenceable load 16 from %ir.a.addr)
- SD %at_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %v0_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %v1_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %a0_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %a1_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %a2_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %a3_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %t0_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %t1_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %t2_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %t3_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %t4_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %t5_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %t6_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %t7_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %s0_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %s1_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %s2_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %s3_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %s4_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %s5_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %s6_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %s7_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %t8_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %t9_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- SD %ra_64, %stack.7.d, 0 :: (store 8 into %ir.d)
- %at_64 = LD %stack.7.d, 0 :: (dereferenceable load 8 from %ir.d)
- %v0 = LB %at_64, 0 :: (load 1 from %ir.arrayidx)
- %w1 = FILL_B killed %v0
- %w0 = ADDV_B killed %w0, killed %w1
- %at = LB killed %at_64, 1 :: (load 1 from %ir.arrayidx3)
- %w1 = FILL_B killed %at
- %w0 = ADDV_B killed %w0, killed %w1
- %w1 = LD_B %stack.4.b.addr, 0 :: (dereferenceable load 16 from %ir.b.addr)
- %w0 = ADDV_B killed %w1, killed %w0
- ST_B killed %w0, %stack.4.b.addr, 0 :: (store 16 into %ir.b.addr)
- %w0 = LD_B %stack.4.b.addr, 0 :: (dereferenceable load 16 from %ir.b.addr)
- ST_B killed %w0, %stack.0.retval, 0 :: (store 16 into %ir.retval)
- %v0_64 = LD %stack.0.retval, 0 :: (dereferenceable load 8 from %ir.20, align 16)
- %v1_64 = LD %stack.0.retval, 8 :: (dereferenceable load 8 from %ir.20 + 8, align 16)
- RetRA implicit %v0_64, implicit %v1_64
+ SD killed $a0_64, %stack.1.a, 0 :: (store 8 into %ir.1, align 16)
+ SD killed $a1_64, %stack.1.a, 8 :: (store 8 into %ir.2)
+ $w0 = LD_B %stack.1.a, 0 :: (dereferenceable load 16 from %ir.a)
+ SD killed $a2_64, %stack.2.b, 0 :: (store 8 into %ir.4, align 16)
+ SD killed $a3_64, %stack.2.b, 8 :: (store 8 into %ir.5)
+ $w1 = LD_B %stack.2.b, 0 :: (dereferenceable load 16 from %ir.b)
+ ST_B killed $w0, %stack.3.a.addr, 0 :: (store 16 into %ir.a.addr)
+ ST_B killed $w1, %stack.4.b.addr, 0 :: (store 16 into %ir.b.addr)
+ SW $t0, %stack.5.c.addr, 0, implicit killed $t0_64 :: (store 4 into %ir.c.addr)
+ $at_64 = LEA_ADDiu64 %stack.8, 0
+ SD killed $at_64, %stack.6.g, 0 :: (store 8 into %ir.g)
+ $a1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+ $a0_64 = LEA_ADDiu64 %stack.4.b.addr, 0
+ JAL @h, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $a1_64, implicit-def $sp
+ ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+ $at_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $v0_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $v1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $a0_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $a1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $a2_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $a3_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $t0_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $t1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $t2_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $t3_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $t4_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $t5_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $t6_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $t7_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $s0_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $s1_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $s2_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $s3_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $s4_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $s5_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $s6_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $s7_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $t8_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $t9_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $ra_64 = LD %stack.6.g, 0 :: (dereferenceable load 8 from %ir.g)
+ $w0 = LD_B %stack.3.a.addr, 0 :: (dereferenceable load 16 from %ir.a.addr)
+ SD $at_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $v0_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $v1_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $a0_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $a1_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $a2_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $a3_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $t0_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $t1_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $t2_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $t3_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $t4_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $t5_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $t6_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $t7_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $s0_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $s1_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $s2_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $s3_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $s4_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $s5_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $s6_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $s7_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $t8_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $t9_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ SD $ra_64, %stack.7.d, 0 :: (store 8 into %ir.d)
+ $at_64 = LD %stack.7.d, 0 :: (dereferenceable load 8 from %ir.d)
+ $v0 = LB $at_64, 0 :: (load 1 from %ir.arrayidx)
+ $w1 = FILL_B killed $v0
+ $w0 = ADDV_B killed $w0, killed $w1
+ $at = LB killed $at_64, 1 :: (load 1 from %ir.arrayidx3)
+ $w1 = FILL_B killed $at
+ $w0 = ADDV_B killed $w0, killed $w1
+ $w1 = LD_B %stack.4.b.addr, 0 :: (dereferenceable load 16 from %ir.b.addr)
+ $w0 = ADDV_B killed $w1, killed $w0
+ ST_B killed $w0, %stack.4.b.addr, 0 :: (store 16 into %ir.b.addr)
+ $w0 = LD_B %stack.4.b.addr, 0 :: (dereferenceable load 16 from %ir.b.addr)
+ ST_B killed $w0, %stack.0.retval, 0 :: (store 16 into %ir.retval)
+ $v0_64 = LD %stack.0.retval, 0 :: (dereferenceable load 8 from %ir.20, align 16)
+ $v1_64 = LD %stack.0.retval, 8 :: (dereferenceable load 8 from %ir.20 + 8, align 16)
+ RetRA implicit $v0_64, implicit $v1_64
...
Modified: llvm/trunk/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/sll-micromips-r6-encoding.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/sll-micromips-r6-encoding.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/sll-micromips-r6-encoding.mir Wed Jan 31 14:04:26 2018
@@ -17,7 +17,7 @@ selected: false
tracksRegLiveness: false
registers:
liveins:
- - { reg: '%a0', virtual-reg: '' }
+ - { reg: '$a0', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -40,7 +40,7 @@ stack:
constants:
body: |
bb.0.entry:
- %zero = SLL_MMR6 killed %zero, 0
- JRC16_MM undef %ra, implicit %v0
+ $zero = SLL_MMR6 killed $zero, 0
+ JRC16_MM undef $ra, implicit $v0
...
Modified: llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir (original)
+++ llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir Wed Jan 31 14:04:26 2018
@@ -46,8 +46,8 @@ alignment: 4
exposesReturnsTwice: false
tracksRegLiveness: true
liveins:
- - { reg: '%x3' }
- - { reg: '%x4' }
+ - { reg: '$x3' }
+ - { reg: '$x4' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
@@ -63,36 +63,36 @@ frameInfo:
hasVAStart: false
hasMustTailInVarArgFunc: false
fixedStack:
- - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%x30' }
- - { id: 1, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '%x29' }
+ - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '$x30' }
+ - { id: 1, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '$x29' }
body: |
bb.0.entry:
- liveins: %x3, %x4, %x29, %x30, %x29, %x30
+ liveins: $x3, $x4, $x29, $x30, $x29, $x30
- %x0 = MFLR8 implicit %lr8
- STD %x0, 16, %x1
- %x1 = STDU %x1, -144, %x1
- STD killed %x29, 120, %x1 :: (store 8 into %fixed-stack.1)
- STD killed %x30, 128, %x1 :: (store 8 into %fixed-stack.0, align 16)
- %x30 = OR8 %x4, %x4
- %x3 = LD 0, killed %x3 :: (load 8 from %ir.p1)
- %x29 = ADDI8 killed %x3, -48
- %x3 = ADDIStocHA %x2, @tasklist_lock
- %x3 = LDtocL @tasklist_lock, killed %x3, implicit %x2 :: (load 8 from got)
- BL8_NOP @__raw_read_unlock, csr_svr464_altivec, implicit-def %lr8, implicit %rm, implicit %x3, implicit %x2, implicit-def %r1, implicit-def dead %x3
- %r3 = LI 0
- STW killed %r3, 0, killed %x30 :: (volatile store 4 into %ir.p2)
+ $x0 = MFLR8 implicit $lr8
+ STD $x0, 16, $x1
+ $x1 = STDU $x1, -144, $x1
+ STD killed $x29, 120, $x1 :: (store 8 into %fixed-stack.1)
+ STD killed $x30, 128, $x1 :: (store 8 into %fixed-stack.0, align 16)
+ $x30 = OR8 $x4, $x4
+ $x3 = LD 0, killed $x3 :: (load 8 from %ir.p1)
+ $x29 = ADDI8 killed $x3, -48
+ $x3 = ADDIStocHA $x2, @tasklist_lock
+ $x3 = LDtocL @tasklist_lock, killed $x3, implicit $x2 :: (load 8 from got)
+ BL8_NOP @__raw_read_unlock, csr_svr464_altivec, implicit-def $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3
+ $r3 = LI 0
+ STW killed $r3, 0, killed $x30 :: (volatile store 4 into %ir.p2)
INLINEASM &"#compiler barrier", 25
- INLINEASM &"\0Alwsync \0A1:\09lwarx\09$0,0,$1\09\09# atomic_dec_return\0A\09addic\09$0,$0,-1\0A\09stwcx.\09$0,0,$1\0A\09bne-\091b\0Async \0A", 25, 131083, def early-clobber %r3, 851977, killed %x29, 12, implicit-def dead early-clobber %cr0
+ INLINEASM &"\0Alwsync \0A1:\09lwarx\09$0,0,$1\09\09# atomic_dec_return\0A\09addic\09$0,$0,-1\0A\09stwcx.\09$0,0,$1\0A\09bne-\091b\0Async \0A", 25, 131083, def early-clobber $r3, 851977, killed $x29, 12, implicit-def dead early-clobber $cr0
; CHECK-LABEL: @mm_update_next_owner
; CHECK-NOT: lwarx 29, 0, 29
; CHECK-NOT: stwcx. 29, 0, 29
- %cr0 = CMPLWI killed %r3, 0
- %x30 = LD 128, %x1 :: (load 8 from %fixed-stack.0, align 16)
- %x29 = LD 120, %x1 :: (load 8 from %fixed-stack.1)
- %x1 = ADDI8 %x1, 144
- %x0 = LD 16, %x1
- MTLR8 %x0, implicit-def %lr8
- BLR8 implicit %lr8, implicit %rm
+ $cr0 = CMPLWI killed $r3, 0
+ $x30 = LD 128, $x1 :: (load 8 from %fixed-stack.0, align 16)
+ $x29 = LD 120, $x1 :: (load 8 from %fixed-stack.1)
+ $x1 = ADDI8 $x1, 144
+ $x0 = LD 16, $x1
+ MTLR8 $x0, implicit-def $lr8
+ BLR8 implicit $lr8, implicit $rm
...
Modified: llvm/trunk/test/CodeGen/PowerPC/addegluecrash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/addegluecrash.ll?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/addegluecrash.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/addegluecrash.ll Wed Jan 31 14:04:26 2018
@@ -23,7 +23,7 @@ define void @bn_mul_comba8(i64* nocaptur
; CHECK-NEXT: cmpld 7, 4, 5
; CHECK-NEXT: mfocrf 10, 1
; CHECK-NEXT: rlwinm 10, 10, 29, 31, 31
-; CHECK-NEXT: # implicit-def: %x4
+; CHECK-NEXT: # implicit-def: $x4
; CHECK-NEXT: mr 4, 10
; CHECK-NEXT: clrldi 4, 4, 32
; CHECK-NEXT: std 4, 0(3)
Modified: llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir (original)
+++ llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir Wed Jan 31 14:04:26 2018
@@ -42,36 +42,36 @@ frameInfo:
hasVAStart: false
hasMustTailInVarArgFunc: false
fixedStack:
- - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%x30' }
+ - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '$x30' }
- { id: 1, offset: -8, size: 8, alignment: 8, isImmutable: true, isAliased: false }
body: |
bb.0.entry:
- liveins: %x30, %x30
+ liveins: $x30, $x30
- %x0 = MFLR8 implicit %lr8
- STD %x31, -8, %x1
- STD killed %x0, 16, %x1
- %x1 = STDU %x1, -64, %x1
- %x3 = ADDIStlsldHA %x2, @x
- %x31 = OR8 %x1, %x1
- %x3 = ADDItlsldL killed %x3, @x
- STD killed %x30, 48, %x31 :: (store 8 into %fixed-stack.0, align 16)
- %x3 = GETtlsldADDR killed %x3, @x, implicit-def dead %x0, implicit-def dead %x4, implicit-def dead %x5, implicit-def dead %x6, implicit-def dead %x7, implicit-def dead %x8, implicit-def dead %x9, implicit-def dead %x10, implicit-def dead %x11, implicit-def dead %x12, implicit-def %lr8, implicit-def %ctr8, implicit-def dead %cr0, implicit-def dead %cr1, implicit-def dead %cr5, implicit-def dead %cr6, implicit-def dead %cr7
- %x12 = ADDIStlsgdHA %x2, @y
- %x30 = OR8 killed %x3, %x3
- %x3 = ADDItlsgdL killed %x12, @y
- %x3 = GETtlsADDR killed %x3, @y, implicit-def dead %x0, implicit-def dead %x4, implicit-def dead %x5, implicit-def dead %x6, implicit-def dead %x7, implicit-def dead %x8, implicit-def dead %x9, implicit-def dead %x10, implicit-def dead %x11, implicit-def dead %x12, implicit-def %lr8, implicit-def %ctr8, implicit-def dead %cr0, implicit-def dead %cr1, implicit-def dead %cr5, implicit-def dead %cr6, implicit-def dead %cr7
- %x4 = ADDISdtprelHA killed %x30, @x
+ $x0 = MFLR8 implicit $lr8
+ STD $x31, -8, $x1
+ STD killed $x0, 16, $x1
+ $x1 = STDU $x1, -64, $x1
+ $x3 = ADDIStlsldHA $x2, @x
+ $x31 = OR8 $x1, $x1
+ $x3 = ADDItlsldL killed $x3, @x
+ STD killed $x30, 48, $x31 :: (store 8 into %fixed-stack.0, align 16)
+ $x3 = GETtlsldADDR killed $x3, @x, implicit-def dead $x0, implicit-def dead $x4, implicit-def dead $x5, implicit-def dead $x6, implicit-def dead $x7, implicit-def dead $x8, implicit-def dead $x9, implicit-def dead $x10, implicit-def dead $x11, implicit-def dead $x12, implicit-def $lr8, implicit-def $ctr8, implicit-def dead $cr0, implicit-def dead $cr1, implicit-def dead $cr5, implicit-def dead $cr6, implicit-def dead $cr7
+ $x12 = ADDIStlsgdHA $x2, @y
+ $x30 = OR8 killed $x3, $x3
+ $x3 = ADDItlsgdL killed $x12, @y
+ $x3 = GETtlsADDR killed $x3, @y, implicit-def dead $x0, implicit-def dead $x4, implicit-def dead $x5, implicit-def dead $x6, implicit-def dead $x7, implicit-def dead $x8, implicit-def dead $x9, implicit-def dead $x10, implicit-def dead $x11, implicit-def dead $x12, implicit-def $lr8, implicit-def $ctr8, implicit-def dead $cr0, implicit-def dead $cr1, implicit-def dead $cr5, implicit-def dead $cr6, implicit-def dead $cr7
+ $x4 = ADDISdtprelHA killed $x30, @x
; CHECK: addis 4, 30, x at dtprel@ha
- %x5 = LI8 1
- %r6 = LI 20
- %x30 = LD 48, %x31 :: (load 8 from %fixed-stack.0, align 16)
- STB8 killed %x5, target-flags(ppc-dtprel-lo) @x, killed %x4 :: (store 1 into @x)
- STW killed %r6, 0, killed %x3 :: (store 4 into @y)
- %x1 = ADDI8 %x1, 64
- %x0 = LD 16, %x1
- %x31 = LD -8, %x1
- MTLR8 killed %x0, implicit-def %lr8
- BLR8 implicit %lr8, implicit %rm
+ $x5 = LI8 1
+ $r6 = LI 20
+ $x30 = LD 48, $x31 :: (load 8 from %fixed-stack.0, align 16)
+ STB8 killed $x5, target-flags(ppc-dtprel-lo) @x, killed $x4 :: (store 1 into @x)
+ STW killed $r6, 0, killed $x3 :: (store 4 into @y)
+ $x1 = ADDI8 $x1, 64
+ $x0 = LD 16, $x1
+ $x31 = LD -8, $x1
+ MTLR8 killed $x0, implicit-def $lr8
+ BLR8 implicit $lr8, implicit $rm
...
Modified: llvm/trunk/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll?rev=323922&r1=323921&r2=323922&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll Wed Jan 31 14:04:26 2018
@@ -10,7 +10,7 @@ entry:
lnext:
%elementArray = load i32*, i32** %elementArrayPtr, align 8
; CHECK: lwz [[LDREG:[0-9]+]], 124(1) # 4-byte Folded Reload
-; CHECK: # implicit-def: %x[[TEMPREG:[0-9]+]]
+; CHECK: # implicit-def: $x[[TEMPREG:[0-9]+]]
%element = load i32, i32* %elementArray, align 4
; CHECK: mr [[TEMPREG]], [[LDREG]]
; CHECK: clrldi 4, [[TEMPREG]], 32
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