[llvm] r323911 - [Hexagon] Handle SETCC on vector pairs in lowering
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 31 12:46:55 PST 2018
Author: kparzysz
Date: Wed Jan 31 12:46:55 2018
New Revision: 323911
URL: http://llvm.org/viewvc/llvm-project?rev=323911&view=rev
Log:
[Hexagon] Handle SETCC on vector pairs in lowering
Added:
llvm/trunk/test/CodeGen/Hexagon/autohvx/isel-setcc-pair.ll
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/trunk/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=323911&r1=323910&r2=323911&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Wed Jan 31 12:46:55 2018
@@ -2139,6 +2139,9 @@ HexagonTargetLowering::HexagonTargetLowe
// independent) handling of it would convert it to a load, which is
// not always the optimal choice.
setOperationAction(ISD::BUILD_VECTOR, T, Custom);
+ // Custom-lower SETCC for pairs. Expand it into a concat of SETCCs
+ // for individual vectors.
+ setOperationAction(ISD::SETCC, T, Custom);
if (T == ByteW)
continue;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp?rev=323911&r1=323910&r2=323911&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp Wed Jan 31 12:46:55 2018
@@ -1014,9 +1014,22 @@ SDValue
HexagonTargetLowering::LowerHvxSetCC(SDValue Op, SelectionDAG &DAG) const {
MVT VecTy = ty(Op.getOperand(0));
assert(VecTy == ty(Op.getOperand(1)));
+ unsigned HwLen = Subtarget.getVectorLength();
+ const SDLoc &dl(Op);
SDValue Cmp = Op.getOperand(2);
ISD::CondCode CC = cast<CondCodeSDNode>(Cmp)->get();
+
+ if (VecTy.getSizeInBits() == 16*HwLen) {
+ VectorPair P0 = opSplit(Op.getOperand(0), dl, DAG);
+ VectorPair P1 = opSplit(Op.getOperand(1), dl, DAG);
+ MVT HalfTy = typeSplit(VecTy).first;
+
+ SDValue V0 = DAG.getSetCC(dl, HalfTy, P0.first, P1.first, CC);
+ SDValue V1 = DAG.getSetCC(dl, HalfTy, P0.second, P1.second, CC);
+ return DAG.getNode(ISD::CONCAT_VECTORS, dl, ty(Op), V1, V0);
+ }
+
bool Negate = false, Swap = false;
// HVX has instructions for SETEQ, SETGT, SETUGT. The other comparisons
@@ -1077,7 +1090,6 @@ HexagonTargetLowering::LowerHvxSetCC(SDV
unsigned CmpOpc = OpcTable[Log2_32(ElemWidth)-3][getIdx(CC)];
MVT ResTy = ty(Op);
- const SDLoc &dl(Op);
SDValue OpL = Swap ? Op.getOperand(1) : Op.getOperand(0);
SDValue OpR = Swap ? Op.getOperand(0) : Op.getOperand(1);
SDValue CmpV = getNode(CmpOpc, dl, ResTy, {OpL, OpR}, DAG);
Added: llvm/trunk/test/CodeGen/Hexagon/autohvx/isel-setcc-pair.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/autohvx/isel-setcc-pair.ll?rev=323911&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/autohvx/isel-setcc-pair.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/autohvx/isel-setcc-pair.ll Wed Jan 31 12:46:55 2018
@@ -0,0 +1,29 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Check that a setcc of a vector pair is handled (without crashing).
+; CHECK: vcmp
+
+target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
+target triple = "hexagon"
+
+; Function Attrs: nounwind
+define hidden fastcc void @fred(i32 %a0) #0 {
+b1:
+ %v2 = insertelement <32 x i32> undef, i32 %a0, i32 0
+ %v3 = shufflevector <32 x i32> %v2, <32 x i32> undef, <32 x i32> zeroinitializer
+ %v4 = icmp eq <32 x i32> %v3, undef
+ %v5 = and <32 x i1> undef, %v4
+ br label %b6
+
+b6: ; preds = %b1
+ %v7 = extractelement <32 x i1> %v5, i32 22
+ br i1 %v7, label %b8, label %b9
+
+b8: ; preds = %b6
+ unreachable
+
+b9: ; preds = %b6
+ unreachable
+}
+
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
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