[PATCH] D42746: MIR PhysReg sigil change from '%' to '$'
Puyan Lotfi via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 31 10:08:34 PST 2018
plotfi created this revision.
plotfi added reviewers: qcolombet, MatzeB, bogner.
Herald added subscribers: llvm-commits, eraman, javed.absar, nhaehnle, nemanjai, sdardis, dschuff.
This is the patch to change the sigil for MIR physical registers to using '$' so that we don't have name conflicts with named vregs that will be coming in the future,
Repository:
rL LLVM
https://reviews.llvm.org/D42746
Files:
lib/CodeGen/MIRParser/MILexer.cpp
lib/CodeGen/TargetRegisterInfo.cpp
test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
test/CodeGen/AArch64/GlobalISel/call-translator.ll
test/CodeGen/AArch64/GlobalISel/debug-insts.ll
test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll
test/CodeGen/AArch64/GlobalISel/fp128-legalize-crash-pr35690.mir
test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll
test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
test/CodeGen/AArch64/GlobalISel/legalize-add.mir
test/CodeGen/AArch64/GlobalISel/legalize-and.mir
test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir
test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-with-success.mir
test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir
test/CodeGen/AArch64/GlobalISel/legalize-combines.mir
test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
test/CodeGen/AArch64/GlobalISel/legalize-div.mir
test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir
test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
test/CodeGen/AArch64/GlobalISel/legalize-fneg.mir
test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir
test/CodeGen/AArch64/GlobalISel/legalize-gep.mir
test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir
test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir
test/CodeGen/AArch64/GlobalISel/legalize-or.mir
test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir
test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir
test/CodeGen/AArch64/GlobalISel/localizer.mir
test/CodeGen/AArch64/GlobalISel/machine-cse-mid-pipeline.mir
test/CodeGen/AArch64/GlobalISel/no-regclass.mir
test/CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir
test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir
test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
test/CodeGen/AArch64/GlobalISel/regbankselect-reg_sequence.mir
test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir
test/CodeGen/AArch64/GlobalISel/select-binop.mir
test/CodeGen/AArch64/GlobalISel/select-bitcast-bigendian.mir
test/CodeGen/AArch64/GlobalISel/select-bitcast.mir
test/CodeGen/AArch64/GlobalISel/select-br.mir
test/CodeGen/AArch64/GlobalISel/select-bswap.mir
test/CodeGen/AArch64/GlobalISel/select-cbz.mir
test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir
test/CodeGen/AArch64/GlobalISel/select-constant.mir
test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir
test/CodeGen/AArch64/GlobalISel/select-fma.mir
test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir
test/CodeGen/AArch64/GlobalISel/select-imm.mir
test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir
test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir
test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-hint.mir
test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-sdiv.mir
test/CodeGen/AArch64/GlobalISel/select-intrinsic-crypto-aesmc.mir
test/CodeGen/AArch64/GlobalISel/select-load.mir
test/CodeGen/AArch64/GlobalISel/select-mul.mir
test/CodeGen/AArch64/GlobalISel/select-muladd.mir
test/CodeGen/AArch64/GlobalISel/select-neon-vcvtfxu2fp.mir
test/CodeGen/AArch64/GlobalISel/select-phi.mir
test/CodeGen/AArch64/GlobalISel/select-pr32733.mir
test/CodeGen/AArch64/GlobalISel/select-store.mir
test/CodeGen/AArch64/GlobalISel/select-trunc.mir
test/CodeGen/AArch64/GlobalISel/select-xor.mir
test/CodeGen/AArch64/GlobalISel/select.mir
test/CodeGen/AArch64/GlobalISel/translate-gep.ll
test/CodeGen/AArch64/GlobalISel/varargs-ios-translator.ll
test/CodeGen/AArch64/GlobalISel/vastart.ll
test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir
test/CodeGen/AArch64/GlobalISel/verify-selected.mir
test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
test/CodeGen/AArch64/arm64-csldst-mmo.ll
test/CodeGen/AArch64/arm64-ldst-unscaled-pre-post.mir
test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
test/CodeGen/AArch64/arm64-misched-multimmo.ll
test/CodeGen/AArch64/arm64-regress-opt-cmp.mir
test/CodeGen/AArch64/ccmp-successor-probs.mir
test/CodeGen/AArch64/cfi_restore.mir
test/CodeGen/AArch64/falkor-hwpf-fix.mir
test/CodeGen/AArch64/ldst-opt-aa.mir
test/CodeGen/AArch64/ldst-opt-zr-clobber.mir
test/CodeGen/AArch64/ldst-opt.mir
test/CodeGen/AArch64/live-interval-analysis.mir
test/CodeGen/AArch64/loh.mir
test/CodeGen/AArch64/machine-combiner.mir
test/CodeGen/AArch64/machine-copy-remove.mir
test/CodeGen/AArch64/machine-dead-copy.mir
test/CodeGen/AArch64/machine-outliner.mir
test/CodeGen/AArch64/machine-scheduler.mir
test/CodeGen/AArch64/machine-sink-zr.mir
test/CodeGen/AArch64/machine-zero-copy-remove.mir
test/CodeGen/AArch64/movimm-wzr.mir
test/CodeGen/AArch64/phi-dbg.ll
test/CodeGen/AArch64/reg-scavenge-frame.mir
test/CodeGen/AArch64/regcoal-physreg.mir
test/CodeGen/AArch64/scheduledag-constreg.mir
test/CodeGen/AArch64/spill-fold.mir
test/CodeGen/AArch64/spill-undef.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
test/CodeGen/AMDGPU/break-smem-soft-clauses.mir
test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir
test/CodeGen/AMDGPU/clamp-omod-special-case.mir
test/CodeGen/AMDGPU/cluster-flat-loads-postra.mir
test/CodeGen/AMDGPU/cluster-flat-loads.mir
test/CodeGen/AMDGPU/coalescer-subreg-join.mir
test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
test/CodeGen/AMDGPU/dead_copy.mir
test/CodeGen/AMDGPU/debug-value2.ll
test/CodeGen/AMDGPU/detect-dead-lanes.mir
test/CodeGen/AMDGPU/endpgm-dce.mir
test/CodeGen/AMDGPU/fix-vgpr-copies.mir
test/CodeGen/AMDGPU/fix-wwm-liveness.mir
test/CodeGen/AMDGPU/flat-load-clustering.mir
test/CodeGen/AMDGPU/fold-cndmask.mir
test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
test/CodeGen/AMDGPU/fold-multiple.mir
test/CodeGen/AMDGPU/fold-operands-order.mir
test/CodeGen/AMDGPU/hazard-inlineasm.mir
test/CodeGen/AMDGPU/hazard.mir
test/CodeGen/AMDGPU/insert-skips-kill-uncond.mir
test/CodeGen/AMDGPU/insert-waits-callee.mir
test/CodeGen/AMDGPU/insert-waits-exp.mir
test/CodeGen/AMDGPU/inserted-wait-states.mir
test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
test/CodeGen/AMDGPU/limit-coalesce.mir
test/CodeGen/AMDGPU/liveness.mir
test/CodeGen/AMDGPU/llvm.dbg.value.ll
test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir
test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir
test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir
test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
test/CodeGen/AMDGPU/merge-load-store-vreg.mir
test/CodeGen/AMDGPU/merge-load-store.mir
test/CodeGen/AMDGPU/merge-m0.mir
test/CodeGen/AMDGPU/misched-killflags.mir
test/CodeGen/AMDGPU/movrels-bug.mir
test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
test/CodeGen/AMDGPU/readlane_exec0.mir
test/CodeGen/AMDGPU/reduce-saveexec.mir
test/CodeGen/AMDGPU/regcoal-subrange-join.mir
test/CodeGen/AMDGPU/regcoalesce-dbg.mir
test/CodeGen/AMDGPU/regcoalesce-prune.mir
test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
test/CodeGen/AMDGPU/rename-independent-subregs.mir
test/CodeGen/AMDGPU/scalar-store-cache-flush.mir
test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
test/CodeGen/AMDGPU/schedule-regpressure.mir
test/CodeGen/AMDGPU/sdwa-gfx9.mir
test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
test/CodeGen/AMDGPU/sdwa-preserve.mir
test/CodeGen/AMDGPU/sdwa-scalar-ops.mir
test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir
test/CodeGen/AMDGPU/sendmsg-m0-hazard.mir
test/CodeGen/AMDGPU/shrink-carry.mir
test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll
test/CodeGen/AMDGPU/spill-empty-live-interval.mir
test/CodeGen/AMDGPU/splitkit.mir
test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
test/CodeGen/AMDGPU/subreg-intervals.mir
test/CodeGen/AMDGPU/subreg_interference.mir
test/CodeGen/AMDGPU/syncscopes.ll
test/CodeGen/AMDGPU/twoaddr-mad.mir
test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir
test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
test/CodeGen/AMDGPU/waitcnt-permute.mir
test/CodeGen/AMDGPU/waitcnt.mir
test/CodeGen/AMDGPU/wqm.mir
test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll
test/CodeGen/ARM/ARMLoadStoreDBG.mir
test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll
test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir
test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir
test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir
test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir
test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir
test/CodeGen/ARM/GlobalISel/select-pr35926.mir
test/CodeGen/ARM/PR32721_ifcvt_triangle_unanalyzable.mir
test/CodeGen/ARM/Windows/vla-cpsr.ll
test/CodeGen/ARM/cmp1-peephole-thumb.mir
test/CodeGen/ARM/cmp2-peephole-thumb.mir
test/CodeGen/ARM/constant-islands-cfg.mir
test/CodeGen/ARM/dbg-range-extension.mir
test/CodeGen/ARM/debug-info-arg.ll
test/CodeGen/ARM/debug-info-branch-folding.ll
test/CodeGen/ARM/expand-pseudos.mir
test/CodeGen/ARM/fpoffset_overflow.mir
test/CodeGen/ARM/ifcvt_canFallThroughTo.mir
test/CodeGen/ARM/ifcvt_diamond_unanalyzable.mir
test/CodeGen/ARM/ifcvt_forked_diamond_unanalyzable.mir
test/CodeGen/ARM/ifcvt_simple_bad_zero_prob_succ.mir
test/CodeGen/ARM/ifcvt_simple_unanalyzable.mir
test/CodeGen/ARM/ifcvt_triangleWoCvtToNextEdge.mir
test/CodeGen/ARM/imm-peephole-arm.mir
test/CodeGen/ARM/imm-peephole-thumb.mir
test/CodeGen/ARM/load_store_opt_kill.mir
test/CodeGen/ARM/machine-copyprop.mir
test/CodeGen/ARM/misched-int-basic-thumb2.mir
test/CodeGen/ARM/misched-int-basic.mir
test/CodeGen/ARM/peephole-phi.mir
test/CodeGen/ARM/pei-swiftself.mir
(708 more files...)
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