[PATCH] D35267: Pass Divergence Analysis data to selection DAG to drive divergence dependent instruction selection

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

In https://reviews.llvm.org/D35267#990432, @alex-t wrote:

> As I understand you are concerned about the mutating the SDNode after it has been created in getNode().


My most important concern is actually getting the modeling correct, so queries come up with the correct result when it gets queried by DAGCombine.  If the bit on the SDNode is just a cache which can be recomputed/verified, it's fine to mutate it when we need to.

> 1. FunctionLoweringInfo::ValueMap is created during the SelectionDAGBuilder walk through the BasicBlock. So we cannot query live-in register divergence from the CreateOperands => TargetLoweringInfo::isSDNodeSourceOfDivergence. By this point ValueMap has not yet been filled in.

Really?  I thought we fill it in before we actually start building the SelectionDAG (in FunctionLoweringInfo::set).  But you can move it earlier if you need to.

> All above means that we cannot just validate the flag values and assert if it does not match. We have to run iterative solver for each block just before the selection to count the control dependencies and to propagate the flag values.
> 
> I tried this approach and it works at a first glance.

Great!

> To meet this design we'd have to add similar hook to the TargetLoweringInfo interface. Is this feasible?

Yes, this should be fine.


https://reviews.llvm.org/D35267