[PATCH] D40343: AMDGPU: Do not combine loads/store across physreg defs

[Nicolai Hähnle via Phabricator via llvm-commits]

nhaehnle marked an inline comment as done.
nhaehnle added a comment.

I would like to commit this as-is, since it's a bug fix. I have a change which tracks def-use as well, I'll upload it in a moment as a related revision, and would like to commit it separately.



================
Comment at: lib/Target/AMDGPU/SILoadStoreOptimizer.cpp:359
+        // tracking physreg defs and uses. This should only affect M0 in
+        // practice.
+        return false;
----------------
arsenm wrote:
> nhaehnle wrote:
> > arsenm wrote:
> > > There could also be a call instruction, and the function may modify m0 or anything else
> > To clarify, this means that we should bail out entirely when we encounter a call instruction, right?
> I think this would just fall out naturally from physreg defs (although I guess you could have a void call that doesn't modify any visible registers), but you might need a call check
I've added a test case to ds_read2.ll. It passes without modifications to the code.


Repository:
  rL LLVM

https://reviews.llvm.org/D40343