[PATCH] D42615: [X86] Generate BT instrutions a bit more agressively

[Amaury SECHET via Phabricator via llvm-commits]

deadalnix added a comment.

Looks like this end up being a problem when the value is in EDI due to calling convention. So a few question come to mind:
1/ Shouldn't this optimization be done only after register allocation, if the selected register allows for it ? This would cause it to fail once in a while because the register allocator do not chose the proper register, but it's probably preferable to the extra copies.
2/ Is that possible to hint the register allocator that something is desirable ? For instance, that we would like this value to be in a `GR8_NOREX` register, but if that's not the case, don't create a copy for it ?


Repository:
  rL LLVM

https://reviews.llvm.org/D42615