[PATCH] D42615: [X86] Generate BT instrutions a bit more agressively

[Amaury SECHET via Phabricator via llvm-commits]

deadalnix created this revision.
deadalnix added reviewers: spatel, hfinkel, niravd, craig.topper, nhaehnle.

Right now, BT isntruction are inly generated when the constant cannot be materialized for a test instruction, and when the source is a (srl (and X, 1), N). This is fragile as any transform that get rid of the srl cause bt to not be materialized anymore. For instance anything (and X, 1 << N) will nto see the bt instruction used.

Because there are numerous pattern that match (and X, 1), bt is only generated when the bit position is greater than 0.


Repository:
  rL LLVM

https://reviews.llvm.org/D42615

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/and-sink.ll
  test/CodeGen/X86/and-su.ll
  test/CodeGen/X86/avx512-cmp.ll
  test/CodeGen/X86/btq.ll
  test/CodeGen/X86/select.ll
  test/CodeGen/X86/test-shrink.ll
  test/CodeGen/X86/testb-je-fusion.ll
  test/CodeGen/X86/use-add-flags.ll
  test/CodeGen/X86/vastart-defs-eflags.ll

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