[llvm] r323593 - Regenrate brcond.ll test results. NFC
Amaury Sechet via llvm-commits
llvm-commits at lists.llvm.org
Sat Jan 27 08:57:15 PST 2018
Author: deadalnix
Date: Sat Jan 27 08:57:15 2018
New Revision: 323593
URL: http://llvm.org/viewvc/llvm-project?rev=323593&view=rev
Log:
Regenrate brcond.ll test results. NFC
Modified:
llvm/trunk/test/CodeGen/X86/brcond.ll
Modified: llvm/trunk/test/CodeGen/X86/brcond.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/brcond.ll?rev=323593&r1=323592&r2=323593&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/brcond.ll (original)
+++ llvm/trunk/test/CodeGen/X86/brcond.ll Sat Jan 27 08:57:15 2018
@@ -1,14 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=penryn | FileCheck %s
; rdar://7475489
define i32 @test1(i32 %a, i32 %b) nounwind ssp {
-entry:
; CHECK-LABEL: test1:
-; CHECK: xorb
-; CHECK-NOT: andb
-; CHECK-NOT: shrb
-; CHECK: testb $64
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: movb {{[0-9]+}}(%esp), %al
+; CHECK-NEXT: xorb {{[0-9]+}}(%esp), %al
+; CHECK-NEXT: testb $64, %al
+; CHECK-NEXT: je LBB0_1
+; CHECK-NEXT: ## %bb.2: ## %bb1
+; CHECK-NEXT: jmp _bar ## TAILCALL
+; CHECK-NEXT: LBB0_1: ## %bb
+; CHECK-NEXT: jmp _foo ## TAILCALL
+entry:
%0 = and i32 %a, 16384
%1 = icmp ne i32 %0, 0
%2 = and i32 %b, 16384
@@ -40,13 +46,31 @@ declare i32 @bar(...)
; ...
;
; to:
-;
+;
; jnCC L2
; L1:
; ...
; L2:
; ...
define float @test4(float %x, float %y) nounwind readnone optsize ssp {
+; CHECK-LABEL: test4:
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: pushl %eax
+; CHECK-NEXT: cvtss2sd {{[0-9]+}}(%esp), %xmm1
+; CHECK-NEXT: cvtss2sd {{[0-9]+}}(%esp), %xmm0
+; CHECK-NEXT: mulsd %xmm1, %xmm0
+; CHECK-NEXT: xorpd %xmm1, %xmm1
+; CHECK-NEXT: ucomisd %xmm1, %xmm0
+; CHECK-NEXT: jne LBB1_1
+; CHECK-NEXT: jnp LBB1_2
+; CHECK-NEXT: LBB1_1: ## %bb1
+; CHECK-NEXT: addsd LCPI1_0, %xmm0
+; CHECK-NEXT: LBB1_2: ## %bb2
+; CHECK-NEXT: cvtsd2ss %xmm0, %xmm0
+; CHECK-NEXT: movss %xmm0, (%esp)
+; CHECK-NEXT: flds (%esp)
+; CHECK-NEXT: popl %eax
+; CHECK-NEXT: retl
entry:
%0 = fpext float %x to double ; <double> [#uses=1]
%1 = fpext float %y to double ; <double> [#uses=1]
@@ -54,10 +78,6 @@ entry:
%3 = fcmp oeq double %2, 0.000000e+00 ; <i1> [#uses=1]
br i1 %3, label %bb2, label %bb1
-; CHECK: jne
-; CHECK-NEXT: jnp
-; CHECK-NOT: jmp
-; CHECK: LBB
bb1: ; preds = %entry
%4 = fadd double %2, -1.000000e+00 ; <double> [#uses=1]
@@ -73,14 +93,22 @@ declare i32 @llvm.x86.sse41.ptestz(<4 x
declare i32 @llvm.x86.sse41.ptestc(<4 x float> %p1, <4 x float> %p2) nounwind
define <4 x float> @test5(<4 x float> %a, <4 x float> %b) nounwind {
-entry:
; CHECK-LABEL: test5:
-; CHECK: ptest
-; CHECK-NEXT: jne
-; CHECK: ret
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: ptest %xmm0, %xmm0
+; CHECK-NEXT: jne LBB2_2
+; CHECK-NEXT: ## %bb.1: ## %bb1
+; CHECK-NEXT: addps LCPI2_0, %xmm1
+; CHECK-NEXT: movaps %xmm1, %xmm0
+; CHECK-NEXT: retl
+; CHECK-NEXT: LBB2_2: ## %bb2
+; CHECK-NEXT: divps LCPI2_0, %xmm1
+; CHECK-NEXT: movaps %xmm1, %xmm0
+; CHECK-NEXT: retl
+entry:
- %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a, <4 x float> %a) nounwind
- %one = icmp ne i32 %res, 0
+ %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a, <4 x float> %a) nounwind
+ %one = icmp ne i32 %res, 0
br i1 %one, label %bb1, label %bb2
bb1:
@@ -97,14 +125,22 @@ return:
}
define <4 x float> @test7(<4 x float> %a, <4 x float> %b) nounwind {
-entry:
; CHECK-LABEL: test7:
-; CHECK: ptest
-; CHECK-NEXT: jne
-; CHECK: ret
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: ptest %xmm0, %xmm0
+; CHECK-NEXT: jne LBB3_2
+; CHECK-NEXT: ## %bb.1: ## %bb1
+; CHECK-NEXT: addps LCPI3_0, %xmm1
+; CHECK-NEXT: movaps %xmm1, %xmm0
+; CHECK-NEXT: retl
+; CHECK-NEXT: LBB3_2: ## %bb2
+; CHECK-NEXT: divps LCPI3_0, %xmm1
+; CHECK-NEXT: movaps %xmm1, %xmm0
+; CHECK-NEXT: retl
+entry:
- %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a, <4 x float> %a) nounwind
- %one = trunc i32 %res to i1
+ %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a, <4 x float> %a) nounwind
+ %one = trunc i32 %res to i1
br i1 %one, label %bb1, label %bb2
bb1:
@@ -121,14 +157,22 @@ return:
}
define <4 x float> @test8(<4 x float> %a, <4 x float> %b) nounwind {
-entry:
; CHECK-LABEL: test8:
-; CHECK: ptest
-; CHECK-NEXT: jae
-; CHECK: ret
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: ptest %xmm0, %xmm0
+; CHECK-NEXT: jae LBB4_2
+; CHECK-NEXT: ## %bb.1: ## %bb1
+; CHECK-NEXT: addps LCPI4_0, %xmm1
+; CHECK-NEXT: movaps %xmm1, %xmm0
+; CHECK-NEXT: retl
+; CHECK-NEXT: LBB4_2: ## %bb2
+; CHECK-NEXT: divps LCPI4_0, %xmm1
+; CHECK-NEXT: movaps %xmm1, %xmm0
+; CHECK-NEXT: retl
+entry:
- %res = call i32 @llvm.x86.sse41.ptestc(<4 x float> %a, <4 x float> %a) nounwind
- %one = icmp ne i32 %res, 0
+ %res = call i32 @llvm.x86.sse41.ptestc(<4 x float> %a, <4 x float> %a) nounwind
+ %one = icmp ne i32 %res, 0
br i1 %one, label %bb1, label %bb2
bb1:
@@ -145,14 +189,22 @@ return:
}
define <4 x float> @test10(<4 x float> %a, <4 x float> %b) nounwind {
-entry:
; CHECK-LABEL: test10:
-; CHECK: ptest
-; CHECK-NEXT: jae
-; CHECK: ret
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: ptest %xmm0, %xmm0
+; CHECK-NEXT: jae LBB5_2
+; CHECK-NEXT: ## %bb.1: ## %bb1
+; CHECK-NEXT: addps LCPI5_0, %xmm1
+; CHECK-NEXT: movaps %xmm1, %xmm0
+; CHECK-NEXT: retl
+; CHECK-NEXT: LBB5_2: ## %bb2
+; CHECK-NEXT: divps LCPI5_0, %xmm1
+; CHECK-NEXT: movaps %xmm1, %xmm0
+; CHECK-NEXT: retl
+entry:
- %res = call i32 @llvm.x86.sse41.ptestc(<4 x float> %a, <4 x float> %a) nounwind
- %one = trunc i32 %res to i1
+ %res = call i32 @llvm.x86.sse41.ptestc(<4 x float> %a, <4 x float> %a) nounwind
+ %one = trunc i32 %res to i1
br i1 %one, label %bb1, label %bb2
bb1:
@@ -169,14 +221,22 @@ return:
}
define <4 x float> @test11(<4 x float> %a, <4 x float> %b) nounwind {
-entry:
; CHECK-LABEL: test11:
-; CHECK: ptest
-; CHECK-NEXT: jne
-; CHECK: ret
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: ptest %xmm0, %xmm0
+; CHECK-NEXT: jne LBB6_2
+; CHECK-NEXT: ## %bb.1: ## %bb1
+; CHECK-NEXT: addps LCPI6_0, %xmm1
+; CHECK-NEXT: movaps %xmm1, %xmm0
+; CHECK-NEXT: retl
+; CHECK-NEXT: LBB6_2: ## %bb2
+; CHECK-NEXT: divps LCPI6_0, %xmm1
+; CHECK-NEXT: movaps %xmm1, %xmm0
+; CHECK-NEXT: retl
+entry:
- %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a, <4 x float> %a) nounwind
- %one = icmp eq i32 %res, 1
+ %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a, <4 x float> %a) nounwind
+ %one = icmp eq i32 %res, 1
br i1 %one, label %bb1, label %bb2
bb1:
@@ -193,14 +253,22 @@ return:
}
define <4 x float> @test12(<4 x float> %a, <4 x float> %b) nounwind {
-entry:
; CHECK-LABEL: test12:
-; CHECK: ptest
-; CHECK-NEXT: je
-; CHECK: ret
+; CHECK: ## %bb.0: ## %entry
+; CHECK-NEXT: ptest %xmm0, %xmm0
+; CHECK-NEXT: je LBB7_2
+; CHECK-NEXT: ## %bb.1: ## %bb1
+; CHECK-NEXT: addps LCPI7_0, %xmm1
+; CHECK-NEXT: movaps %xmm1, %xmm0
+; CHECK-NEXT: retl
+; CHECK-NEXT: LBB7_2: ## %bb2
+; CHECK-NEXT: divps LCPI7_0, %xmm1
+; CHECK-NEXT: movaps %xmm1, %xmm0
+; CHECK-NEXT: retl
+entry:
- %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a, <4 x float> %a) nounwind
- %one = icmp ne i32 %res, 1
+ %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a, <4 x float> %a) nounwind
+ %one = icmp ne i32 %res, 1
br i1 %one, label %bb1, label %bb2
bb1:
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