[PATCH] D42574: [ARM] Lower lower saturate to 0 and lower saturate to -1 using bit-operations

[Pablo Barrio via Phabricator via llvm-commits]

pbarrio requested changes to this revision.
pbarrio added a comment.
This revision now requires changes to proceed.

The logic & testing LGTM. Just a couple of coding standard nits.



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Comment at: lib/Target/ARM/ARMISelLowering.cpp:4386
+
+    SDValue shiftV = DAG.getNode(ISD::SRA, dl, VT, V, DAG.getConstant(31, dl, VT));
+    if (KVal == 0) {
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Variable names should start with uppercase (see https://llvm.org/docs/CodingStandards.html, "Name Types, Functions, Variables, and Enumerators Properly")


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Comment at: lib/Target/ARM/ARMISelLowering.cpp:4388
+    if (KVal == 0) {
+      SDValue not_shiftV = DAG.getNode(ISD::XOR, dl, VT, shiftV, DAG.getConstant(-1, dl, VT));
+      return DAG.getNode(ISD::AND, dl, VT, V, not_shiftV);
----------------
Same here: upper case + camel case, i.e. NotShiftV


Repository:
  rL LLVM

https://reviews.llvm.org/D42574