[llvm] r323514 - [ARM] Accept a subset of Thumb GPR register class when emitting an SP-relative

[Momchil Velikov via llvm-commits]

Author: chill
Date: Fri Jan 26 02:20:58 2018
New Revision: 323514

URL: http://llvm.org/viewvc/llvm-project?rev=323514&view=rev
Log:
[ARM] Accept a subset of Thumb GPR register class when emitting an SP-relative
load instruction

The function `Thumb1InstrInfo::loadRegFromStackSlot` accepts only the `tGPR`
register class. The function serves to emit a `tLDRspi` instruction and
certainly any subset of the `tGPR` register class is a valid destination of the
load.

Differential revision: https://reviews.llvm.org/D42535

Modified:
    llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
    llvm/trunk/test/CodeGen/ARM/v8m-tail-call.ll

Modified: llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp?rev=323514&r1=323513&r2=323514&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp Fri Jan 26 02:20:58 2018
@@ -109,11 +109,11 @@ loadRegFromStackSlot(MachineBasicBlock &
                      unsigned DestReg, int FI,
                      const TargetRegisterClass *RC,
                      const TargetRegisterInfo *TRI) const {
-  assert((RC == &ARM::tGPRRegClass ||
+  assert((RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
           (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
            isARMLowRegister(DestReg))) && "Unknown regclass!");
 
-  if (RC == &ARM::tGPRRegClass ||
+  if (RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
       (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
        isARMLowRegister(DestReg))) {
     DebugLoc DL;

Modified: llvm/trunk/test/CodeGen/ARM/v8m-tail-call.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/v8m-tail-call.ll?rev=323514&r1=323513&r2=323514&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/v8m-tail-call.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/v8m-tail-call.ll Fri Jan 26 02:20:58 2018
@@ -103,3 +103,28 @@ define i32 @test7() {
 }
 
 declare i32 @bar(i32, i32, i32, i32)
+
+; Regression test for failure to load indirect branch target (class tcGPR) from
+; a stack slot.
+%struct.S = type { i32 }
+
+define void @test8(i32 (i32, i32, i32)* nocapture %fn, i32 %x) local_unnamed_addr {
+entry:
+  %call = tail call %struct.S* bitcast (%struct.S* (...)* @test8_u to %struct.S* ()*)()
+  %a = getelementptr inbounds %struct.S, %struct.S* %call, i32 0, i32 0
+  %0 = load i32, i32* %a, align 4
+  %call1 = tail call i32 @test8_h(i32 0)
+  %call2 = tail call i32 @test8_g(i32 %0, i32 %call1, i32 0)
+  store i32 %x, i32* %a, align 4
+  %call4 = tail call i32 %fn(i32 1, i32 2, i32 3)
+  ret void
+}
+
+declare %struct.S* @test8_u(...)
+
+declare i32 @test8_g(i32, i32, i32)
+
+declare i32 @test8_h(i32)
+; CHECK: str r0, [sp] @ 4-byte Spill
+; CHECK: ldr r3, [sp] @ 4-byte Reload
+; CHECK: bx r3