[PATCH] D42565: [ARM][GISel] PR35965 Constrain RegClasses of nested instructions built from Dst Patter

[Roman Tereshin via Phabricator via llvm-commits]

rtereshin created this revision.
rtereshin added reviewers: dsanders, qcolombet, rovka, bogner, aditya_nandakumar, volkan.
Herald added subscribers: llvm-commits, kristof.beyls, javed.absar, aemerson.

Apparently, we missed on constraining register classes of VReg-operands of all the instructions
built from a destination pattern but the root (top-level) one. The issue exposed itself
while selecting G_FPTOSI for armv7: the corresponding pattern generates VTOSIZS wrapped
into COPY_TO_REGCLASS, so top-level COPY_TO_REGCLASS gets properly constrained,
while nested VTOSIZS (or rather its destination virtual register to be exact) does not.

Fixing this by issuing GIR_ConstrainSelectedInstOperands for every nested GIR_BuildMI.

https://bugs.llvm.org/show_bug.cgi?id=35965
rdar://problem/36886530


Repository:
  rL LLVM

https://reviews.llvm.org/D42565

Files:
  lib/CodeGen/GlobalISel/Utils.cpp
  lib/Target/ARM/ARMLegalizerInfo.cpp
  test/CodeGen/ARM/GlobalISel/arm-select-fptosi-pr35965.mir
  test/TableGen/GlobalISelEmitter.td
  utils/TableGen/GlobalISelEmitter.cpp

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