[llvm] r323438 - Revert "[Hexagon] Replace EmitFunctionEntryCode with a DAG preprocessing code"

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Thu Jan 25 08:36:53 2018
New Revision: 323438

URL: http://llvm.org/viewvc/llvm-project?rev=323438&view=rev
Log:
Revert "[Hexagon] Replace EmitFunctionEntryCode with a DAG preprocessing code"

This reverts r323374. The fix needs a different approach.

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
    llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.h

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp?rev=323438&r1=323437&r2=323438&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp Thu Jan 25 08:36:53 2018
@@ -1034,23 +1034,6 @@ void HexagonDAGToDAGISel::ppHoistZextI1(
   }
 }
 
-void HexagonDAGToDAGISel::ppEmitAligna() {
-  auto &HST = static_cast<const HexagonSubtarget&>(MF->getSubtarget());
-  auto &HFI = *HST.getFrameLowering();
-  if (!HFI.needsAligna(*MF))
-    return;
-
-  MachineFrameInfo &MFI = MF->getFrameInfo();
-  MachineBasicBlock &EntryBB = MF->front();
-  unsigned AR = FuncInfo->CreateReg(MVT::i32);
-  unsigned MaxA = MFI.getMaxAlignment();
-  MachineBasicBlock::iterator End = EntryBB.end();
-  DebugLoc DL = EntryBB.findDebugLoc(End);
-  BuildMI(EntryBB, End, DL, HII->get(Hexagon::PS_aligna), AR)
-      .addImm(MaxA);
-  MF->getInfo<HexagonMachineFunctionInfo>()->setStackAlignBaseVReg(AR);
-}
-
 void HexagonDAGToDAGISel::PreprocessISelDAG() {
   // Repack all nodes before calling each preprocessing function,
   // because each of them can modify the set of nodes.
@@ -1106,11 +1089,21 @@ void HexagonDAGToDAGISel::PreprocessISel
       CurDAG->dump();
     });
   }
+}
+
+void HexagonDAGToDAGISel::EmitFunctionEntryCode() {
+  auto &HST = static_cast<const HexagonSubtarget&>(MF->getSubtarget());
+  auto &HFI = *HST.getFrameLowering();
+  if (!HFI.needsAligna(*MF))
+    return;
 
-  // Finally, emit the PS_aligna instruction, if necessary. Do it late,
-  // because the max required stack layout may change up until right before
-  // instruction selection.
-  ppEmitAligna();
+  MachineFrameInfo &MFI = MF->getFrameInfo();
+  MachineBasicBlock *EntryBB = &MF->front();
+  unsigned AR = FuncInfo->CreateReg(MVT::i32);
+  unsigned MaxA = MFI.getMaxAlignment();
+  BuildMI(EntryBB, DebugLoc(), HII->get(Hexagon::PS_aligna), AR)
+      .addImm(MaxA);
+  MF->getInfo<HexagonMachineFunctionInfo>()->setStackAlignBaseVReg(AR);
 }
 
 // Match a frame index that can be used in an addressing mode.

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.h?rev=323438&r1=323437&r2=323438&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.h Thu Jan 25 08:36:53 2018
@@ -51,6 +51,8 @@ public:
     return true;
   }
   void PreprocessISelDAG() override;
+  void EmitFunctionEntryCode() override;
+
   void Select(SDNode *N) override;
 
   // Complex Pattern Selectors.
@@ -137,7 +139,6 @@ private:
   void ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes);
   void ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes);
   void ppHoistZextI1(std::vector<SDNode*> &&Nodes);
-  void ppEmitAligna();
 
   SmallDenseMap<SDNode *,int> RootWeights;
   SmallDenseMap<SDNode *,int> RootHeights;