[llvm] r323352 - [X86] Adjust names of PINSRW/PEXTRW intructions between MMX/SSE/AVX/AVX512 for consistency and to maybe enable more regular expression compaction in the scheduler models. NFCI
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 24 09:58:52 PST 2018
Author: ctopper
Date: Wed Jan 24 09:58:51 2018
New Revision: 323352
URL: http://llvm.org/viewvc/llvm-project?rev=323352&view=rev
Log:
[X86] Adjust names of PINSRW/PEXTRW intructions between MMX/SSE/AVX/AVX512 for consistency and to maybe enable more regular expression compaction in the scheduler models. NFCI
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/lib/Target/X86/X86InstrMMX.td
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
llvm/trunk/test/CodeGen/X86/evex-to-vex-compress.mir
llvm/trunk/test/MC/X86/x86_64-asm-match.s
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=323352&r1=323351&r2=323352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Wed Jan 24 09:58:51 2018
@@ -1317,7 +1317,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::PINSRBrr, X86::PINSRBrm, 0 },
{ X86::PINSRDrr, X86::PINSRDrm, 0 },
{ X86::PINSRQrr, X86::PINSRQrm, 0 },
- { X86::PINSRWrri, X86::PINSRWrmi, 0 },
+ { X86::PINSRWrr, X86::PINSRWrm, 0 },
{ X86::PMADDUBSWrr, X86::PMADDUBSWrm, TB_ALIGN_16 },
{ X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
{ X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 },
@@ -1430,7 +1430,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::MMX_PHSUBDrr64, X86::MMX_PHSUBDrm64, 0 },
{ X86::MMX_PHSUBSWrr64, X86::MMX_PHSUBSWrm64, 0 },
{ X86::MMX_PHSUBWrr64, X86::MMX_PHSUBWrm64, 0 },
- { X86::MMX_PINSRWirri, X86::MMX_PINSRWirmi, 0 },
+ { X86::MMX_PINSRWrr, X86::MMX_PINSRWrm, 0 },
{ X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
{ X86::MMX_PMADDWDirr, X86::MMX_PMADDWDirm, 0 },
{ X86::MMX_PMAXSWirr, X86::MMX_PMAXSWirm, 0 },
@@ -1603,7 +1603,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
{ X86::VPINSRBrr, X86::VPINSRBrm, 0 },
{ X86::VPINSRDrr, X86::VPINSRDrm, 0 },
{ X86::VPINSRQrr, X86::VPINSRQrm, 0 },
- { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
+ { X86::VPINSRWrr, X86::VPINSRWrm, 0 },
{ X86::VPMADDUBSWrr, X86::VPMADDUBSWrm, 0 },
{ X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
{ X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=323352&r1=323351&r2=323352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Wed Jan 24 09:58:51 2018
@@ -599,30 +599,30 @@ let Constraints = "$src1 = $dst" in {
// Extract / Insert
let Predicates = [HasSSE1] in
-def MMX_PEXTRWirri: MMXIi8<0xC5, MRMSrcReg,
- (outs GR32orGR64:$dst), (ins VR64:$src1, i32u8imm:$src2),
- "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
- [(set GR32orGR64:$dst, (int_x86_mmx_pextr_w VR64:$src1,
- imm:$src2))],
- IIC_MMX_PEXTR>, Sched<[WriteShuffle]>;
+def MMX_PEXTRWrr: MMXIi8<0xC5, MRMSrcReg,
+ (outs GR32orGR64:$dst), (ins VR64:$src1, i32u8imm:$src2),
+ "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+ [(set GR32orGR64:$dst, (int_x86_mmx_pextr_w VR64:$src1,
+ imm:$src2))],
+ IIC_MMX_PEXTR>, Sched<[WriteShuffle]>;
let Constraints = "$src1 = $dst" in {
let Predicates = [HasSSE1] in {
- def MMX_PINSRWirri : MMXIi8<0xC4, MRMSrcReg,
- (outs VR64:$dst),
- (ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3),
- "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
- [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
- GR32orGR64:$src2, imm:$src3))],
- IIC_MMX_PINSRW>, Sched<[WriteShuffle]>;
+ def MMX_PINSRWrr : MMXIi8<0xC4, MRMSrcReg,
+ (outs VR64:$dst),
+ (ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3),
+ "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
+ [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
+ GR32orGR64:$src2, imm:$src3))],
+ IIC_MMX_PINSRW>, Sched<[WriteShuffle]>;
- def MMX_PINSRWirmi : MMXIi8<0xC4, MRMSrcMem,
- (outs VR64:$dst),
- (ins VR64:$src1, i16mem:$src2, i32u8imm:$src3),
- "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
- [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
- (i32 (anyext (loadi16 addr:$src2))),
- imm:$src3))],
- IIC_MMX_PINSRW>, Sched<[WriteShuffleLd, ReadAfterLd]>;
+ def MMX_PINSRWrm : MMXIi8<0xC4, MRMSrcMem,
+ (outs VR64:$dst),
+ (ins VR64:$src1, i16mem:$src2, i32u8imm:$src3),
+ "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
+ [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
+ (i32 (anyext (loadi16 addr:$src2))),
+ imm:$src3))],
+ IIC_MMX_PINSRW>, Sched<[WriteShuffleLd, ReadAfterLd]>;
}
}
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=323352&r1=323351&r2=323352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jan 24 09:58:51 2018
@@ -4234,7 +4234,7 @@ let Constraints = "$src1 = $dst" in {
let ExeDomain = SSEPackedInt in {
multiclass sse2_pinsrw<bit Is2Addr = 1> {
- def rri : Ii8<0xC4, MRMSrcReg,
+ def rr : Ii8<0xC4, MRMSrcReg,
(outs VR128:$dst), (ins VR128:$src1,
GR32orGR64:$src2, u8imm:$src3),
!if(Is2Addr,
@@ -4243,9 +4243,9 @@ multiclass sse2_pinsrw<bit Is2Addr = 1>
[(set VR128:$dst,
(X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
- def rmi : Ii8<0xC4, MRMSrcMem,
- (outs VR128:$dst), (ins VR128:$src1,
- i16mem:$src2, u8imm:$src3),
+ def rm : Ii8<0xC4, MRMSrcMem,
+ (outs VR128:$dst), (ins VR128:$src1,
+ i16mem:$src2, u8imm:$src3),
!if(Is2Addr,
"pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
"vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
@@ -4257,13 +4257,13 @@ multiclass sse2_pinsrw<bit Is2Addr = 1>
// Extract
let Predicates = [HasAVX, NoBWI] in
-def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
+def VPEXTRWrr : Ii8<0xC5, MRMSrcReg,
(outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
"vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
[(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
imm:$src2))]>, PD, VEX,
Sched<[WriteShuffle]>;
-def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
+def PEXTRWrr : PDIi8<0xC5, MRMSrcReg,
(outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
"pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
[(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=323352&r1=323351&r2=323352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Wed Jan 24 09:58:51 2018
@@ -994,12 +994,12 @@ def BWWriteResGroup11 : SchedWriteRes<[B
}
def: InstRW<[BWWriteResGroup11], (instregex "BLENDVPDrr0")>;
def: InstRW<[BWWriteResGroup11], (instregex "BLENDVPSrr0")>;
-def: InstRW<[BWWriteResGroup11], (instregex "MMX_PINSRWirri")>;
+def: InstRW<[BWWriteResGroup11], (instregex "MMX_PINSRWrr")>;
def: InstRW<[BWWriteResGroup11], (instregex "PBLENDVBrr0")>;
def: InstRW<[BWWriteResGroup11], (instregex "PINSRBrr")>;
def: InstRW<[BWWriteResGroup11], (instregex "PINSRDrr")>;
def: InstRW<[BWWriteResGroup11], (instregex "PINSRQrr")>;
-def: InstRW<[BWWriteResGroup11], (instregex "PINSRWrri")>;
+def: InstRW<[BWWriteResGroup11], (instregex "PINSRWrr")>;
def: InstRW<[BWWriteResGroup11], (instregex "VBLENDVPDYrr")>;
def: InstRW<[BWWriteResGroup11], (instregex "VBLENDVPDrr")>;
def: InstRW<[BWWriteResGroup11], (instregex "VBLENDVPSYrr")>;
@@ -1009,7 +1009,7 @@ def: InstRW<[BWWriteResGroup11], (instre
def: InstRW<[BWWriteResGroup11], (instregex "VPINSRBrr")>;
def: InstRW<[BWWriteResGroup11], (instregex "VPINSRDrr")>;
def: InstRW<[BWWriteResGroup11], (instregex "VPINSRQrr")>;
-def: InstRW<[BWWriteResGroup11], (instregex "VPINSRWrri")>;
+def: InstRW<[BWWriteResGroup11], (instregex "VPINSRWrr")>;
def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
let Latency = 2;
@@ -1050,12 +1050,11 @@ def BWWriteResGroup15 : SchedWriteRes<[B
def: InstRW<[BWWriteResGroup15], (instregex "CVTPS2PDrr")>;
def: InstRW<[BWWriteResGroup15], (instregex "CVTSS2SDrr")>;
def: InstRW<[BWWriteResGroup15], (instregex "EXTRACTPSrr")>;
-def: InstRW<[BWWriteResGroup15], (instregex "MMX_PEXTRWirri")>;
+def: InstRW<[BWWriteResGroup15], (instregex "MMX_PEXTRWrr")>;
def: InstRW<[BWWriteResGroup15], (instregex "PEXTRBrr")>;
def: InstRW<[BWWriteResGroup15], (instregex "PEXTRDrr")>;
def: InstRW<[BWWriteResGroup15], (instregex "PEXTRQrr")>;
-def: InstRW<[BWWriteResGroup15], (instregex "PEXTRWri")>;
-def: InstRW<[BWWriteResGroup15], (instregex "PEXTRWrr_REV")>;
+def: InstRW<[BWWriteResGroup15], (instregex "PEXTRWrr")>;
def: InstRW<[BWWriteResGroup15], (instregex "PSLLDrr")>;
def: InstRW<[BWWriteResGroup15], (instregex "PSLLQrr")>;
def: InstRW<[BWWriteResGroup15], (instregex "PSLLWrr")>;
@@ -1073,8 +1072,7 @@ def: InstRW<[BWWriteResGroup15], (instre
def: InstRW<[BWWriteResGroup15], (instregex "VPEXTRBrr")>;
def: InstRW<[BWWriteResGroup15], (instregex "VPEXTRDrr")>;
def: InstRW<[BWWriteResGroup15], (instregex "VPEXTRQrr")>;
-def: InstRW<[BWWriteResGroup15], (instregex "VPEXTRWri")>;
-def: InstRW<[BWWriteResGroup15], (instregex "VPEXTRWrr_REV")>;
+def: InstRW<[BWWriteResGroup15], (instregex "VPEXTRWrr")>;
def: InstRW<[BWWriteResGroup15], (instregex "VPSLLDrr")>;
def: InstRW<[BWWriteResGroup15], (instregex "VPSLLQrr")>;
def: InstRW<[BWWriteResGroup15], (instregex "VPSLLWrr")>;
@@ -1870,7 +1868,7 @@ def: InstRW<[BWWriteResGroup61], (instre
def: InstRW<[BWWriteResGroup61], (instregex "ANDPSrm")>;
def: InstRW<[BWWriteResGroup61], (instregex "INSERTPSrm")>;
def: InstRW<[BWWriteResGroup61], (instregex "MMX_PALIGNR64irm")>;
-def: InstRW<[BWWriteResGroup61], (instregex "MMX_PINSRWirmi")>;
+def: InstRW<[BWWriteResGroup61], (instregex "MMX_PINSRWrm")>;
def: InstRW<[BWWriteResGroup61], (instregex "MMX_PSHUFBrm64")>;
def: InstRW<[BWWriteResGroup61], (instregex "MMX_PSHUFWmi")>;
def: InstRW<[BWWriteResGroup61], (instregex "MMX_PUNPCKHBWirm")>;
@@ -1894,7 +1892,7 @@ def: InstRW<[BWWriteResGroup61], (instre
def: InstRW<[BWWriteResGroup61], (instregex "PINSRBrm")>;
def: InstRW<[BWWriteResGroup61], (instregex "PINSRDrm")>;
def: InstRW<[BWWriteResGroup61], (instregex "PINSRQrm")>;
-def: InstRW<[BWWriteResGroup61], (instregex "PINSRWrmi")>;
+def: InstRW<[BWWriteResGroup61], (instregex "PINSRWrm")>;
def: InstRW<[BWWriteResGroup61], (instregex "PMOVSXBDrm")>;
def: InstRW<[BWWriteResGroup61], (instregex "PMOVSXBQrm")>;
def: InstRW<[BWWriteResGroup61], (instregex "PMOVSXBWrm")>;
@@ -1949,7 +1947,7 @@ def: InstRW<[BWWriteResGroup61], (instre
def: InstRW<[BWWriteResGroup61], (instregex "VPINSRBrm")>;
def: InstRW<[BWWriteResGroup61], (instregex "VPINSRDrm")>;
def: InstRW<[BWWriteResGroup61], (instregex "VPINSRQrm")>;
-def: InstRW<[BWWriteResGroup61], (instregex "VPINSRWrmi")>;
+def: InstRW<[BWWriteResGroup61], (instregex "VPINSRWrm")>;
def: InstRW<[BWWriteResGroup61], (instregex "VPMOVSXBDrm")>;
def: InstRW<[BWWriteResGroup61], (instregex "VPMOVSXBQrm")>;
def: InstRW<[BWWriteResGroup61], (instregex "VPMOVSXBWrm")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=323352&r1=323351&r2=323352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Wed Jan 24 09:58:51 2018
@@ -1708,7 +1708,7 @@ def HWWriteResGroup13_2 : SchedWriteRes<
let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PALIGNR64irm")>;
-def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PINSRWirmi")>;
+def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PINSRWrm")>;
def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PSHUFBrm64")>;
def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PSHUFWmi")>;
def: InstRW<[HWWriteResGroup13_2], (instregex "MMX_PUNPCKHBWirm")>;
@@ -1724,7 +1724,7 @@ def: InstRW<[HWWriteResGroup13_2], (inst
def: InstRW<[HWWriteResGroup13_2], (instregex "PINSRBrm")>;
def: InstRW<[HWWriteResGroup13_2], (instregex "PINSRDrm")>;
def: InstRW<[HWWriteResGroup13_2], (instregex "PINSRQrm")>;
-def: InstRW<[HWWriteResGroup13_2], (instregex "PINSRWrmi")>;
+def: InstRW<[HWWriteResGroup13_2], (instregex "PINSRWrm")>;
def: InstRW<[HWWriteResGroup13_2], (instregex "PMOVSXBDrm")>;
def: InstRW<[HWWriteResGroup13_2], (instregex "PMOVSXBQrm")>;
def: InstRW<[HWWriteResGroup13_2], (instregex "PMOVSXBWrm")>;
@@ -1744,7 +1744,7 @@ def: InstRW<[HWWriteResGroup13_2], (inst
def: InstRW<[HWWriteResGroup13_2], (instregex "VPINSRBrm")>;
def: InstRW<[HWWriteResGroup13_2], (instregex "VPINSRDrm")>;
def: InstRW<[HWWriteResGroup13_2], (instregex "VPINSRQrm")>;
-def: InstRW<[HWWriteResGroup13_2], (instregex "VPINSRWrmi")>;
+def: InstRW<[HWWriteResGroup13_2], (instregex "VPINSRWrm")>;
def: InstRW<[HWWriteResGroup13_2], (instregex "VPMOVSXBDrm")>;
def: InstRW<[HWWriteResGroup13_2], (instregex "VPMOVSXBQrm")>;
def: InstRW<[HWWriteResGroup13_2], (instregex "VPMOVSXBWrm")>;
@@ -2167,12 +2167,12 @@ def HWWriteResGroup27 : SchedWriteRes<[H
}
def: InstRW<[HWWriteResGroup27], (instregex "BLENDVPDrr0")>;
def: InstRW<[HWWriteResGroup27], (instregex "BLENDVPSrr0")>;
-def: InstRW<[HWWriteResGroup27], (instregex "MMX_PINSRWirri")>;
+def: InstRW<[HWWriteResGroup27], (instregex "MMX_PINSRWrr")>;
def: InstRW<[HWWriteResGroup27], (instregex "PBLENDVBrr0")>;
def: InstRW<[HWWriteResGroup27], (instregex "PINSRBrr")>;
def: InstRW<[HWWriteResGroup27], (instregex "PINSRDrr")>;
def: InstRW<[HWWriteResGroup27], (instregex "PINSRQrr")>;
-def: InstRW<[HWWriteResGroup27], (instregex "PINSRWrri")>;
+def: InstRW<[HWWriteResGroup27], (instregex "PINSRWrr")>;
def: InstRW<[HWWriteResGroup27], (instregex "VBLENDVPDYrr")>;
def: InstRW<[HWWriteResGroup27], (instregex "VBLENDVPDrr")>;
def: InstRW<[HWWriteResGroup27], (instregex "VBLENDVPSYrr")>;
@@ -2182,7 +2182,7 @@ def: InstRW<[HWWriteResGroup27], (instre
def: InstRW<[HWWriteResGroup27], (instregex "VPINSRBrr")>;
def: InstRW<[HWWriteResGroup27], (instregex "VPINSRDrr")>;
def: InstRW<[HWWriteResGroup27], (instregex "VPINSRQrr")>;
-def: InstRW<[HWWriteResGroup27], (instregex "VPINSRWrri")>;
+def: InstRW<[HWWriteResGroup27], (instregex "VPINSRWrr")>;
def HWWriteResGroup28 : SchedWriteRes<[HWPort01]> {
let Latency = 2;
@@ -2223,12 +2223,11 @@ def HWWriteResGroup31 : SchedWriteRes<[H
def: InstRW<[HWWriteResGroup31], (instregex "CVTPS2PDrr")>;
def: InstRW<[HWWriteResGroup31], (instregex "CVTSS2SDrr")>;
def: InstRW<[HWWriteResGroup31], (instregex "EXTRACTPSrr")>;
-def: InstRW<[HWWriteResGroup31], (instregex "MMX_PEXTRWirri")>;
+def: InstRW<[HWWriteResGroup31], (instregex "MMX_PEXTRWrr")>;
def: InstRW<[HWWriteResGroup31], (instregex "PEXTRBrr")>;
def: InstRW<[HWWriteResGroup31], (instregex "PEXTRDrr")>;
def: InstRW<[HWWriteResGroup31], (instregex "PEXTRQrr")>;
-def: InstRW<[HWWriteResGroup31], (instregex "PEXTRWri")>;
-def: InstRW<[HWWriteResGroup31], (instregex "PEXTRWrr_REV")>;
+def: InstRW<[HWWriteResGroup31], (instregex "PEXTRWrr")>;
def: InstRW<[HWWriteResGroup31], (instregex "PSLLDrr")>;
def: InstRW<[HWWriteResGroup31], (instregex "PSLLQrr")>;
def: InstRW<[HWWriteResGroup31], (instregex "PSLLWrr")>;
@@ -2246,8 +2245,7 @@ def: InstRW<[HWWriteResGroup31], (instre
def: InstRW<[HWWriteResGroup31], (instregex "VPEXTRBrr")>;
def: InstRW<[HWWriteResGroup31], (instregex "VPEXTRDrr")>;
def: InstRW<[HWWriteResGroup31], (instregex "VPEXTRQrr")>;
-def: InstRW<[HWWriteResGroup31], (instregex "VPEXTRWri")>;
-def: InstRW<[HWWriteResGroup31], (instregex "VPEXTRWrr_REV")>;
+def: InstRW<[HWWriteResGroup31], (instregex "VPEXTRWrr")>;
def: InstRW<[HWWriteResGroup31], (instregex "VPSLLDrr")>;
def: InstRW<[HWWriteResGroup31], (instregex "VPSLLQrr")>;
def: InstRW<[HWWriteResGroup31], (instregex "VPSLLWrr")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=323352&r1=323351&r2=323352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Wed Jan 24 09:58:51 2018
@@ -840,11 +840,11 @@ def SBWriteResGroup17 : SchedWriteRes<[S
def: InstRW<[SBWriteResGroup17], (instregex "PINSRBrr")>;
def: InstRW<[SBWriteResGroup17], (instregex "PINSRDrr")>;
def: InstRW<[SBWriteResGroup17], (instregex "PINSRQrr")>;
-def: InstRW<[SBWriteResGroup17], (instregex "PINSRWrri")>;
+def: InstRW<[SBWriteResGroup17], (instregex "PINSRWrr")>;
def: InstRW<[SBWriteResGroup17], (instregex "VPINSRBrr")>;
def: InstRW<[SBWriteResGroup17], (instregex "VPINSRDrr")>;
def: InstRW<[SBWriteResGroup17], (instregex "VPINSRQrr")>;
-def: InstRW<[SBWriteResGroup17], (instregex "VPINSRWrri")>;
+def: InstRW<[SBWriteResGroup17], (instregex "VPINSRWrr")>;
def SBWriteResGroup18 : SchedWriteRes<[SBPort5,SBPort015]> {
let Latency = 2;
@@ -1016,11 +1016,11 @@ def SBWriteResGroup23 : SchedWriteRes<[S
def: InstRW<[SBWriteResGroup23], (instregex "PEXTRBrr")>;
def: InstRW<[SBWriteResGroup23], (instregex "PEXTRDrr")>;
def: InstRW<[SBWriteResGroup23], (instregex "PEXTRQrr")>;
-def: InstRW<[SBWriteResGroup23], (instregex "PEXTRWri")>;
+def: InstRW<[SBWriteResGroup23], (instregex "PEXTRWrr")>;
def: InstRW<[SBWriteResGroup23], (instregex "VPEXTRBrr")>;
def: InstRW<[SBWriteResGroup23], (instregex "VPEXTRDrr")>;
def: InstRW<[SBWriteResGroup23], (instregex "VPEXTRQrr")>;
-def: InstRW<[SBWriteResGroup23], (instregex "VPEXTRWri")>;
+def: InstRW<[SBWriteResGroup23], (instregex "VPEXTRWrr")>;
def SBWriteResGroup23_2 : SchedWriteRes<[SBPort05]> {
let Latency = 3;
@@ -1680,7 +1680,7 @@ def: InstRW<[SBWriteResGroup59], (instre
def: InstRW<[SBWriteResGroup59], (instregex "PINSRBrm")>;
def: InstRW<[SBWriteResGroup59], (instregex "PINSRDrm")>;
def: InstRW<[SBWriteResGroup59], (instregex "PINSRQrm")>;
-def: InstRW<[SBWriteResGroup59], (instregex "PINSRWrmi")>;
+def: InstRW<[SBWriteResGroup59], (instregex "PINSRWrm")>;
def: InstRW<[SBWriteResGroup59], (instregex "PMAXSBrm")>;
def: InstRW<[SBWriteResGroup59], (instregex "PMAXSDrm")>;
def: InstRW<[SBWriteResGroup59], (instregex "PMAXSWrm")>;
@@ -1757,7 +1757,7 @@ def: InstRW<[SBWriteResGroup59], (instre
def: InstRW<[SBWriteResGroup59], (instregex "VPINSRBrm")>;
def: InstRW<[SBWriteResGroup59], (instregex "VPINSRDrm")>;
def: InstRW<[SBWriteResGroup59], (instregex "VPINSRQrm")>;
-def: InstRW<[SBWriteResGroup59], (instregex "VPINSRWrmi")>;
+def: InstRW<[SBWriteResGroup59], (instregex "VPINSRWrm")>;
def: InstRW<[SBWriteResGroup59], (instregex "VPMAXSBrm")>;
def: InstRW<[SBWriteResGroup59], (instregex "VPMAXSDrm")>;
def: InstRW<[SBWriteResGroup59], (instregex "VPMAXSWrm")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=323352&r1=323351&r2=323352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Wed Jan 24 09:58:51 2018
@@ -1026,15 +1026,15 @@ def SKLWriteResGroup13 : SchedWriteRes<[
let ResourceCycles = [2];
}
def: InstRW<[SKLWriteResGroup13], (instregex "MMX_MOVQ2DQrr")>;
-def: InstRW<[SKLWriteResGroup13], (instregex "MMX_PINSRWirri")>;
+def: InstRW<[SKLWriteResGroup13], (instregex "MMX_PINSRWrr")>;
def: InstRW<[SKLWriteResGroup13], (instregex "PINSRBrr")>;
def: InstRW<[SKLWriteResGroup13], (instregex "PINSRDrr")>;
def: InstRW<[SKLWriteResGroup13], (instregex "PINSRQrr")>;
-def: InstRW<[SKLWriteResGroup13], (instregex "PINSRWrri")>;
+def: InstRW<[SKLWriteResGroup13], (instregex "PINSRWrr")>;
def: InstRW<[SKLWriteResGroup13], (instregex "VPINSRBrr")>;
def: InstRW<[SKLWriteResGroup13], (instregex "VPINSRDrr")>;
def: InstRW<[SKLWriteResGroup13], (instregex "VPINSRQrr")>;
-def: InstRW<[SKLWriteResGroup13], (instregex "VPINSRWrri")>;
+def: InstRW<[SKLWriteResGroup13], (instregex "VPINSRWrr")>;
def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> {
let Latency = 2;
@@ -1296,19 +1296,17 @@ def SKLWriteResGroup31 : SchedWriteRes<[
let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup31], (instregex "EXTRACTPSrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "MMX_PEXTRWirri")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "MMX_PEXTRWrr")>;
def: InstRW<[SKLWriteResGroup31], (instregex "PEXTRBrr")>;
def: InstRW<[SKLWriteResGroup31], (instregex "PEXTRDrr")>;
def: InstRW<[SKLWriteResGroup31], (instregex "PEXTRQrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "PEXTRWri")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "PEXTRWrr_REV")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "PEXTRWrr")>;
def: InstRW<[SKLWriteResGroup31], (instregex "PTESTrr")>;
def: InstRW<[SKLWriteResGroup31], (instregex "VEXTRACTPSrr")>;
def: InstRW<[SKLWriteResGroup31], (instregex "VPEXTRBrr")>;
def: InstRW<[SKLWriteResGroup31], (instregex "VPEXTRDrr")>;
def: InstRW<[SKLWriteResGroup31], (instregex "VPEXTRQrr")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "VPEXTRWri")>;
-def: InstRW<[SKLWriteResGroup31], (instregex "VPEXTRWrr_REV")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "VPEXTRWrr")>;
def: InstRW<[SKLWriteResGroup31], (instregex "VPTESTYrr")>;
def: InstRW<[SKLWriteResGroup31], (instregex "VPTESTrr")>;
@@ -1902,7 +1900,7 @@ def SKLWriteResGroup71 : SchedWriteRes<[
let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PALIGNR64irm")>;
-def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PINSRWirmi")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PINSRWrm")>;
def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PSHUFBrm64")>;
def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PSHUFWmi")>;
def: InstRW<[SKLWriteResGroup71], (instregex "MMX_PUNPCKHBWirm")>;
@@ -1918,7 +1916,7 @@ def: InstRW<[SKLWriteResGroup71], (instr
def: InstRW<[SKLWriteResGroup71], (instregex "PINSRBrm")>;
def: InstRW<[SKLWriteResGroup71], (instregex "PINSRDrm")>;
def: InstRW<[SKLWriteResGroup71], (instregex "PINSRQrm")>;
-def: InstRW<[SKLWriteResGroup71], (instregex "PINSRWrmi")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "PINSRWrm")>;
def: InstRW<[SKLWriteResGroup71], (instregex "PMOVSXBDrm")>;
def: InstRW<[SKLWriteResGroup71], (instregex "PMOVSXBQrm")>;
def: InstRW<[SKLWriteResGroup71], (instregex "PMOVSXBWrm")>;
@@ -1938,7 +1936,7 @@ def: InstRW<[SKLWriteResGroup71], (instr
def: InstRW<[SKLWriteResGroup71], (instregex "VPINSRBrm")>;
def: InstRW<[SKLWriteResGroup71], (instregex "VPINSRDrm")>;
def: InstRW<[SKLWriteResGroup71], (instregex "VPINSRQrm")>;
-def: InstRW<[SKLWriteResGroup71], (instregex "VPINSRWrmi")>;
+def: InstRW<[SKLWriteResGroup71], (instregex "VPINSRWrm")>;
def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVSXBDrm")>;
def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVSXBQrm")>;
def: InstRW<[SKLWriteResGroup71], (instregex "VPMOVSXBWrm")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=323352&r1=323351&r2=323352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Wed Jan 24 09:58:51 2018
@@ -1524,11 +1524,11 @@ def SKXWriteResGroup13 : SchedWriteRes<[
let ResourceCycles = [2];
}
def: InstRW<[SKXWriteResGroup13], (instregex "MMX_MOVQ2DQrr")>;
-def: InstRW<[SKXWriteResGroup13], (instregex "MMX_PINSRWirri")>;
+def: InstRW<[SKXWriteResGroup13], (instregex "MMX_PINSRWrr")>;
def: InstRW<[SKXWriteResGroup13], (instregex "PINSRBrr")>;
def: InstRW<[SKXWriteResGroup13], (instregex "PINSRDrr")>;
def: InstRW<[SKXWriteResGroup13], (instregex "PINSRQrr")>;
-def: InstRW<[SKXWriteResGroup13], (instregex "PINSRWrri")>;
+def: InstRW<[SKXWriteResGroup13], (instregex "PINSRWrr")>;
def: InstRW<[SKXWriteResGroup13], (instregex "VPINSRBZrr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup13], (instregex "VPINSRBrr")>;
def: InstRW<[SKXWriteResGroup13], (instregex "VPINSRDZrr(b?)(k?)(z?)")>;
@@ -1536,7 +1536,7 @@ def: InstRW<[SKXWriteResGroup13], (instr
def: InstRW<[SKXWriteResGroup13], (instregex "VPINSRQZrr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup13], (instregex "VPINSRQrr")>;
def: InstRW<[SKXWriteResGroup13], (instregex "VPINSRWZrr(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup13], (instregex "VPINSRWrri")>;
+def: InstRW<[SKXWriteResGroup13], (instregex "VPINSRWrr")>;
def SKXWriteResGroup14 : SchedWriteRes<[SKXPort05]> {
let Latency = 2;
@@ -2097,12 +2097,11 @@ def SKXWriteResGroup33 : SchedWriteRes<[
let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup33], (instregex "EXTRACTPSrr")>;
-def: InstRW<[SKXWriteResGroup33], (instregex "MMX_PEXTRWirri")>;
+def: InstRW<[SKXWriteResGroup33], (instregex "MMX_PEXTRWrr")>;
def: InstRW<[SKXWriteResGroup33], (instregex "PEXTRBrr")>;
def: InstRW<[SKXWriteResGroup33], (instregex "PEXTRDrr")>;
def: InstRW<[SKXWriteResGroup33], (instregex "PEXTRQrr")>;
-def: InstRW<[SKXWriteResGroup33], (instregex "PEXTRWri")>;
-def: InstRW<[SKXWriteResGroup33], (instregex "PEXTRWrr_REV")>;
+def: InstRW<[SKXWriteResGroup33], (instregex "PEXTRWrr")>;
def: InstRW<[SKXWriteResGroup33], (instregex "PTESTrr")>;
def: InstRW<[SKXWriteResGroup33], (instregex "VEXTRACTPSZrr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup33], (instregex "VEXTRACTPSrr")>;
@@ -2113,8 +2112,7 @@ def: InstRW<[SKXWriteResGroup33], (instr
def: InstRW<[SKXWriteResGroup33], (instregex "VPEXTRQZrr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup33], (instregex "VPEXTRQrr")>;
def: InstRW<[SKXWriteResGroup33], (instregex "VPEXTRWZrr")>;
-def: InstRW<[SKXWriteResGroup33], (instregex "VPEXTRWri")>;
-def: InstRW<[SKXWriteResGroup33], (instregex "VPEXTRWrr_REV")>;
+def: InstRW<[SKXWriteResGroup33], (instregex "VPEXTRWrr")>;
def: InstRW<[SKXWriteResGroup33], (instregex "VPTESTYrr")>;
def: InstRW<[SKXWriteResGroup33], (instregex "VPTESTrr")>;
@@ -3078,7 +3076,7 @@ def SKXWriteResGroup75 : SchedWriteRes<[
let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup75], (instregex "MMX_PALIGNR64irm")>;
-def: InstRW<[SKXWriteResGroup75], (instregex "MMX_PINSRWirmi")>;
+def: InstRW<[SKXWriteResGroup75], (instregex "MMX_PINSRWrm")>;
def: InstRW<[SKXWriteResGroup75], (instregex "MMX_PSHUFBrm64")>;
def: InstRW<[SKXWriteResGroup75], (instregex "MMX_PSHUFWmi")>;
def: InstRW<[SKXWriteResGroup75], (instregex "MMX_PUNPCKHBWirm")>;
@@ -3094,7 +3092,7 @@ def: InstRW<[SKXWriteResGroup75], (instr
def: InstRW<[SKXWriteResGroup75], (instregex "PINSRBrm")>;
def: InstRW<[SKXWriteResGroup75], (instregex "PINSRDrm")>;
def: InstRW<[SKXWriteResGroup75], (instregex "PINSRQrm")>;
-def: InstRW<[SKXWriteResGroup75], (instregex "PINSRWrmi")>;
+def: InstRW<[SKXWriteResGroup75], (instregex "PINSRWrm")>;
def: InstRW<[SKXWriteResGroup75], (instregex "PMOVSXBDrm")>;
def: InstRW<[SKXWriteResGroup75], (instregex "PMOVSXBQrm")>;
def: InstRW<[SKXWriteResGroup75], (instregex "PMOVSXBWrm")>;
@@ -3122,7 +3120,7 @@ def: InstRW<[SKXWriteResGroup75], (instr
def: InstRW<[SKXWriteResGroup75], (instregex "VPINSRQZrm(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup75], (instregex "VPINSRQrm")>;
def: InstRW<[SKXWriteResGroup75], (instregex "VPINSRWZrm(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup75], (instregex "VPINSRWrmi")>;
+def: InstRW<[SKXWriteResGroup75], (instregex "VPINSRWrm")>;
def: InstRW<[SKXWriteResGroup75], (instregex "VPMOVSXBDrm")>;
def: InstRW<[SKXWriteResGroup75], (instregex "VPMOVSXBQrm")>;
def: InstRW<[SKXWriteResGroup75], (instregex "VPMOVSXBWrm")>;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=323352&r1=323351&r2=323352&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td Wed Jan 24 09:58:51 2018
@@ -1031,7 +1031,7 @@ def ZnWritePEXTRr : SchedWriteRes<[ZnFPU
let Latency = 2;
let ResourceCycles = [1, 2];
}
-def : InstRW<[ZnWritePEXTRr], (instregex "PEXTR(B|W|D|Q)rr", "MMX_PEXTRWirri")>;
+def : InstRW<[ZnWritePEXTRr], (instregex "PEXTR(B|W|D|Q)rr", "MMX_PEXTRWrr")>;
def ZnWritePEXTRm : SchedWriteRes<[ZnAGU, ZnFPU12, ZnFPU2]> {
let Latency = 5;
Modified: llvm/trunk/test/CodeGen/X86/evex-to-vex-compress.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/evex-to-vex-compress.mir?rev=323352&r1=323351&r2=323352&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/evex-to-vex-compress.mir (original)
+++ llvm/trunk/test/CodeGen/X86/evex-to-vex-compress.mir Wed Jan 24 09:58:51 2018
@@ -2088,7 +2088,7 @@ body: |
%rax = VPEXTRQZrr %xmm0, 1
; CHECK: VPEXTRWmr %rdi, 1, %noreg, 0, %noreg, %xmm0, 3
VPEXTRWZmr %rdi, 1, %noreg, 0, %noreg, %xmm0, 3
- ; CHECK: %eax = VPEXTRWri %xmm0, 1
+ ; CHECK: %eax = VPEXTRWrr %xmm0, 1
%eax = VPEXTRWZrr %xmm0, 1
; CHECK: %eax = VPEXTRWrr_REV %xmm0, 1
%eax = VPEXTRWZrr_REV %xmm0, 1
@@ -2104,9 +2104,9 @@ body: |
%xmm0 = VPINSRQZrm %xmm0, %rsi, 1, %noreg, 0, %noreg, 3
; CHECK: %xmm0 = VPINSRQrr %xmm0, %rdi, 5
%xmm0 = VPINSRQZrr %xmm0, %rdi, 5
- ; CHECK: %xmm0 = VPINSRWrmi %xmm0, %rsi, 1, %noreg, 0, %noreg, 3
+ ; CHECK: %xmm0 = VPINSRWrm %xmm0, %rsi, 1, %noreg, 0, %noreg, 3
%xmm0 = VPINSRWZrm %xmm0, %rsi, 1, %noreg, 0, %noreg, 3
- ; CHECK: %xmm0 = VPINSRWrri %xmm0, %edi, 5
+ ; CHECK: %xmm0 = VPINSRWrr %xmm0, %edi, 5
%xmm0 = VPINSRWZrr %xmm0, %edi, 5
; CHECK: %xmm0 = VSQRTSDm %xmm0, %noreg, %noreg, %noreg, %noreg, %noreg
%xmm0 = VSQRTSDZm %xmm0, %noreg, %noreg, %noreg, %noreg, %noreg
Modified: llvm/trunk/test/MC/X86/x86_64-asm-match.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86_64-asm-match.s?rev=323352&r1=323351&r2=323352&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86_64-asm-match.s (original)
+++ llvm/trunk/test/MC/X86/x86_64-asm-match.s Wed Jan 24 09:58:51 2018
@@ -17,11 +17,11 @@
// CHECK: Matching formal operand class MCK_FR32 against actual operand at index 3 (Reg:xmm2): match success using generic matcher
// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 4: actual operand index out of range Opcode result: complete match, selecting this opcode
// CHECK: AsmMatcher: found 4 encodings with mnemonic 'pinsrw'
-// CHECK: Trying to match opcode MMX_PINSRWirri
+// CHECK: Trying to match opcode MMX_PINSRWrr
// CHECK: Matching formal operand class MCK_ImmUnsignedi8 against actual operand at index 1 (Imm:3): match success using generic matcher
// CHECK: Matching formal operand class MCK_GR32orGR64 against actual operand at index 2 (Reg:ecx): match success using generic matcher
// CHECK: Matching formal operand class MCK_VR64 against actual operand at index 3 (Reg:xmm5): Opcode result: multiple operand mismatches, ignoring this opcode
-// CHECK: Trying to match opcode PINSRWrri
+// CHECK: Trying to match opcode PINSRWrr
// CHECK: Matching formal operand class MCK_ImmUnsignedi8 against actual operand at index 1 (Imm:3): match success using generic matcher
// CHECK: Matching formal operand class MCK_GR32orGR64 against actual operand at index 2 (Reg:ecx): match success using generic matcher
// CHECK: Matching formal operand class MCK_FR32 against actual operand at index 3 (Reg:xmm5): match success using generic matcher
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