[llvm] r323312 - [DAGCombiner] Bail out if vector size is not a multiple

[Sven van Haastregt via llvm-commits]

Author: svenvh
Date: Wed Jan 24 01:53:47 2018
New Revision: 323312

URL: http://llvm.org/viewvc/llvm-project?rev=323312&view=rev
Log:
[DAGCombiner] Bail out if vector size is not a multiple

For the included test case, the DAG transformation
  concat_vectors(scalar, undef) -> scalar_to_vector(sclr)
would attempt to create a v2i32 vector for a v9i8
concat_vector.  Bail out to avoid creating a bitcast with
mismatching sizes later on.

Differential Revision: https://reviews.llvm.org/D42379

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/AMDGPU/concat_vectors.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=323312&r1=323311&r2=323312&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Jan 24 01:53:47 2018
@@ -15188,6 +15188,10 @@ SDValue DAGCombiner::visitCONCAT_VECTORS
       if (!SclTy.isFloatingPoint() && !SclTy.isInteger())
         return SDValue();
 
+      // Bail out if the vector size is not a multiple of the scalar size.
+      if (VT.getSizeInBits() % SclTy.getSizeInBits())
+        return SDValue();
+
       unsigned VNTNumElms = VT.getSizeInBits() / SclTy.getSizeInBits();
       if (VNTNumElms < 2)
         return SDValue();

Modified: llvm/trunk/test/CodeGen/AMDGPU/concat_vectors.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/concat_vectors.ll?rev=323312&r1=323311&r2=323312&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/concat_vectors.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/concat_vectors.ll Wed Jan 24 01:53:47 2018
@@ -294,3 +294,15 @@ bb:
   store <8 x float> %tmp2, <8 x float> addrspace(1)* %out, align 32
   ret void
 }
+
+; FUNC-LABEL: {{^}}concat_vector_crash2:
+; SI: s_endpgm
+define amdgpu_kernel void @concat_vector_crash2(<8 x i8> addrspace(1)* %out, i32 addrspace(1)* %in) {
+  %tmp = load i32, i32 addrspace(1)* %in, align 1
+  %tmp1 = trunc i32 %tmp to i24
+  %tmp2 = bitcast i24 %tmp1 to <3 x i8>
+  %tmp3 = shufflevector <3 x i8> %tmp2, <3 x i8> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 undef, i32 undef>
+  %tmp4 = shufflevector <8 x i8> %tmp3, <8 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 7, i8 8>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 14, i32 15>
+  store <8 x i8> %tmp4, <8 x i8> addrspace(1)* %out, align 8
+  ret void
+}