[PATCH] D42465: [RFC][CallingConv] Add CCAssignToRegWithType Calling Convention Interface

[Shiva Chen via Phabricator via llvm-commits]

shiva0217 created this revision.
shiva0217 added reviewers: stoklund, rnk, venkatra, asb.
Herald added subscribers: niosHD, sabuasal, apazos, jordy.potman.lists, simoncook, johnrusso, rbar, fedor.sergeev, kbarton, aheejin, jgravelle-google, sbc100, javed.absar, nhaehnle, nemanjai, sdardis, dylanmckay, jyknight, dschuff, arsenm, jfb, jholewinski.

For the target have f64 registers, but have calling convention passing the f64 type by i32 registers, legalizer will not split the argument.

The target has to define custom calling convention functions to assign f64 type to two location record by CCValAssign structure.

LowerFormalArgument has to generate SDNode to describe how to get input parameters and store in InVals array. Normally, one InputArg assigns to one location, but for the above case, the target has to add custom code to generate SDNode for two locations. Lowercall will need similar effort to deal with it.

If we could split the argument to i32 type during analyzing arguments, we could eliminate the effort and handle it as normal i32 type arguments.

The idea is to add CCAssignToRegWithType interface
which could describe as

  CCIfType<[f64], CCAssignToRegWithType<i32, [I0, I1, I2, I3, I4, I5]>>,

The semantic will be: if the first part of i32 type could assign to a register, split the argument into two i32 arguments.

The tablegen result will be:

  if (LocVT == MVT::f64) {
    LocVT = MVT::i32;
    static const MCPhysReg RegList2[] = {
      SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
  };
  if (unsigned Reg = State.AllocateReg(RegList2)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      State.setCCSplitType(MVT::i32);
      State.setCCSplit();
      return false;
  } 
   

If State.isCCSplit() is true, call CCState::SplitInputArg and CCState::SplitOutputArg functions to split the argument.
The patch use sparc32 to apply the interface and pass the codegen test cases in llvm/test/Codegen/SPARC.
Any suggestion would be helpful.


Repository:
  rL LLVM

https://reviews.llvm.org/D42465

Files:
  include/llvm/CodeGen/CallingConvLower.h
  include/llvm/CodeGen/TargetLowering.h
  include/llvm/Target/TargetCallingConv.td
  lib/CodeGen/CallingConvLower.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AArch64/AArch64ISelLowering.h
  lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  lib/Target/AMDGPU/AMDGPUISelLowering.h
  lib/Target/AMDGPU/R600ISelLowering.cpp
  lib/Target/AMDGPU/R600ISelLowering.h
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Target/AMDGPU/SIISelLowering.h
  lib/Target/ARC/ARCISelLowering.cpp
  lib/Target/ARC/ARCISelLowering.h
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/ARMISelLowering.h
  lib/Target/AVR/AVRISelLowering.cpp
  lib/Target/AVR/AVRISelLowering.h
  lib/Target/BPF/BPFISelLowering.cpp
  lib/Target/BPF/BPFISelLowering.h
  lib/Target/Hexagon/HexagonISelLowering.cpp
  lib/Target/Hexagon/HexagonISelLowering.h
  lib/Target/Lanai/LanaiISelLowering.cpp
  lib/Target/Lanai/LanaiISelLowering.h
  lib/Target/MSP430/MSP430ISelLowering.cpp
  lib/Target/MSP430/MSP430ISelLowering.h
  lib/Target/Mips/MipsCCState.h
  lib/Target/Mips/MipsISelLowering.cpp
  lib/Target/Mips/MipsISelLowering.h
  lib/Target/NVPTX/NVPTXISelLowering.cpp
  lib/Target/NVPTX/NVPTXISelLowering.h
  lib/Target/Nios2/Nios2ISelLowering.cpp
  lib/Target/Nios2/Nios2ISelLowering.h
  lib/Target/PowerPC/PPCISelLowering.cpp
  lib/Target/PowerPC/PPCISelLowering.h
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  lib/Target/Sparc/SparcCallingConv.td
  lib/Target/Sparc/SparcISelLowering.cpp
  lib/Target/Sparc/SparcISelLowering.h
  lib/Target/SystemZ/SystemZCallingConv.h
  lib/Target/SystemZ/SystemZISelLowering.cpp
  lib/Target/SystemZ/SystemZISelLowering.h
  lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
  lib/Target/WebAssembly/WebAssemblyISelLowering.h
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86ISelLowering.h
  lib/Target/XCore/XCoreISelLowering.cpp
  lib/Target/XCore/XCoreISelLowering.h
  test/CodeGen/SPARC/32abi.ll
  utils/TableGen/CallingConvEmitter.cpp

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