[llvm] r323302 - [NFC] fix trivial typos in comments
Hiroshi Inoue via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 23 21:04:35 PST 2018
Author: inouehrs
Date: Tue Jan 23 21:04:35 2018
New Revision: 323302
URL: http://llvm.org/viewvc/llvm-project?rev=323302&view=rev
Log:
[NFC] fix trivial typos in comments
"the the" -> "the"
Modified:
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h
llvm/trunk/test/CodeGen/AArch64/arm64-stp-aa.ll
llvm/trunk/test/CodeGen/AMDGPU/sgpr-copy.ll
llvm/trunk/test/CodeGen/Hexagon/swp-epilog-reuse-1.ll
llvm/trunk/test/CodeGen/Mips/cconv/callee-saved-float.ll
llvm/trunk/test/Transforms/GVN/PRE/load-pre-licm.ll
llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h?rev=323302&r1=323301&r2=323302&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h Tue Jan 23 21:04:35 2018
@@ -44,7 +44,7 @@ private:
const SIRegisterInfo RI;
const SISubtarget &ST;
- // The the inverse predicate should have the negative value.
+ // The inverse predicate should have the negative value.
enum BranchPredicate {
INVALID_BR = 0,
SCC_TRUE = 1,
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-stp-aa.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-stp-aa.ll?rev=323302&r1=323301&r2=323302&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-stp-aa.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-stp-aa.ll Tue Jan 23 21:04:35 2018
@@ -112,7 +112,7 @@ define double @stp_double_aa_after(doubl
; Check that the stores %c and %d are paired after the fadd instruction,
; and then the stores %a and %d are paired after proving that they do not
-; depend on the the (%c, %d) pair.
+; depend on the (%c, %d) pair.
;
; CHECK-LABEL: st1:
; CHECK: stp q0, q1, [x{{[0-9]+}}]
Modified: llvm/trunk/test/CodeGen/AMDGPU/sgpr-copy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/sgpr-copy.ll?rev=323302&r1=323301&r2=323302&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/sgpr-copy.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/sgpr-copy.ll Tue Jan 23 21:04:35 2018
@@ -379,7 +379,7 @@ bb71:
ret void
}
-; Check the the resource descriptor is stored in an sgpr.
+; Check the resource descriptor is stored in an sgpr.
; CHECK-LABEL: {{^}}mimg_srsrc_sgpr:
; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
define amdgpu_ps void @mimg_srsrc_sgpr([34 x <8 x i32>] addrspace(2)* byval %arg) #0 {
@@ -394,7 +394,7 @@ bb:
ret void
}
-; Check the the sampler is stored in an sgpr.
+; Check the sampler is stored in an sgpr.
; CHECK-LABEL: {{^}}mimg_ssamp_sgpr:
; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
define amdgpu_ps void @mimg_ssamp_sgpr([17 x <4 x i32>] addrspace(2)* byval %arg) #0 {
Modified: llvm/trunk/test/CodeGen/Hexagon/swp-epilog-reuse-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-epilog-reuse-1.ll?rev=323302&r1=323301&r2=323302&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/swp-epilog-reuse-1.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/swp-epilog-reuse-1.ll Tue Jan 23 21:04:35 2018
@@ -4,7 +4,7 @@
; Test that the pipeliner reuses an existing Phi when generating the epilog
; block. In this case, the original loops has a Phi whose operand is another
; Phi. When the loop is pipelined, the Phi that generates the operand value
-; is used in two stages. This means the the Phi for the second stage can
+; is used in two stages. This means the Phi for the second stage can
; be reused. The bug causes an assert due to an invalid virtual register error
; in the live variable analysis.
Modified: llvm/trunk/test/CodeGen/Mips/cconv/callee-saved-float.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cconv/callee-saved-float.ll?rev=323302&r1=323301&r2=323302&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/cconv/callee-saved-float.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/cconv/callee-saved-float.ll Tue Jan 23 21:04:35 2018
@@ -20,7 +20,7 @@
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -filetype=obj < %s -o - | llvm-objdump -no-show-raw-insn -arch mips -mcpu=mips32r6 -mattr=micromips -d - | FileCheck --check-prefix=MM32R6 %s
-; Test the the callee-saved registers are callee-saved as specified by section
+; Test the callee-saved registers are callee-saved as specified by section
; 2 of the MIPSpro N32 Handbook and section 3 of the SYSV ABI spec.
define void @fpu_clobber() nounwind {
Modified: llvm/trunk/test/Transforms/GVN/PRE/load-pre-licm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/PRE/load-pre-licm.ll?rev=323302&r1=323301&r2=323302&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/GVN/PRE/load-pre-licm.ll (original)
+++ llvm/trunk/test/Transforms/GVN/PRE/load-pre-licm.ll Tue Jan 23 21:04:35 2018
@@ -88,7 +88,7 @@ merge:
; TODO: at the moment, our anticipation check does not handle anything
; other than straight-line unconditional fallthrough. This particular
; case could be solved through either a backwards anticipation walk or
-; use of the the "safe to speculate" status (if we annotate the param)
+; use of the "safe to speculate" status (if we annotate the param)
define i32 @test3(i1 %cnd, i32* %p) {
entry:
; CHECK-LABEL: @test3
Modified: llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp?rev=323302&r1=323301&r2=323302&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp Tue Jan 23 21:04:35 2018
@@ -2651,7 +2651,7 @@ private:
/// Takes a sequence of \p Rules and group them based on the predicates
/// they share. \p StorageGroupMatcher is used as a memory container
- /// for the the group that are created as part of this process.
+ /// for the group that are created as part of this process.
/// The optimization process does not change the relative order of
/// the rules. In particular, we don't try to share predicates if
/// that means reordering the rules (e.g., we won't group R1 and R3
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